From patchwork Fri Sep 25 11:55:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manish Chopra X-Patchwork-Id: 78839 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 74A25A04C0; Fri, 25 Sep 2020 13:58:07 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 54FF31C297; Fri, 25 Sep 2020 13:58:07 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 162791C243 for ; Fri, 25 Sep 2020 13:58:05 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08PBtInk010841; Fri, 25 Sep 2020 04:58:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; 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Fri, 25 Sep 2020 04:58:00 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Sep 2020 04:58:00 -0700 Received: from dut1171.mv.qlogic.com (unknown [10.112.88.18]) by maili.marvell.com (Postfix) with ESMTP id C2B353F703F; Fri, 25 Sep 2020 04:58:00 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 08PBw0n5004265; Fri, 25 Sep 2020 04:58:00 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 08PBw0ht004263; Fri, 25 Sep 2020 04:58:00 -0700 From: Manish Chopra To: , , , CC: , , , , , , , , Date: Fri, 25 Sep 2020 04:55:08 -0700 Message-ID: <20200925115508.4179-7-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200925115508.4179-1-manishc@marvell.com> References: <20200925115508.4179-1-manishc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-25_08:2020-09-24, 2020-09-25 signatures=0 Subject: [dpdk-dev] [PATCH v6 6/6] net/qede: add VF FLR support X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch adds required bit to handle VF FLR indication from Management FW (MFW) of the device With that VFs were able to load in VM (VF attached as PCI passthrough to the guest VM) followed by FLR successfully Updated the docs/guides with the feature support Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh Signed-off-by: Rasesh Mody --- doc/guides/nics/features/qede.ini | 1 + doc/guides/nics/qede.rst | 7 +------ drivers/net/qede/base/bcm_osal.c | 5 +++++ drivers/net/qede/base/bcm_osal.h | 4 +++- drivers/net/qede/qede_sriov.c | 18 ++++++++++++++++++ 5 files changed, 28 insertions(+), 7 deletions(-) diff --git a/doc/guides/nics/features/qede.ini b/doc/guides/nics/features/qede.ini index f8716523e..46fba8e6c 100644 --- a/doc/guides/nics/features/qede.ini +++ b/doc/guides/nics/features/qede.ini @@ -32,6 +32,7 @@ Basic stats = Y Extended stats = Y Stats per queue = Y Registers dump = Y +SR-IOV = Y Multiprocess aware = Y Linux UIO = Y Linux VFIO = Y diff --git a/doc/guides/nics/qede.rst b/doc/guides/nics/qede.rst index 5b2f86895..e874915c2 100644 --- a/doc/guides/nics/qede.rst +++ b/doc/guides/nics/qede.rst @@ -34,18 +34,13 @@ Supported Features - VLAN offload - Filtering and stripping - N-tuple filter and flow director (limited support) - NPAR (NIC Partitioning) -- SR-IOV VF +- SR-IOV PF and VF - GRE Tunneling offload - GENEVE Tunneling offload - VXLAN Tunneling offload - MPLSoUDP Tx Tunneling offload - Generic flow API -Non-supported Features ----------------------- - -- SR-IOV PF - Co-existence considerations --------------------------- diff --git a/drivers/net/qede/base/bcm_osal.c b/drivers/net/qede/base/bcm_osal.c index ef47339df..44a8692f5 100644 --- a/drivers/net/qede/base/bcm_osal.c +++ b/drivers/net/qede/base/bcm_osal.c @@ -29,6 +29,11 @@ int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn) return rc; } +void osal_vf_flr_update(struct ecore_hwfn *p_hwfn) +{ + qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); +} + void osal_poll_mode_dpc(osal_int_ptr_t hwfn_cookie) { struct ecore_hwfn *p_hwfn = (struct ecore_hwfn *)hwfn_cookie; diff --git a/drivers/net/qede/base/bcm_osal.h b/drivers/net/qede/base/bcm_osal.h index e7212f40c..575d4d099 100644 --- a/drivers/net/qede/base/bcm_osal.h +++ b/drivers/net/qede/base/bcm_osal.h @@ -348,7 +348,9 @@ u32 qede_find_first_zero_bit(u32 *bitmap, u32 length); /* SR-IOV channel */ int osal_pf_vf_msg(struct ecore_hwfn *p_hwfn); -#define OSAL_VF_FLR_UPDATE(hwfn) nothing +void osal_vf_flr_update(struct ecore_hwfn *p_hwfn); +#define OSAL_VF_FLR_UPDATE(hwfn) \ + osal_vf_flr_update(hwfn) #define OSAL_VF_SEND_MSG2PF(dev, done, msg, reply_addr, msg_size, reply_size) 0 #define OSAL_VF_CQE_COMPLETION(_dev_p, _cqe, _protocol) (0) #define OSAL_PF_VF_MSG(hwfn, vfid) \ diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c index 93f7a2a55..0b99a8d6f 100644 --- a/drivers/net/qede/qede_sriov.c +++ b/drivers/net/qede/qede_sriov.c @@ -151,6 +151,7 @@ static void qed_handle_bulletin_post(struct ecore_hwfn *hwfn) void qed_iov_pf_task(void *arg) { struct ecore_hwfn *p_hwfn = arg; + int rc; if (OSAL_GET_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags)) { OSAL_CLEAR_BIT(QED_IOV_WQ_MSG_FLAG, &p_hwfn->iov_task_flags); @@ -163,6 +164,23 @@ void qed_iov_pf_task(void *arg) &p_hwfn->iov_task_flags); qed_handle_bulletin_post(p_hwfn); } + + if (OSAL_GET_BIT(QED_IOV_WQ_FLR_FLAG, &p_hwfn->iov_task_flags)) { + struct ecore_ptt *p_ptt = ecore_ptt_acquire(p_hwfn); + + OSAL_CLEAR_BIT(QED_IOV_WQ_FLR_FLAG, &p_hwfn->iov_task_flags); + + if (!p_ptt) { + qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); + return; + } + + rc = ecore_iov_vf_flr_cleanup(p_hwfn, p_ptt); + if (rc) + qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG); + + ecore_ptt_release(p_hwfn, p_ptt); + } } int qed_schedule_iov(struct ecore_hwfn *p_hwfn, enum qed_iov_wq_flag flag)