From patchwork Fri Sep 25 11:55:05 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manish Chopra X-Patchwork-Id: 78836 X-Patchwork-Delegate: jerinj@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id F29DBA04C0; Fri, 25 Sep 2020 13:56:51 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id DB0E51C244; Fri, 25 Sep 2020 13:56:51 +0200 (CEST) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id CCB281C243 for ; Fri, 25 Sep 2020 13:56:50 +0200 (CEST) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 08PBtIna010841; Fri, 25 Sep 2020 04:56:50 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=pfpt0220; bh=TAYwSOsJPJ8CqQwH7GFQNImrzbbAxUVhwBzbOMm0tj0=; b=J6GyyQJWlkEHRIq8ifk6Pdw8Cagfh8fFNondbG29Ma6036K5Raddfv9ln3W32VzYNcB0 zV0PvYQUZYFCSB2brE9Shx9vWeJD53WG5nHqvpsn2jpfCNeNoOzVnH1U0lqs3nmR1nS/ aS6HlOUusGFWCrUhe6CFhij4C6pW0/88Nt4048odqi3NwDNzI1OOEyZnN1ayjDW5wz5q r8mKV/WNhMmkcUTy9Ci2bQG0nMe9l0N1bAa7K9GQaeqbxVHsyEmr0255JVy28Fm7x/NL 10gwt6ztMHISCfh2DAUGqNoIrO0X8SLWiO/X0z5Rgf1H3oBEg+fvvKRbNLtX1zIp4ibH LQ== Received: from sc-exch03.marvell.com ([199.233.58.183]) by mx0b-0016f401.pphosted.com with ESMTP id 33nhgntb34-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Fri, 25 Sep 2020 04:56:50 -0700 Received: from DC5-EXCH02.marvell.com (10.69.176.39) by SC-EXCH03.marvell.com (10.93.176.83) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 25 Sep 2020 04:56:48 -0700 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 25 Sep 2020 04:56:48 -0700 Received: from dut1171.mv.qlogic.com (unknown [10.112.88.18]) by maili.marvell.com (Postfix) with ESMTP id 48EF13F703F; Fri, 25 Sep 2020 04:56:48 -0700 (PDT) Received: from dut1171.mv.qlogic.com (localhost [127.0.0.1]) by dut1171.mv.qlogic.com (8.14.7/8.14.7) with ESMTP id 08PBum4D004244; Fri, 25 Sep 2020 04:56:48 -0700 Received: (from root@localhost) by dut1171.mv.qlogic.com (8.14.7/8.14.7/Submit) id 08PBumAm004243; Fri, 25 Sep 2020 04:56:48 -0700 From: Manish Chopra To: , , , CC: , , , , , , , , Date: Fri, 25 Sep 2020 04:55:05 -0700 Message-ID: <20200925115508.4179-4-manishc@marvell.com> X-Mailer: git-send-email 2.12.0 In-Reply-To: <20200925115508.4179-1-manishc@marvell.com> References: <20200925115508.4179-1-manishc@marvell.com> MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-09-25_08:2020-09-24, 2020-09-25 signatures=0 Subject: [dpdk-dev] [PATCH v6 3/6] net/qede: configure VFs on hardware X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Based on number of VFs enabled at PCI, PF-PMD driver instance enables/configures those VFs from hardware perspective, such that in later patches they could get required HW access to communicate with PFs for slowpath configuration and run the fastpath themsleves. This patch also add two new qede IOV files [qede_sriov(.c|.h)] under qede directory to add non-base driver IOV APIs/contents there. Signed-off-by: Manish Chopra Signed-off-by: Igor Russkikh Signed-off-by: Rasesh Mody --- drivers/net/qede/meson.build | 1 + drivers/net/qede/qede_ethdev.c | 1 + drivers/net/qede/qede_ethdev.h | 1 + drivers/net/qede/qede_if.h | 1 + drivers/net/qede/qede_main.c | 1 + drivers/net/qede/qede_sriov.c | 85 ++++++++++++++++++++++++++++++++++ drivers/net/qede/qede_sriov.h | 9 ++++ 7 files changed, 99 insertions(+) create mode 100644 drivers/net/qede/qede_sriov.c create mode 100644 drivers/net/qede/qede_sriov.h diff --git a/drivers/net/qede/meson.build b/drivers/net/qede/meson.build index 05c9bff73..ff0ac0b03 100644 --- a/drivers/net/qede/meson.build +++ b/drivers/net/qede/meson.build @@ -11,6 +11,7 @@ sources = files( 'qede_rxtx.c', 'qede_debug.c', 'qede_regs.c', + 'qede_sriov.c', ) if cc.has_argument('-Wno-format-nonliteral') diff --git a/drivers/net/qede/qede_ethdev.c b/drivers/net/qede/qede_ethdev.c index 59f1746ee..27ec42e2c 100644 --- a/drivers/net/qede/qede_ethdev.c +++ b/drivers/net/qede/qede_ethdev.c @@ -2699,6 +2699,7 @@ static int qede_common_dev_init(struct rte_eth_dev *eth_dev, bool is_vf) adapter->vxlan.enable = false; adapter->geneve.enable = false; adapter->ipgre.enable = false; + qed_ops->sriov_configure(edev, pci_dev->max_vfs); } DP_INFO(edev, "MAC address : %02x:%02x:%02x:%02x:%02x:%02x\n", diff --git a/drivers/net/qede/qede_ethdev.h b/drivers/net/qede/qede_ethdev.h index 76c5dae3b..4fb77b05c 100644 --- a/drivers/net/qede/qede_ethdev.h +++ b/drivers/net/qede/qede_ethdev.h @@ -34,6 +34,7 @@ #include "base/ecore_l2.h" #include "base/ecore_vf.h" +#include "qede_sriov.h" #include "qede_logs.h" #include "qede_if.h" #include "qede_rxtx.h" diff --git a/drivers/net/qede/qede_if.h b/drivers/net/qede/qede_if.h index c5ae3fb2e..1693a243f 100644 --- a/drivers/net/qede/qede_if.h +++ b/drivers/net/qede/qede_if.h @@ -82,6 +82,7 @@ struct qed_eth_ops { const struct qed_common_ops *common; int (*fill_dev_info)(struct ecore_dev *edev, struct qed_dev_eth_info *info); + void (*sriov_configure)(struct ecore_dev *edev, int num_vfs); }; struct qed_link_params { diff --git a/drivers/net/qede/qede_main.c b/drivers/net/qede/qede_main.c index 94061ec11..c1135822b 100644 --- a/drivers/net/qede/qede_main.c +++ b/drivers/net/qede/qede_main.c @@ -821,6 +821,7 @@ const struct qed_common_ops qed_common_ops_pass = { const struct qed_eth_ops qed_eth_ops_pass = { INIT_STRUCT_FIELD(common, &qed_common_ops_pass), INIT_STRUCT_FIELD(fill_dev_info, &qed_fill_eth_dev_info), + INIT_STRUCT_FIELD(sriov_configure, &qed_sriov_configure), }; const struct qed_eth_ops *qed_get_eth_ops(void) diff --git a/drivers/net/qede/qede_sriov.c b/drivers/net/qede/qede_sriov.c new file mode 100644 index 000000000..ba4384e90 --- /dev/null +++ b/drivers/net/qede/qede_sriov.c @@ -0,0 +1,85 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2020 Marvell. + * All rights reserved. + * www.marvell.com + */ + +#include "qede_sriov.h" + +static void qed_sriov_enable_qid_config(struct ecore_hwfn *hwfn, + u16 vfid, + struct ecore_iov_vf_init_params *params) +{ + u16 num_pf_l2_queues, base, i; + + /* Since we have an equal resource distribution per-VF, and we assume + * PF has acquired its first queues, we start setting sequentially from + * there. + */ + num_pf_l2_queues = (u16)FEAT_NUM(hwfn, ECORE_PF_L2_QUE); + + base = num_pf_l2_queues + vfid * params->num_queues; + params->rel_vf_id = vfid; + + for (i = 0; i < params->num_queues; i++) { + params->req_rx_queue[i] = base + i; + params->req_tx_queue[i] = base + i; + } + + /* PF uses indices 0 for itself; Set vport/RSS afterwards */ + params->vport_id = vfid + 1; + params->rss_eng_id = vfid + 1; +} + +static void qed_sriov_enable(struct ecore_dev *edev, int num) +{ + struct ecore_iov_vf_init_params params; + struct ecore_hwfn *p_hwfn; + struct ecore_ptt *p_ptt; + int i, j, rc; + + if ((u32)num >= RESC_NUM(&edev->hwfns[0], ECORE_VPORT)) { + DP_NOTICE(edev, false, "Can start at most %d VFs\n", + RESC_NUM(&edev->hwfns[0], ECORE_VPORT) - 1); + return; + } + + OSAL_MEMSET(¶ms, 0, sizeof(struct ecore_iov_vf_init_params)); + + for_each_hwfn(edev, j) { + int feat_num; + + p_hwfn = &edev->hwfns[j]; + p_ptt = ecore_ptt_acquire(p_hwfn); + feat_num = FEAT_NUM(p_hwfn, ECORE_VF_L2_QUE) / num; + + params.num_queues = OSAL_MIN_T(int, feat_num, 16); + + for (i = 0; i < num; i++) { + if (!ecore_iov_is_valid_vfid(p_hwfn, i, false, true)) + continue; + + qed_sriov_enable_qid_config(p_hwfn, i, ¶ms); + + rc = ecore_iov_init_hw_for_vf(p_hwfn, p_ptt, ¶ms); + if (rc) { + DP_ERR(edev, "Failed to enable VF[%d]\n", i); + ecore_ptt_release(p_hwfn, p_ptt); + return; + } + } + + ecore_ptt_release(p_hwfn, p_ptt); + } +} + +void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param) +{ + if (!IS_ECORE_SRIOV(edev)) { + DP_VERBOSE(edev, ECORE_MSG_IOV, "SR-IOV is not supported\n"); + return; + } + + if (num_vfs_param) + qed_sriov_enable(edev, num_vfs_param); +} diff --git a/drivers/net/qede/qede_sriov.h b/drivers/net/qede/qede_sriov.h new file mode 100644 index 000000000..6c85b1dd5 --- /dev/null +++ b/drivers/net/qede/qede_sriov.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * Copyright (c) 2020 Marvell. + * All rights reserved. + * www.marvell.com + */ + +#include "qede_ethdev.h" + +void qed_sriov_configure(struct ecore_dev *edev, int num_vfs_param);