[11/22] event/dlb2: add port setup
diff mbox series

Message ID 1599855987-25976-12-git-send-email-timothy.mcdaniel@intel.com
State Superseded
Delegated to: Jerin Jacob
Headers show
Series
  • Add DLB2 PMD
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Context Check Description
ci/checkpatch warning coding style issues

Commit Message

McDaniel, Timothy Sept. 11, 2020, 8:26 p.m. UTC
Configure the load balanded (ldb) or directed (dir) port.
The consumer queue (CQ) and producer port (PP) are also
set up here.

Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
---
 drivers/event/dlb2/dlb2.c                  | 527 +++++++++++++++++
 drivers/event/dlb2/dlb2_iface.c            |   9 +
 drivers/event/dlb2/dlb2_iface.h            |   8 +
 drivers/event/dlb2/pf/base/dlb2_resource.c | 921 +++++++++++++++++++++++++++++
 drivers/event/dlb2/pf/dlb2_main.c          |  28 +
 drivers/event/dlb2/pf/dlb2_pf.c            | 179 ++++++
 6 files changed, 1672 insertions(+)

Comments

Eads, Gage Oct. 7, 2020, 8:34 p.m. UTC | #1
> -----Original Message-----
> From: McDaniel, Timothy <timothy.mcdaniel@intel.com>
> Sent: Friday, September 11, 2020 3:26 PM
> Cc: dev@dpdk.org; Carrillo, Erik G <erik.g.carrillo@intel.com>; Eads, Gage
> <gage.eads@intel.com>; Van Haaren, Harry <harry.van.haaren@intel.com>;
> jerinj@marvell.com
> Subject: [PATCH 11/22] event/dlb2: add port setup
> 
> Configure the load balanded (ldb) or directed (dir) port.
> The consumer queue (CQ) and producer port (PP) are also
> set up here.
> 
> Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
> ---
>  drivers/event/dlb2/dlb2.c                  | 527 +++++++++++++++++
>  drivers/event/dlb2/dlb2_iface.c            |   9 +
>  drivers/event/dlb2/dlb2_iface.h            |   8 +
>  drivers/event/dlb2/pf/base/dlb2_resource.c | 921
> +++++++++++++++++++++++++++++
>  drivers/event/dlb2/pf/dlb2_main.c          |  28 +
>  drivers/event/dlb2/pf/dlb2_pf.c            | 179 ++++++
>  6 files changed, 1672 insertions(+)
> 
> diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
> index 366e194..a4c8833 100644
> --- a/drivers/event/dlb2/dlb2.c
> +++ b/drivers/event/dlb2/dlb2.c
> @@ -1043,6 +1043,532 @@ dlb2_eventdev_queue_setup(struct rte_eventdev
> *dev,
>  	return ret;
>  }
> 
> +static int
> +dlb2_init_consume_qe(struct dlb2_port *qm_port, char *mz_name)
> +{
> +	struct dlb2_cq_pop_qe *qe;
> +
> +	qe = rte_malloc(mz_name,
> +			DLB2_NUM_QES_PER_CACHE_LINE *
> +				sizeof(struct dlb2_cq_pop_qe),
> +			RTE_CACHE_LINE_SIZE);
> +
> +	if (qe == NULL)	{
> +		DLB2_LOG_ERR("dlb2: no memory for consume_qe\n");
> +		return -ENOMEM;
> +	}
> +	qm_port->consume_qe = qe;
> +
> +	memset(qe, 0, DLB2_NUM_QES_PER_CACHE_LINE *
> +	       sizeof(struct dlb2_cq_pop_qe));

You can use rte_zmalloc() instead (applies to other init_*_qe functions below too), and
no need to zero-init the fields again after the memset.

> +
> +	qe->qe_valid = 0;
> +	qe->qe_frag = 0;
> +	qe->qe_comp = 0;
> +	qe->cq_token = 1;
> +	/* Tokens value is 0-based; i.e. '0' returns 1 token, '1' returns 2,
> +	 * and so on.
> +	 */
> +	qe->tokens = 0;	/* set at run time */
> +	qe->meas_lat = 0;
> +	qe->no_dec = 0;
> +	/* Completion IDs are disabled */
> +	qe->cmp_id = 0;
> +
> +	return 0;
> +}
> +
> +static int
> +dlb2_init_int_arm_qe(struct dlb2_port *qm_port, char *mz_name)
> +{
> +	struct dlb2_enqueue_qe *qe;
> +
> +	qe = rte_malloc(mz_name,
> +			DLB2_NUM_QES_PER_CACHE_LINE *
> +				sizeof(struct dlb2_enqueue_qe),
> +			RTE_CACHE_LINE_SIZE);
> +
> +	if (qe == NULL) {
> +		DLB2_LOG_ERR("dlb2: no memory for complete_qe\n");
> +		return -ENOMEM;
> +	}
> +	qm_port->int_arm_qe = qe;
> +
> +	memset(qe, 0, DLB2_NUM_QES_PER_CACHE_LINE *
> +	       sizeof(struct dlb2_enqueue_qe));
> +
> +	/* V2 - INT ARM is CQ_TOKEN + FRAG */
> +	qe->qe_valid = 0;
> +	qe->qe_frag = 1;
> +	qe->qe_comp = 0;
> +	qe->cq_token = 1;
> +	qe->meas_lat = 0;
> +	qe->no_dec = 0;
> +	/* Completion IDs are disabled */
> +	qe->cmp_id = 0;
> +
> +	return 0;
> +}
> +
> +static int
> +dlb2_init_qe_mem(struct dlb2_port *qm_port, char *mz_name)
> +{
> +	int ret, sz;
> +
> +	sz = DLB2_NUM_QES_PER_CACHE_LINE * sizeof(struct
> dlb2_enqueue_qe);
> +
> +	qm_port->qe4 = rte_malloc(mz_name, sz, RTE_CACHE_LINE_SIZE);
> +
> +	if (qm_port->qe4 == NULL) {
> +		DLB2_LOG_ERR("dlb2: no qe4 memory\n");
> +		ret = -ENOMEM;
> +		goto error_exit;
> +	}
> +
> +	memset(qm_port->qe4, 0, sz);
> +
> +	ret = dlb2_init_int_arm_qe(qm_port, mz_name);
> +	if (ret < 0) {
> +		DLB2_LOG_ERR("dlb2: dlb2_init_int_arm_qe ret=%d\n",
> +			     ret);

This can fit on one line

> +		goto error_exit;
> +	}
> +
> +	ret = dlb2_init_consume_qe(qm_port, mz_name);
> +	if (ret < 0) {
> +		DLB2_LOG_ERR("dlb2: dlb2_init_consume_qe ret=%d\n",
> +			     ret);

This can fit on one line

> +		goto error_exit;
> +	}
> +
> +	return 0;
> +
> +error_exit:
> +
> +	dlb2_free_qe_mem(qm_port);
> +
> +	return ret;
> +}
> +
> +static int
> +dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,
> +			struct dlb2_eventdev_port *ev_port,
> +			uint32_t dequeue_depth,
> +			uint32_t enqueue_depth)
> +{
> +	struct dlb2_hw_dev *handle = &dlb2->qm_instance;
> +	struct dlb2_create_ldb_port_args cfg = {0};
> +	int ret;
> +	struct dlb2_port *qm_port = NULL;
> +	char mz_name[RTE_MEMZONE_NAMESIZE];
> +	uint32_t qm_port_id;
> +	uint16_t ldb_credit_high_watermark;
> +	uint16_t dir_credit_high_watermark;
> +
> +	if (handle == NULL)
> +		return -EINVAL;
> +
> +	if (dequeue_depth < DLB2_MIN_CQ_DEPTH ||
> +	    dequeue_depth > DLB2_MAX_INPUT_QUEUE_DEPTH) {
> +		DLB2_LOG_ERR("dlb2: invalid dequeue_depth, must be %d-
> %d\n",
> +			     DLB2_MIN_CQ_DEPTH,
> DLB2_MAX_INPUT_QUEUE_DEPTH);
> +		return -EINVAL;
> +	}
> +
> +	if (enqueue_depth < DLB2_MIN_ENQUEUE_DEPTH) {
> +		DLB2_LOG_ERR("dlb2: invalid enqueue_depth, must be at least
> %d\n",
> +			     DLB2_MIN_ENQUEUE_DEPTH);
> +		return -EINVAL;
> +	}

The dequeue and enqueue depth checks are suspiciously inconsistent -- only the dequeue
depth is compared against an upper bound. I suspect the enqueue upper bound check is missing
because it's already checked in both dlb2_eventdev_port_setup() and
rte_event_port_setup()...if that's the case, can the dequeue depth max check be dropped as well?

> +
> +	rte_spinlock_lock(&handle->resource_lock);
> +
> +	/* TODO - additional parameter validation */

Leftover TODO

> +	/* We round up to the next power of 2 if necessary */
> +	cfg.cq_depth = rte_align32pow2(dequeue_depth);
> +	cfg.cq_depth_threshold = 1;
> +
> +	cfg.cq_history_list_size =
> DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;
> +
> +	if (handle->cos_id == DLB2_COS_DEFAULT)
> +		cfg.cos_id = 0;
> +	else
> +		cfg.cos_id = handle->cos_id;
> +
> +	cfg.cos_strict = 0;
> +
> +	/* User controls the LDB high watermark via enqueue depth. The DIR
> high
> +	 * watermark is equal, unless the directed credit pool is too small.
> +	 */
> +	ldb_credit_high_watermark = enqueue_depth;
> +
> +	/* If there are no directed ports, the kernel driver will ignore this
> +	 * port's directed credit settings. Don't use enqueue_depth if it would
> +	 * require more directed credits than are available.
> +	 */
> +	dir_credit_high_watermark =
> +		RTE_MIN(enqueue_depth,
> +			handle->cfg.num_dir_credits / dlb2->num_ports);
> +
> +	/* Per QM values */
> +
> +	/* DEBUG
> +	 * DLB2_LOG_ERR("create ldb port - grp=%d, devId=%d\n",
> +	 * handle->cfg.domain_id, handle->device_id);
> +	 */

Leftover debug code

> +
> +	ret = dlb2_iface_ldb_port_create(handle, &cfg,  dlb2->poll_mode);
> +	if (ret < 0) {
> +		DLB2_LOG_ERR("dlb2: dlb2_ldb_port_create error, ret=%d
> (driver status: %s)\n",
> +			     ret, dlb2_error_strings[cfg.response.status]);
> +		goto error_exit;
> +	}
> +
> +	qm_port_id = cfg.response.id;
> +
> +	DLB2_LOG_DBG("dlb2: ev_port %d uses qm LB port %d <<<<<\n",
> +		     ev_port->id, qm_port_id);
> +
> +	qm_port = &ev_port->qm_port;
> +	qm_port->ev_port = ev_port; /* back ptr */
> +	qm_port->dlb2 = dlb2; /* back ptr */
> +	/*
> +	 * Allocate and init local qe struct(s).
> +	 * Note: MOVDIR64 requires the enqueue QE (qe4) to be aligned.
> +	 */
> +
> +	snprintf(mz_name, sizeof(mz_name), "%s_ldb_port%d",
> +		 handle->device_name,
> +		 ev_port->id);
> +

I see handle->device_name getting read here, in dlb2_hw_create_dir_port(),
and also in dlb2_eventdev_dump(), but I don't see it written anywhere?

> +	ret = dlb2_init_qe_mem(qm_port, mz_name);
> +	if (ret < 0) {
> +		DLB2_LOG_ERR("dlb2: init_qe_mem failed, ret=%d\n", ret);
> +		goto error_exit;
> +	}
> +
> +	qm_port->id = qm_port_id;
> +
> +	qm_port->cached_ldb_credits = 0;
> +	qm_port->cached_dir_credits = 0;
> +	/* CQs with depth < 8 use an 8-entry queue, but withhold credits so
> +	 * the effective depth is smaller.
> +	 */
> +	qm_port->cq_depth = cfg.cq_depth <= 8 ? 8 : cfg.cq_depth;
> +	qm_port->cq_idx = 0;
> +	qm_port->cq_idx_unmasked = 0;
> +
> +	if (dlb2->poll_mode == DLB2_CQ_POLL_MODE_SPARSE)
> +		qm_port->cq_depth_mask = (qm_port->cq_depth * 4) - 1;
> +	else
> +		qm_port->cq_depth_mask = qm_port->cq_depth - 1;
> +
> +	qm_port->gen_bit_shift = __builtin_popcount(qm_port-
> >cq_depth_mask);
> +	/* starting value of gen bit - it toggles at wrap time */
> +	qm_port->gen_bit = 1;
> +
> +	qm_port->int_armed = false;
> +
> +	/* Save off for later use in info and lookup APIs. */
> +	qm_port->qid_mappings = &dlb2->qm_ldb_to_ev_queue_id[0];
> +
> +	qm_port->dequeue_depth = dequeue_depth;
> +	qm_port->token_pop_thresh = dequeue_depth;
> +
> +	qm_port->owed_tokens = 0;
> +	qm_port->issued_releases = 0;
> +
> +	/* Save config message too. */
> +	rte_memcpy(&qm_port->cfg.ldb, &cfg, sizeof(cfg));

I know qm_port->cfg.ldb and cfg are the same type, but just for safety in case that
ever changes in the future...probably better to use sizeof() on the destination rather
than the source.

> +
> +	/* update state */
> +	qm_port->state = PORT_STARTED; /* enabled at create time */
> +	qm_port->config_state = DLB2_CONFIGURED;
> +
> +	qm_port->dir_credits = dir_credit_high_watermark;
> +	qm_port->ldb_credits = ldb_credit_high_watermark;
> +	qm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;
> +	qm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;
> +
> +	DLB2_LOG_DBG("dlb2: created ldb port %d, depth = %d, ldb credits=%d,
> dir credits=%d\n",
> +		     qm_port_id,
> +		     dequeue_depth,
> +		     qm_port->ldb_credits,
> +		     qm_port->dir_credits);
> +
> +	rte_spinlock_unlock(&handle->resource_lock);
> +
> +	return 0;
> +
> +error_exit:
> +
> +	if (qm_port)
> +		dlb2_free_qe_mem(qm_port);
> +
> +	rte_spinlock_unlock(&handle->resource_lock);
> +
> +	DLB2_LOG_ERR("dlb2: create ldb port failed!\n");
> +
> +	return ret;
> +}
> +
> +static void
> +dlb2_port_link_teardown(struct dlb2_eventdev *dlb2,
> +			struct dlb2_eventdev_port *ev_port)
> +{
> +	struct dlb2_eventdev_queue *ev_queue;
> +	int i;
> +
> +	for (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {
> +		if (!ev_port->link[i].valid)
> +			continue;
> +
> +		ev_queue = &dlb2->ev_queues[ev_port->link[i].queue_id];
> +
> +		ev_port->link[i].valid = false;
> +		ev_port->num_links--;
> +		ev_queue->num_links--;
> +	}
> +}
> +
> +static int
> +dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
> +			struct dlb2_eventdev_port *ev_port,
> +			uint32_t dequeue_depth,
> +			uint32_t enqueue_depth)
> +{
> +	struct dlb2_hw_dev *handle = &dlb2->qm_instance;
> +	struct dlb2_create_dir_port_args cfg = {0};
> +	int ret;
> +	struct dlb2_port *qm_port = NULL;
> +	char mz_name[RTE_MEMZONE_NAMESIZE];
> +	uint32_t qm_port_id;
> +	uint16_t ldb_credit_high_watermark;
> +	uint16_t dir_credit_high_watermark;
> +
> +	if (dlb2 == NULL || handle == NULL)
> +		return -EINVAL;
> +
> +	if (dequeue_depth < DLB2_MIN_CQ_DEPTH ||
> +	    dequeue_depth > DLB2_MAX_INPUT_QUEUE_DEPTH) {
> +		DLB2_LOG_ERR("dlb2: invalid dequeue_depth, must be %d-
> %d\n",
> +			     DLB2_MIN_CQ_DEPTH,
> DLB2_MAX_INPUT_QUEUE_DEPTH);
> +		return -EINVAL;
> +	}

Enqueue depth check needed?

> +
> +	rte_spinlock_lock(&handle->resource_lock);
> +
> +	/* Directed queues are configured at link time. */
> +	cfg.queue_id = -1;
> +
> +	/* We round up to the next power of 2 if necessary */
> +	cfg.cq_depth = rte_align32pow2(dequeue_depth);
> +	cfg.cq_depth_threshold = 1;
> +
> +	/* User controls the LDB high watermark via enqueue depth. The DIR
> high
> +	 * watermark is equal, unless the directed credit pool is too small.
> +	 */
> +	ldb_credit_high_watermark = enqueue_depth;
> +
> +	/* Don't use enqueue_depth if it would require more directed credits
> +	 * than are available.
> +	 */
> +	dir_credit_high_watermark =
> +		RTE_MIN(enqueue_depth,
> +			handle->cfg.num_dir_credits / dlb2->num_ports);
> +
> +	/* Per QM values */
> +
> +	ret = dlb2_iface_dir_port_create(handle, &cfg,  dlb2->poll_mode);
> +	if (ret < 0) {
> +		DLB2_LOG_ERR("dlb2: dlb2_dir_port_create error, ret=%d (driver
> status: %s)\n",
> +			     ret, dlb2_error_strings[cfg.response.status]);
> +		goto error_exit;
> +	}
> +
> +	qm_port_id = cfg.response.id;
> +
> +	DLB2_LOG_DBG("dlb2: ev_port %d uses qm DIR port %d <<<<<\n",
> +		     ev_port->id, qm_port_id);
> +
> +	qm_port = &ev_port->qm_port;
> +	qm_port->ev_port = ev_port; /* back ptr */
> +	qm_port->dlb2 = dlb2;  /* back ptr */
> +
> +	/*
> +	 * Init local qe struct(s).
> +	 * Note: MOVDIR64 requires the enqueue QE to be aligned
> +	 */
> +
> +	snprintf(mz_name, sizeof(mz_name), "%s_dir_port%d",
> +		 handle->device_name,

(See device_name comment above)

> +		 ev_port->id);
> +
> +	ret = dlb2_init_qe_mem(qm_port, mz_name);
> +
> +	if (ret < 0) {
> +		DLB2_LOG_ERR("dlb2: init_qe_mem failed, ret=%d\n", ret);
> +		goto error_exit;
> +	}
> +
> +	qm_port->id = qm_port_id;
> +
> +	qm_port->cached_ldb_credits = 0;
> +	qm_port->cached_dir_credits = 0;
> +	/* CQs with depth < 8 use an 8-entry queue, but withhold credits so
> +	 * the effective depth is smaller.
> +	 */
> +	qm_port->cq_depth = cfg.cq_depth <= 8 ? 8 : cfg.cq_depth;
> +	qm_port->cq_idx = 0;
> +	qm_port->cq_idx_unmasked = 0;
> +
> +	if (dlb2->poll_mode == DLB2_CQ_POLL_MODE_SPARSE)
> +		qm_port->cq_depth_mask = (cfg.cq_depth * 4) - 1;
> +	else
> +		qm_port->cq_depth_mask = cfg.cq_depth - 1;
> +
> +	qm_port->gen_bit_shift = __builtin_popcount(qm_port-
> >cq_depth_mask);
> +	/* starting value of gen bit - it toggles at wrap time */
> +	qm_port->gen_bit = 1;
> +
> +	qm_port->int_armed = false;
> +
> +	/* Save off for later use in info and lookup APIs. */
> +	qm_port->qid_mappings = &dlb2->qm_dir_to_ev_queue_id[0];
> +
> +	qm_port->dequeue_depth = dequeue_depth;
> +
> +	/* Directed ports are auto-pop, by default. */
> +	qm_port->token_pop_mode = AUTO_POP;
> +	qm_port->owed_tokens = 0;
> +	qm_port->issued_releases = 0;
> +
> +	/* Save config message too. */
> +	rte_memcpy(&qm_port->cfg.dir, &cfg, sizeof(cfg));

(See sizeof() comment above)

> +
> +	/* update state */
> +	qm_port->state = PORT_STARTED; /* enabled at create time */
> +	qm_port->config_state = DLB2_CONFIGURED;
> +
> +	qm_port->dir_credits = dir_credit_high_watermark;
> +	qm_port->ldb_credits = ldb_credit_high_watermark;
> +	qm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;
> +	qm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;
> +
> +	DLB2_LOG_DBG("dlb2: created dir port %d, depth = %d cr=%d,%d\n",
> +		     qm_port_id,
> +		     dequeue_depth,
> +		     dir_credit_high_watermark,
> +		     ldb_credit_high_watermark);
> +
> +	rte_spinlock_unlock(&handle->resource_lock);
> +
> +	return 0;
> +
> +error_exit:
> +
> +	if (qm_port)
> +		dlb2_free_qe_mem(qm_port);
> +
> +	rte_spinlock_unlock(&handle->resource_lock);
> +
> +	DLB2_LOG_ERR("dlb2: create dir port failed!\n");
> +
> +	return ret;
> +}
> +
> +static int
> +dlb2_eventdev_port_setup(struct rte_eventdev *dev,
> +			 uint8_t ev_port_id,
> +			 const struct rte_event_port_conf *port_conf)
> +{
> +	struct dlb2_eventdev *dlb2;
> +	struct dlb2_eventdev_port *ev_port;
> +	int ret;
> +
> +	if (dev == NULL || port_conf == NULL) {
> +		DLB2_LOG_ERR("Null parameter\n");
> +		return -EINVAL;
> +	}
> +
> +	dlb2 = dlb2_pmd_priv(dev);
> +
> +	if (ev_port_id >= DLB2_MAX_NUM_PORTS)
> +		return -EINVAL;
> +
> +	if (port_conf->dequeue_depth >
> +		evdev_dlb2_default_info.max_event_port_dequeue_depth ||
> +	    port_conf->enqueue_depth >
> +		evdev_dlb2_default_info.max_event_port_enqueue_depth)
> +		return -EINVAL;
> +
> +	ev_port = &dlb2->ev_ports[ev_port_id];
> +	/* configured? */
> +	if (ev_port->setup_done) {
> +		DLB2_LOG_ERR("evport %d is already configured\n",
> ev_port_id);
> +		return -EINVAL;
> +	}
> +
> +	/* The reserved token interrupt arming scheme requires that one or
> more
> +	 * CQ tokens be reserved by the PMD. This limits the amount of CQ space
> +	 * usable by the DLB, so in order to give an *effective* CQ depth equal
> +	 * to the user-requested value, we double CQ depth and reserve half of
> +	 * its tokens. If the user requests the max CQ depth (256) then we
> +	 * cannot double it, so we reserve one token and give an effective
> +	 * depth of 255 entries.
> +	 */

I don't think this comment applies to the 2.0 device.

> +
> +	ev_port->qm_port.is_directed = port_conf->event_port_cfg &
> +		RTE_EVENT_PORT_CFG_SINGLE_LINK;
> +
> +	if (!ev_port->qm_port.is_directed) {
> +		ret = dlb2_hw_create_ldb_port(dlb2,
> +					      ev_port,
> +					      port_conf->dequeue_depth,
> +					      port_conf->enqueue_depth);
> +		if (ret < 0) {
> +			DLB2_LOG_ERR("Failed to create the lB port ve
> portId=%d\n",
> +				     ev_port_id);
> +
> +			return ret;
> +		}
> +	} else {
> +		ret = dlb2_hw_create_dir_port(dlb2,
> +					      ev_port,
> +					      port_conf->dequeue_depth,
> +					      port_conf->enqueue_depth);
> +		if (ret < 0) {
> +			DLB2_LOG_ERR("Failed to create the DIR port\n");
> +			return ret;
> +		}
> +	}
> +
> +	/* Save off port config for reconfig */
> +	dlb2->ev_ports[ev_port_id].conf = *port_conf;

Nit: 'ev_port' is assigned to &dlb2->ev_ports[ev_port_id] above, use it here and below?

> +
> +	dlb2->ev_ports[ev_port_id].id = ev_port_id;
> +	dlb2->ev_ports[ev_port_id].enq_configured = true;
> +	dlb2->ev_ports[ev_port_id].setup_done = true;
> +	dlb2->ev_ports[ev_port_id].inflight_max =
> +		port_conf->new_event_threshold;
> +	dlb2->ev_ports[ev_port_id].implicit_release =
> +		!(port_conf->event_port_cfg &
> +		  RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL);
> +	dlb2->ev_ports[ev_port_id].outstanding_releases = 0;
> +	dlb2->ev_ports[ev_port_id].inflight_credits = 0;
> +	dlb2->ev_ports[ev_port_id].credit_update_quanta =
> +		RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA;
> +	dlb2->ev_ports[ev_port_id].dlb2 = dlb2; /* reverse link */
> +
> +	/* Tear down pre-existing port->queue links */
> +	if (dlb2->run_state == DLB2_RUN_STATE_STOPPED)
> +		dlb2_port_link_teardown(dlb2, &dlb2->ev_ports[ev_port_id]);
> +
> +	dev->data->ports[ev_port_id] = &dlb2->ev_ports[ev_port_id];
> +
> +	return 0;
> +}

[...]

> diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c
> index dea70e6..a6824b1 100644
> --- a/drivers/event/dlb2/pf/dlb2_pf.c
> +++ b/drivers/event/dlb2/pf/dlb2_pf.c
> @@ -234,6 +234,183 @@ dlb2_pf_set_sn_allocation(struct dlb2_hw_dev
> *handle,
>  	return ret;
>  }
> 
> +static void *
> +dlb2_alloc_coherent_aligned(uintptr_t *phys, size_t size, int align)
> +{
> +	const struct rte_memzone *mz;
> +	char mz_name[RTE_MEMZONE_NAMESIZE];
> +	uint32_t core_id = rte_lcore_id();
> +	unsigned int socket_id;
> +
> +	snprintf(mz_name, sizeof(mz_name) - 1, "%lx",
> +		 (unsigned long)rte_get_timer_cycles());

For debug purposes, it would be better if this name can trace the mz back to
this driver. How about something like event_dlb2_pf_name + ldb/dir_port + port ID?

> +	if (core_id == (unsigned int)LCORE_ID_ANY)
> +		core_id = rte_get_master_lcore();
> +	socket_id = rte_lcore_to_socket_id(core_id);

Should this use the socket ID devarg (and perhaps fall back to the core's socket if unspecified)?

> +	mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
> +					 RTE_MEMZONE_IOVA_CONTIG, align);
> +	if (!mz) {
> +		DLB2_LOG_DBG("Unable to allocate DMA memory of size %zu
> bytes - %s\n",
> +			     size, rte_strerror(rte_errno));
> +		*phys = 0;
> +		return NULL;
> +	}
> +	*phys = mz->iova;
> +	return mz->addr;
> +}
> +
> +static int
> +dlb2_pf_ldb_port_create(struct dlb2_hw_dev *handle,
> +			struct dlb2_create_ldb_port_args *cfg,
> +			enum dlb2_cq_poll_modes poll_mode)
> +{
> +	struct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;
> +	struct dlb2_cmd_response response = {0};
> +	struct dlb2_port_memory port_memory;
> +	int ret, cq_alloc_depth;
> +	uint8_t *port_base;
> +	int alloc_sz, qe_sz;
> +	phys_addr_t cq_base;
> +	phys_addr_t pp_base;
> +	int is_dir = false;
> +
> +	DLB2_INFO(dev->dlb2_device, "Entering %s()\n", __func__);
> +
> +	if (poll_mode == DLB2_CQ_POLL_MODE_STD)
> +		qe_sz = sizeof(struct dlb2_dequeue_qe);
> +	else
> +		qe_sz = RTE_CACHE_LINE_SIZE;
> +
> +	/* Calculate the port memory required, and round up to the nearest
> +	 * cache line.
> +	 */
> +	cq_alloc_depth = RTE_MAX(cfg->cq_depth,
> DLB2_MIN_HARDWARE_CQ_DEPTH);
> +	alloc_sz = cq_alloc_depth * qe_sz;
> +	alloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);
> +
> +	port_base = dlb2_alloc_coherent_aligned(&cq_base,
> +						alloc_sz,
> +						PAGE_SIZE);

This can fit on one line

> +	if (port_base == NULL)
> +		return -ENOMEM;
> +
> +	/* Lock the page in memory */
> +	ret = rte_mem_lock_page(port_base);
> +	if (ret < 0) {
> +		DLB2_LOG_ERR("dlb2 pf pmd could not lock page for device
> i/o\n");
> +		goto create_port_err;
> +	}
> +
> +
> +	memset(port_base, 0, alloc_sz);
> +
> +	ret = dlb2_pf_create_ldb_port(&dlb2_dev->hw,
> +				      handle->domain_id,
> +				      cfg,
> +				      cq_base,
> +				      &response);
> +	if (ret)
> +		goto create_port_err;
> +
> +	pp_base = (uintptr_t)dlb2_dev->hw.func_kva + PP_BASE(is_dir);
> +	dlb2_port[response.id][DLB2_LDB_PORT].pp_addr =
> +		(void *)(uintptr_t)(pp_base + (PAGE_SIZE * response.id));

If pp_base is defined as a uintptr_t, I think you can avoid some of the explicit
casts.

> +
> +	dlb2_port[response.id][DLB2_LDB_PORT].cq_base =
> +		(void *)(uintptr_t)(port_base);

Since port_base is a uint8_t*, the uintptr_t cast shouldn't be necessary

> +	memset(&port_memory, 0, sizeof(port_memory));
> +	dlb2_list_init_head(&port_memory.list);
> +
> +	/* Fill out the per-port memory tracking structure */
> +	dlb2_dev->ldb_port_pages[response.id].valid = true;
> +	dlb2_list_splice(&port_memory.list,
> +			 &dlb2_dev->ldb_port_pages[response.id].list);

Does the list serve any purpose? Looks like port_memory is zero-initialized, then it becomes
the sole entry on a per-port list.

> +
> +	cfg->response = response;
> +
> +	DLB2_INFO(dev->dlb2_device, "Exiting %s() with ret=%d\n",
> +		  __func__, ret);
> +
> +create_port_err:

Need to free the memzone in this case.

> +
> +	return ret;
> +}
> +
> +static int
> +dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,
> +			struct dlb2_create_dir_port_args *cfg,
> +			enum dlb2_cq_poll_modes poll_mode)
> +{
> +	struct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;
> +	struct dlb2_cmd_response response = {0};
> +	struct dlb2_port_memory port_memory;
> +	int ret;
> +	uint8_t *port_base;
> +	int alloc_sz, qe_sz;
> +	phys_addr_t cq_base;
> +	phys_addr_t pp_base;
> +	int is_dir = true;
> +
> +	DLB2_INFO(dev->dlb2_device, "Entering %s()\n", __func__);
> +
> +	if (poll_mode == DLB2_CQ_POLL_MODE_STD)
> +		qe_sz = sizeof(struct dlb2_dequeue_qe);
> +	else
> +		qe_sz = RTE_CACHE_LINE_SIZE;
> +
> +	/* Calculate the port memory required, and round up to the nearest
> +	 * cache line.
> +	 */
> +	alloc_sz = cfg->cq_depth * qe_sz;
> +	alloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);
> +
> +	port_base = dlb2_alloc_coherent_aligned(&cq_base,
> +						alloc_sz,
> +						PAGE_SIZE);

This can fit on one line

> +	if (port_base == NULL)
> +		return -ENOMEM;
> +
> +	/* Lock the page in memory */
> +	ret = rte_mem_lock_page(port_base);
> +	if (ret < 0) {
> +		DLB2_LOG_ERR("dlb2 pf pmd could not lock page for device
> i/o\n");
> +		goto create_port_err;
> +	}
> +
> +	memset(port_base, 0, alloc_sz);
> +
> +	ret = dlb2_pf_create_dir_port(&dlb2_dev->hw,
> +				      handle->domain_id,
> +				      cfg,
> +				      cq_base,
> +				      &response);
> +	if (ret)
> +		goto create_port_err;
> +
> +	pp_base = (uintptr_t)dlb2_dev->hw.func_kva + PP_BASE(is_dir);

(See uintptr_t comment above)

> +	dlb2_port[response.id][DLB2_DIR_PORT].pp_addr =
> +		(void *)(uintptr_t)(pp_base + (PAGE_SIZE * response.id));
> +
> +	dlb2_port[response.id][DLB2_DIR_PORT].cq_base =
> +		(void *)(uintptr_t)(port_base);

(See port_base comment above)

> +	memset(&port_memory, 0, sizeof(port_memory));
> +	dlb2_list_init_head(&port_memory.list);
> +
> +	/* Fill out the per-port memory tracking structure */
> +	dlb2_dev->dir_port_pages[response.id].valid = true;
> +	dlb2_list_splice(&port_memory.list,
> +			 &dlb2_dev->dir_port_pages[response.id].list);
> +

(See list comment above)

> +	cfg->response = response;
> +
> +	DLB2_INFO(dev->dlb2_device, "Exiting %s() with ret=%d\n",
> +		  __func__, ret);
> +
> +create_port_err:

Need to free the memzone in this case

> +
> +	return ret;
> +}
> +
>  static void
>  dlb2_pf_iface_fn_ptrs_init(void)
>  {
> @@ -247,6 +424,8 @@ dlb2_pf_iface_fn_ptrs_init(void)
>  	dlb2_iface_get_cq_poll_mode = dlb2_pf_get_cq_poll_mode;
>  	dlb2_iface_sched_domain_create = dlb2_pf_sched_domain_create;
>  	dlb2_iface_ldb_queue_create = dlb2_pf_ldb_queue_create;
> +	dlb2_iface_ldb_port_create = dlb2_pf_ldb_port_create;
> +	dlb2_iface_dir_port_create = dlb2_pf_dir_port_create;
>  	dlb2_iface_get_sn_allocation = dlb2_pf_get_sn_allocation;
>  	dlb2_iface_set_sn_allocation = dlb2_pf_set_sn_allocation;
>  	dlb2_iface_get_sn_occupancy = dlb2_pf_get_sn_occupancy;
> --
> 2.6.4

I don't see the port memzones getting freed anywhere, e.g. if the event device is reset.
Looks like a possible memory leak.

Thanks,
Gage

Patch
diff mbox series

diff --git a/drivers/event/dlb2/dlb2.c b/drivers/event/dlb2/dlb2.c
index 366e194..a4c8833 100644
--- a/drivers/event/dlb2/dlb2.c
+++ b/drivers/event/dlb2/dlb2.c
@@ -1043,6 +1043,532 @@  dlb2_eventdev_queue_setup(struct rte_eventdev *dev,
 	return ret;
 }
 
+static int
+dlb2_init_consume_qe(struct dlb2_port *qm_port, char *mz_name)
+{
+	struct dlb2_cq_pop_qe *qe;
+
+	qe = rte_malloc(mz_name,
+			DLB2_NUM_QES_PER_CACHE_LINE *
+				sizeof(struct dlb2_cq_pop_qe),
+			RTE_CACHE_LINE_SIZE);
+
+	if (qe == NULL)	{
+		DLB2_LOG_ERR("dlb2: no memory for consume_qe\n");
+		return -ENOMEM;
+	}
+	qm_port->consume_qe = qe;
+
+	memset(qe, 0, DLB2_NUM_QES_PER_CACHE_LINE *
+	       sizeof(struct dlb2_cq_pop_qe));
+
+	qe->qe_valid = 0;
+	qe->qe_frag = 0;
+	qe->qe_comp = 0;
+	qe->cq_token = 1;
+	/* Tokens value is 0-based; i.e. '0' returns 1 token, '1' returns 2,
+	 * and so on.
+	 */
+	qe->tokens = 0;	/* set at run time */
+	qe->meas_lat = 0;
+	qe->no_dec = 0;
+	/* Completion IDs are disabled */
+	qe->cmp_id = 0;
+
+	return 0;
+}
+
+static int
+dlb2_init_int_arm_qe(struct dlb2_port *qm_port, char *mz_name)
+{
+	struct dlb2_enqueue_qe *qe;
+
+	qe = rte_malloc(mz_name,
+			DLB2_NUM_QES_PER_CACHE_LINE *
+				sizeof(struct dlb2_enqueue_qe),
+			RTE_CACHE_LINE_SIZE);
+
+	if (qe == NULL) {
+		DLB2_LOG_ERR("dlb2: no memory for complete_qe\n");
+		return -ENOMEM;
+	}
+	qm_port->int_arm_qe = qe;
+
+	memset(qe, 0, DLB2_NUM_QES_PER_CACHE_LINE *
+	       sizeof(struct dlb2_enqueue_qe));
+
+	/* V2 - INT ARM is CQ_TOKEN + FRAG */
+	qe->qe_valid = 0;
+	qe->qe_frag = 1;
+	qe->qe_comp = 0;
+	qe->cq_token = 1;
+	qe->meas_lat = 0;
+	qe->no_dec = 0;
+	/* Completion IDs are disabled */
+	qe->cmp_id = 0;
+
+	return 0;
+}
+
+static int
+dlb2_init_qe_mem(struct dlb2_port *qm_port, char *mz_name)
+{
+	int ret, sz;
+
+	sz = DLB2_NUM_QES_PER_CACHE_LINE * sizeof(struct dlb2_enqueue_qe);
+
+	qm_port->qe4 = rte_malloc(mz_name, sz, RTE_CACHE_LINE_SIZE);
+
+	if (qm_port->qe4 == NULL) {
+		DLB2_LOG_ERR("dlb2: no qe4 memory\n");
+		ret = -ENOMEM;
+		goto error_exit;
+	}
+
+	memset(qm_port->qe4, 0, sz);
+
+	ret = dlb2_init_int_arm_qe(qm_port, mz_name);
+	if (ret < 0) {
+		DLB2_LOG_ERR("dlb2: dlb2_init_int_arm_qe ret=%d\n",
+			     ret);
+		goto error_exit;
+	}
+
+	ret = dlb2_init_consume_qe(qm_port, mz_name);
+	if (ret < 0) {
+		DLB2_LOG_ERR("dlb2: dlb2_init_consume_qe ret=%d\n",
+			     ret);
+		goto error_exit;
+	}
+
+	return 0;
+
+error_exit:
+
+	dlb2_free_qe_mem(qm_port);
+
+	return ret;
+}
+
+static int
+dlb2_hw_create_ldb_port(struct dlb2_eventdev *dlb2,
+			struct dlb2_eventdev_port *ev_port,
+			uint32_t dequeue_depth,
+			uint32_t enqueue_depth)
+{
+	struct dlb2_hw_dev *handle = &dlb2->qm_instance;
+	struct dlb2_create_ldb_port_args cfg = {0};
+	int ret;
+	struct dlb2_port *qm_port = NULL;
+	char mz_name[RTE_MEMZONE_NAMESIZE];
+	uint32_t qm_port_id;
+	uint16_t ldb_credit_high_watermark;
+	uint16_t dir_credit_high_watermark;
+
+	if (handle == NULL)
+		return -EINVAL;
+
+	if (dequeue_depth < DLB2_MIN_CQ_DEPTH ||
+	    dequeue_depth > DLB2_MAX_INPUT_QUEUE_DEPTH) {
+		DLB2_LOG_ERR("dlb2: invalid dequeue_depth, must be %d-%d\n",
+			     DLB2_MIN_CQ_DEPTH, DLB2_MAX_INPUT_QUEUE_DEPTH);
+		return -EINVAL;
+	}
+
+	if (enqueue_depth < DLB2_MIN_ENQUEUE_DEPTH) {
+		DLB2_LOG_ERR("dlb2: invalid enqueue_depth, must be at least %d\n",
+			     DLB2_MIN_ENQUEUE_DEPTH);
+		return -EINVAL;
+	}
+
+	rte_spinlock_lock(&handle->resource_lock);
+
+	/* TODO - additional parameter validation */
+	/* We round up to the next power of 2 if necessary */
+	cfg.cq_depth = rte_align32pow2(dequeue_depth);
+	cfg.cq_depth_threshold = 1;
+
+	cfg.cq_history_list_size = DLB2_NUM_HIST_LIST_ENTRIES_PER_LDB_PORT;
+
+	if (handle->cos_id == DLB2_COS_DEFAULT)
+		cfg.cos_id = 0;
+	else
+		cfg.cos_id = handle->cos_id;
+
+	cfg.cos_strict = 0;
+
+	/* User controls the LDB high watermark via enqueue depth. The DIR high
+	 * watermark is equal, unless the directed credit pool is too small.
+	 */
+	ldb_credit_high_watermark = enqueue_depth;
+
+	/* If there are no directed ports, the kernel driver will ignore this
+	 * port's directed credit settings. Don't use enqueue_depth if it would
+	 * require more directed credits than are available.
+	 */
+	dir_credit_high_watermark =
+		RTE_MIN(enqueue_depth,
+			handle->cfg.num_dir_credits / dlb2->num_ports);
+
+	/* Per QM values */
+
+	/* DEBUG
+	 * DLB2_LOG_ERR("create ldb port - grp=%d, devId=%d\n",
+	 * handle->cfg.domain_id, handle->device_id);
+	 */
+
+	ret = dlb2_iface_ldb_port_create(handle, &cfg,  dlb2->poll_mode);
+	if (ret < 0) {
+		DLB2_LOG_ERR("dlb2: dlb2_ldb_port_create error, ret=%d (driver status: %s)\n",
+			     ret, dlb2_error_strings[cfg.response.status]);
+		goto error_exit;
+	}
+
+	qm_port_id = cfg.response.id;
+
+	DLB2_LOG_DBG("dlb2: ev_port %d uses qm LB port %d <<<<<\n",
+		     ev_port->id, qm_port_id);
+
+	qm_port = &ev_port->qm_port;
+	qm_port->ev_port = ev_port; /* back ptr */
+	qm_port->dlb2 = dlb2; /* back ptr */
+	/*
+	 * Allocate and init local qe struct(s).
+	 * Note: MOVDIR64 requires the enqueue QE (qe4) to be aligned.
+	 */
+
+	snprintf(mz_name, sizeof(mz_name), "%s_ldb_port%d",
+		 handle->device_name,
+		 ev_port->id);
+
+	ret = dlb2_init_qe_mem(qm_port, mz_name);
+	if (ret < 0) {
+		DLB2_LOG_ERR("dlb2: init_qe_mem failed, ret=%d\n", ret);
+		goto error_exit;
+	}
+
+	qm_port->id = qm_port_id;
+
+	qm_port->cached_ldb_credits = 0;
+	qm_port->cached_dir_credits = 0;
+	/* CQs with depth < 8 use an 8-entry queue, but withhold credits so
+	 * the effective depth is smaller.
+	 */
+	qm_port->cq_depth = cfg.cq_depth <= 8 ? 8 : cfg.cq_depth;
+	qm_port->cq_idx = 0;
+	qm_port->cq_idx_unmasked = 0;
+
+	if (dlb2->poll_mode == DLB2_CQ_POLL_MODE_SPARSE)
+		qm_port->cq_depth_mask = (qm_port->cq_depth * 4) - 1;
+	else
+		qm_port->cq_depth_mask = qm_port->cq_depth - 1;
+
+	qm_port->gen_bit_shift = __builtin_popcount(qm_port->cq_depth_mask);
+	/* starting value of gen bit - it toggles at wrap time */
+	qm_port->gen_bit = 1;
+
+	qm_port->int_armed = false;
+
+	/* Save off for later use in info and lookup APIs. */
+	qm_port->qid_mappings = &dlb2->qm_ldb_to_ev_queue_id[0];
+
+	qm_port->dequeue_depth = dequeue_depth;
+	qm_port->token_pop_thresh = dequeue_depth;
+
+	qm_port->owed_tokens = 0;
+	qm_port->issued_releases = 0;
+
+	/* Save config message too. */
+	rte_memcpy(&qm_port->cfg.ldb, &cfg, sizeof(cfg));
+
+	/* update state */
+	qm_port->state = PORT_STARTED; /* enabled at create time */
+	qm_port->config_state = DLB2_CONFIGURED;
+
+	qm_port->dir_credits = dir_credit_high_watermark;
+	qm_port->ldb_credits = ldb_credit_high_watermark;
+	qm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;
+	qm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;
+
+	DLB2_LOG_DBG("dlb2: created ldb port %d, depth = %d, ldb credits=%d, dir credits=%d\n",
+		     qm_port_id,
+		     dequeue_depth,
+		     qm_port->ldb_credits,
+		     qm_port->dir_credits);
+
+	rte_spinlock_unlock(&handle->resource_lock);
+
+	return 0;
+
+error_exit:
+
+	if (qm_port)
+		dlb2_free_qe_mem(qm_port);
+
+	rte_spinlock_unlock(&handle->resource_lock);
+
+	DLB2_LOG_ERR("dlb2: create ldb port failed!\n");
+
+	return ret;
+}
+
+static void
+dlb2_port_link_teardown(struct dlb2_eventdev *dlb2,
+			struct dlb2_eventdev_port *ev_port)
+{
+	struct dlb2_eventdev_queue *ev_queue;
+	int i;
+
+	for (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++) {
+		if (!ev_port->link[i].valid)
+			continue;
+
+		ev_queue = &dlb2->ev_queues[ev_port->link[i].queue_id];
+
+		ev_port->link[i].valid = false;
+		ev_port->num_links--;
+		ev_queue->num_links--;
+	}
+}
+
+static int
+dlb2_hw_create_dir_port(struct dlb2_eventdev *dlb2,
+			struct dlb2_eventdev_port *ev_port,
+			uint32_t dequeue_depth,
+			uint32_t enqueue_depth)
+{
+	struct dlb2_hw_dev *handle = &dlb2->qm_instance;
+	struct dlb2_create_dir_port_args cfg = {0};
+	int ret;
+	struct dlb2_port *qm_port = NULL;
+	char mz_name[RTE_MEMZONE_NAMESIZE];
+	uint32_t qm_port_id;
+	uint16_t ldb_credit_high_watermark;
+	uint16_t dir_credit_high_watermark;
+
+	if (dlb2 == NULL || handle == NULL)
+		return -EINVAL;
+
+	if (dequeue_depth < DLB2_MIN_CQ_DEPTH ||
+	    dequeue_depth > DLB2_MAX_INPUT_QUEUE_DEPTH) {
+		DLB2_LOG_ERR("dlb2: invalid dequeue_depth, must be %d-%d\n",
+			     DLB2_MIN_CQ_DEPTH, DLB2_MAX_INPUT_QUEUE_DEPTH);
+		return -EINVAL;
+	}
+
+	rte_spinlock_lock(&handle->resource_lock);
+
+	/* Directed queues are configured at link time. */
+	cfg.queue_id = -1;
+
+	/* We round up to the next power of 2 if necessary */
+	cfg.cq_depth = rte_align32pow2(dequeue_depth);
+	cfg.cq_depth_threshold = 1;
+
+	/* User controls the LDB high watermark via enqueue depth. The DIR high
+	 * watermark is equal, unless the directed credit pool is too small.
+	 */
+	ldb_credit_high_watermark = enqueue_depth;
+
+	/* Don't use enqueue_depth if it would require more directed credits
+	 * than are available.
+	 */
+	dir_credit_high_watermark =
+		RTE_MIN(enqueue_depth,
+			handle->cfg.num_dir_credits / dlb2->num_ports);
+
+	/* Per QM values */
+
+	ret = dlb2_iface_dir_port_create(handle, &cfg,  dlb2->poll_mode);
+	if (ret < 0) {
+		DLB2_LOG_ERR("dlb2: dlb2_dir_port_create error, ret=%d (driver status: %s)\n",
+			     ret, dlb2_error_strings[cfg.response.status]);
+		goto error_exit;
+	}
+
+	qm_port_id = cfg.response.id;
+
+	DLB2_LOG_DBG("dlb2: ev_port %d uses qm DIR port %d <<<<<\n",
+		     ev_port->id, qm_port_id);
+
+	qm_port = &ev_port->qm_port;
+	qm_port->ev_port = ev_port; /* back ptr */
+	qm_port->dlb2 = dlb2;  /* back ptr */
+
+	/*
+	 * Init local qe struct(s).
+	 * Note: MOVDIR64 requires the enqueue QE to be aligned
+	 */
+
+	snprintf(mz_name, sizeof(mz_name), "%s_dir_port%d",
+		 handle->device_name,
+		 ev_port->id);
+
+	ret = dlb2_init_qe_mem(qm_port, mz_name);
+
+	if (ret < 0) {
+		DLB2_LOG_ERR("dlb2: init_qe_mem failed, ret=%d\n", ret);
+		goto error_exit;
+	}
+
+	qm_port->id = qm_port_id;
+
+	qm_port->cached_ldb_credits = 0;
+	qm_port->cached_dir_credits = 0;
+	/* CQs with depth < 8 use an 8-entry queue, but withhold credits so
+	 * the effective depth is smaller.
+	 */
+	qm_port->cq_depth = cfg.cq_depth <= 8 ? 8 : cfg.cq_depth;
+	qm_port->cq_idx = 0;
+	qm_port->cq_idx_unmasked = 0;
+
+	if (dlb2->poll_mode == DLB2_CQ_POLL_MODE_SPARSE)
+		qm_port->cq_depth_mask = (cfg.cq_depth * 4) - 1;
+	else
+		qm_port->cq_depth_mask = cfg.cq_depth - 1;
+
+	qm_port->gen_bit_shift = __builtin_popcount(qm_port->cq_depth_mask);
+	/* starting value of gen bit - it toggles at wrap time */
+	qm_port->gen_bit = 1;
+
+	qm_port->int_armed = false;
+
+	/* Save off for later use in info and lookup APIs. */
+	qm_port->qid_mappings = &dlb2->qm_dir_to_ev_queue_id[0];
+
+	qm_port->dequeue_depth = dequeue_depth;
+
+	/* Directed ports are auto-pop, by default. */
+	qm_port->token_pop_mode = AUTO_POP;
+	qm_port->owed_tokens = 0;
+	qm_port->issued_releases = 0;
+
+	/* Save config message too. */
+	rte_memcpy(&qm_port->cfg.dir, &cfg, sizeof(cfg));
+
+	/* update state */
+	qm_port->state = PORT_STARTED; /* enabled at create time */
+	qm_port->config_state = DLB2_CONFIGURED;
+
+	qm_port->dir_credits = dir_credit_high_watermark;
+	qm_port->ldb_credits = ldb_credit_high_watermark;
+	qm_port->credit_pool[DLB2_DIR_QUEUE] = &dlb2->dir_credit_pool;
+	qm_port->credit_pool[DLB2_LDB_QUEUE] = &dlb2->ldb_credit_pool;
+
+	DLB2_LOG_DBG("dlb2: created dir port %d, depth = %d cr=%d,%d\n",
+		     qm_port_id,
+		     dequeue_depth,
+		     dir_credit_high_watermark,
+		     ldb_credit_high_watermark);
+
+	rte_spinlock_unlock(&handle->resource_lock);
+
+	return 0;
+
+error_exit:
+
+	if (qm_port)
+		dlb2_free_qe_mem(qm_port);
+
+	rte_spinlock_unlock(&handle->resource_lock);
+
+	DLB2_LOG_ERR("dlb2: create dir port failed!\n");
+
+	return ret;
+}
+
+static int
+dlb2_eventdev_port_setup(struct rte_eventdev *dev,
+			 uint8_t ev_port_id,
+			 const struct rte_event_port_conf *port_conf)
+{
+	struct dlb2_eventdev *dlb2;
+	struct dlb2_eventdev_port *ev_port;
+	int ret;
+
+	if (dev == NULL || port_conf == NULL) {
+		DLB2_LOG_ERR("Null parameter\n");
+		return -EINVAL;
+	}
+
+	dlb2 = dlb2_pmd_priv(dev);
+
+	if (ev_port_id >= DLB2_MAX_NUM_PORTS)
+		return -EINVAL;
+
+	if (port_conf->dequeue_depth >
+		evdev_dlb2_default_info.max_event_port_dequeue_depth ||
+	    port_conf->enqueue_depth >
+		evdev_dlb2_default_info.max_event_port_enqueue_depth)
+		return -EINVAL;
+
+	ev_port = &dlb2->ev_ports[ev_port_id];
+	/* configured? */
+	if (ev_port->setup_done) {
+		DLB2_LOG_ERR("evport %d is already configured\n", ev_port_id);
+		return -EINVAL;
+	}
+
+	/* The reserved token interrupt arming scheme requires that one or more
+	 * CQ tokens be reserved by the PMD. This limits the amount of CQ space
+	 * usable by the DLB, so in order to give an *effective* CQ depth equal
+	 * to the user-requested value, we double CQ depth and reserve half of
+	 * its tokens. If the user requests the max CQ depth (256) then we
+	 * cannot double it, so we reserve one token and give an effective
+	 * depth of 255 entries.
+	 */
+
+	ev_port->qm_port.is_directed = port_conf->event_port_cfg &
+		RTE_EVENT_PORT_CFG_SINGLE_LINK;
+
+	if (!ev_port->qm_port.is_directed) {
+		ret = dlb2_hw_create_ldb_port(dlb2,
+					      ev_port,
+					      port_conf->dequeue_depth,
+					      port_conf->enqueue_depth);
+		if (ret < 0) {
+			DLB2_LOG_ERR("Failed to create the lB port ve portId=%d\n",
+				     ev_port_id);
+
+			return ret;
+		}
+	} else {
+		ret = dlb2_hw_create_dir_port(dlb2,
+					      ev_port,
+					      port_conf->dequeue_depth,
+					      port_conf->enqueue_depth);
+		if (ret < 0) {
+			DLB2_LOG_ERR("Failed to create the DIR port\n");
+			return ret;
+		}
+	}
+
+	/* Save off port config for reconfig */
+	dlb2->ev_ports[ev_port_id].conf = *port_conf;
+
+	dlb2->ev_ports[ev_port_id].id = ev_port_id;
+	dlb2->ev_ports[ev_port_id].enq_configured = true;
+	dlb2->ev_ports[ev_port_id].setup_done = true;
+	dlb2->ev_ports[ev_port_id].inflight_max =
+		port_conf->new_event_threshold;
+	dlb2->ev_ports[ev_port_id].implicit_release =
+		!(port_conf->event_port_cfg &
+		  RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL);
+	dlb2->ev_ports[ev_port_id].outstanding_releases = 0;
+	dlb2->ev_ports[ev_port_id].inflight_credits = 0;
+	dlb2->ev_ports[ev_port_id].credit_update_quanta =
+		RTE_LIBRTE_PMD_DLB2_SW_CREDIT_QUANTA;
+	dlb2->ev_ports[ev_port_id].dlb2 = dlb2; /* reverse link */
+
+	/* Tear down pre-existing port->queue links */
+	if (dlb2->run_state == DLB2_RUN_STATE_STOPPED)
+		dlb2_port_link_teardown(dlb2, &dlb2->ev_ports[ev_port_id]);
+
+	dev->data->ports[ev_port_id] = &dlb2->ev_ports[ev_port_id];
+
+	return 0;
+}
+
 static void
 dlb2_entry_points_init(struct rte_eventdev *dev)
 {
@@ -1053,6 +1579,7 @@  dlb2_entry_points_init(struct rte_eventdev *dev)
 		.queue_def_conf   = dlb2_eventdev_queue_default_conf_get,
 		.queue_setup      = dlb2_eventdev_queue_setup,
 		.port_def_conf    = dlb2_eventdev_port_default_conf_get,
+		.port_setup       = dlb2_eventdev_port_setup,
 		.dump             = dlb2_eventdev_dump,
 		.xstats_get       = dlb2_eventdev_xstats_get,
 		.xstats_get_names = dlb2_eventdev_xstats_get_names,
diff --git a/drivers/event/dlb2/dlb2_iface.c b/drivers/event/dlb2/dlb2_iface.c
index f50a918..84cbf25 100644
--- a/drivers/event/dlb2/dlb2_iface.c
+++ b/drivers/event/dlb2/dlb2_iface.c
@@ -57,3 +57,12 @@  int (*dlb2_iface_set_sn_allocation)(struct dlb2_hw_dev *handle,
 
 int (*dlb2_iface_get_sn_occupancy)(struct dlb2_hw_dev *handle,
 				   struct dlb2_get_sn_occupancy_args *args);
+
+int (*dlb2_iface_ldb_port_create)(struct dlb2_hw_dev *handle,
+				  struct dlb2_create_ldb_port_args *cfg,
+				  enum dlb2_cq_poll_modes poll_mode);
+
+int (*dlb2_iface_dir_port_create)(struct dlb2_hw_dev *handle,
+				  struct dlb2_create_dir_port_args *cfg,
+				  enum dlb2_cq_poll_modes poll_mode);
+
diff --git a/drivers/event/dlb2/dlb2_iface.h b/drivers/event/dlb2/dlb2_iface.h
index c1ef7c2..a090a54 100644
--- a/drivers/event/dlb2/dlb2_iface.h
+++ b/drivers/event/dlb2/dlb2_iface.h
@@ -43,4 +43,12 @@  extern int (*dlb2_iface_set_sn_allocation)(struct dlb2_hw_dev *handle,
 extern int (*dlb2_iface_get_sn_occupancy)(struct dlb2_hw_dev *handle,
 				  struct dlb2_get_sn_occupancy_args *args);
 
+extern int (*dlb2_iface_ldb_port_create)(struct dlb2_hw_dev *handle,
+					 struct dlb2_create_ldb_port_args *cfg,
+					 enum dlb2_cq_poll_modes poll_mode);
+
+extern int (*dlb2_iface_dir_port_create)(struct dlb2_hw_dev *handle,
+					 struct dlb2_create_dir_port_args *cfg,
+					 enum dlb2_cq_poll_modes poll_mode);
+
 #endif /* _DLB2_IFACE_H_ */
diff --git a/drivers/event/dlb2/pf/base/dlb2_resource.c b/drivers/event/dlb2/pf/base/dlb2_resource.c
index dc9d19a..bb8683c 100644
--- a/drivers/event/dlb2/pf/base/dlb2_resource.c
+++ b/drivers/event/dlb2/pf/base/dlb2_resource.c
@@ -3970,3 +3970,924 @@  int dlb2_set_group_sequence_numbers(struct dlb2_hw *hw,
 
 	return 0;
 }
+
+static void dlb2_ldb_port_configure_pp(struct dlb2_hw *hw,
+				       struct dlb2_hw_domain *domain,
+				       struct dlb2_ldb_port *port,
+				       bool vdev_req,
+				       unsigned int vdev_id)
+{
+	union dlb2_sys_ldb_pp2vas r0 = { {0} };
+	union dlb2_sys_ldb_pp_v r4 = { {0} };
+
+	r0.field.vas = domain->id.phys_id;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_LDB_PP2VAS(port->id.phys_id), r0.val);
+
+	if (vdev_req) {
+		union dlb2_sys_vf_ldb_vpp2pp r1 = { {0} };
+		union dlb2_sys_ldb_pp2vdev r2 = { {0} };
+		union dlb2_sys_vf_ldb_vpp_v r3 = { {0} };
+		unsigned int offs;
+		u32 virt_id;
+
+		/*
+		 * DLB uses producer port address bits 17:12 to determine the
+		 * producer port ID. In Scalable IOV mode, PP accesses come
+		 * through the PF MMIO window for the physical producer port,
+		 * so for translation purposes the virtual and physical port
+		 * IDs are equal.
+		 */
+		if (hw->virt_mode == DLB2_VIRT_SRIOV)
+			virt_id = port->id.virt_id;
+		else
+			virt_id = port->id.phys_id;
+
+		r1.field.pp = port->id.phys_id;
+
+		offs = vdev_id * DLB2_MAX_NUM_LDB_PORTS + virt_id;
+
+		DLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VPP2PP(offs), r1.val);
+
+		r2.field.vdev = vdev_id;
+
+		DLB2_CSR_WR(hw,
+			    DLB2_SYS_LDB_PP2VDEV(port->id.phys_id),
+			    r2.val);
+
+		r3.field.vpp_v = 1;
+
+		DLB2_CSR_WR(hw, DLB2_SYS_VF_LDB_VPP_V(offs), r3.val);
+	}
+
+	r4.field.pp_v = 1;
+
+	DLB2_CSR_WR(hw,
+		    DLB2_SYS_LDB_PP_V(port->id.phys_id),
+		    r4.val);
+}
+
+static int dlb2_ldb_port_configure_cq(struct dlb2_hw *hw,
+				      struct dlb2_hw_domain *domain,
+				      struct dlb2_ldb_port *port,
+				      uintptr_t cq_dma_base,
+				      struct dlb2_create_ldb_port_args *args,
+				      bool vdev_req,
+				      unsigned int vdev_id)
+{
+	union dlb2_sys_ldb_cq_addr_l r0 = { {0} };
+	union dlb2_sys_ldb_cq_addr_u r1 = { {0} };
+	union dlb2_sys_ldb_cq2vf_pf_ro r2 = { {0} };
+	union dlb2_chp_ldb_cq_tkn_depth_sel r3 = { {0} };
+	union dlb2_lsp_cq_ldb_tkn_depth_sel r4 = { {0} };
+	union dlb2_chp_hist_list_lim r5 = { {0} };
+	union dlb2_chp_hist_list_base r6 = { {0} };
+	union dlb2_lsp_cq_ldb_infl_lim r7 = { {0} };
+	union dlb2_chp_hist_list_push_ptr r8 = { {0} };
+	union dlb2_chp_hist_list_pop_ptr r9 = { {0} };
+	union dlb2_sys_ldb_cq_at r10 = { {0} };
+	union dlb2_sys_ldb_cq_pasid r11 = { {0} };
+	union dlb2_chp_ldb_cq2vas r12 = { {0} };
+	union dlb2_lsp_cq2priov r13 = { {0} };
+
+	/* The CQ address is 64B-aligned, and the DLB only wants bits [63:6] */
+	r0.field.addr_l = cq_dma_base >> 6;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_ADDR_L(port->id.phys_id), r0.val);
+
+	r1.field.addr_u = cq_dma_base >> 32;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_ADDR_U(port->id.phys_id), r1.val);
+
+	/*
+	 * 'ro' == relaxed ordering. This setting allows DLB2 to write
+	 * cache lines out-of-order (but QEs within a cache line are always
+	 * updated in-order).
+	 */
+	r2.field.vf = vdev_id;
+	r2.field.is_pf = !vdev_req && (hw->virt_mode != DLB2_VIRT_SIOV);
+	r2.field.ro = 1;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ2VF_PF_RO(port->id.phys_id), r2.val);
+
+	if (args->cq_depth <= 8) {
+		r3.field.token_depth_select = 1;
+	} else if (args->cq_depth == 16) {
+		r3.field.token_depth_select = 2;
+	} else if (args->cq_depth == 32) {
+		r3.field.token_depth_select = 3;
+	} else if (args->cq_depth == 64) {
+		r3.field.token_depth_select = 4;
+	} else if (args->cq_depth == 128) {
+		r3.field.token_depth_select = 5;
+	} else if (args->cq_depth == 256) {
+		r3.field.token_depth_select = 6;
+	} else if (args->cq_depth == 512) {
+		r3.field.token_depth_select = 7;
+	} else if (args->cq_depth == 1024) {
+		r3.field.token_depth_select = 8;
+	} else {
+		DLB2_HW_ERR(hw,
+			    "[%s():%d] Internal error: invalid CQ depth\n",
+			    __func__, __LINE__);
+		return -EFAULT;
+	}
+
+	DLB2_CSR_WR(hw,
+		    DLB2_CHP_LDB_CQ_TKN_DEPTH_SEL(port->id.phys_id),
+		    r3.val);
+
+	/*
+	 * To support CQs with depth less than 8, program the token count
+	 * register with a non-zero initial value. Operations such as domain
+	 * reset must take this initial value into account when quiescing the
+	 * CQ.
+	 */
+	port->init_tkn_cnt = 0;
+
+	if (args->cq_depth < 8) {
+		union dlb2_lsp_cq_ldb_tkn_cnt r14 = { {0} };
+
+		port->init_tkn_cnt = 8 - args->cq_depth;
+
+		r14.field.token_count = port->init_tkn_cnt;
+
+		DLB2_CSR_WR(hw,
+			    DLB2_LSP_CQ_LDB_TKN_CNT(port->id.phys_id),
+			    r14.val);
+	} else {
+		DLB2_CSR_WR(hw,
+			    DLB2_LSP_CQ_LDB_TKN_CNT(port->id.phys_id),
+			    DLB2_LSP_CQ_LDB_TKN_CNT_RST);
+	}
+
+	r4.field.token_depth_select = r3.field.token_depth_select;
+	r4.field.ignore_depth = 0;
+
+	DLB2_CSR_WR(hw,
+		    DLB2_LSP_CQ_LDB_TKN_DEPTH_SEL(port->id.phys_id),
+		    r4.val);
+
+	/* Reset the CQ write pointer */
+	DLB2_CSR_WR(hw,
+		    DLB2_CHP_LDB_CQ_WPTR(port->id.phys_id),
+		    DLB2_CHP_LDB_CQ_WPTR_RST);
+
+	r5.field.limit = port->hist_list_entry_limit - 1;
+
+	DLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_LIM(port->id.phys_id), r5.val);
+
+	r6.field.base = port->hist_list_entry_base;
+
+	DLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_BASE(port->id.phys_id), r6.val);
+
+	/*
+	 * The inflight limit sets a cap on the number of QEs for which this CQ
+	 * can owe completions at one time.
+	 */
+	r7.field.limit = args->cq_history_list_size;
+
+	DLB2_CSR_WR(hw, DLB2_LSP_CQ_LDB_INFL_LIM(port->id.phys_id), r7.val);
+
+	r8.field.push_ptr = r6.field.base;
+	r8.field.generation = 0;
+
+	DLB2_CSR_WR(hw,
+		    DLB2_CHP_HIST_LIST_PUSH_PTR(port->id.phys_id),
+		    r8.val);
+
+	r9.field.pop_ptr = r6.field.base;
+	r9.field.generation = 0;
+
+	DLB2_CSR_WR(hw, DLB2_CHP_HIST_LIST_POP_PTR(port->id.phys_id), r9.val);
+
+	/*
+	 * Address translation (AT) settings: 0: untranslated, 2: translated
+	 * (see ATS spec regarding Address Type field for more details)
+	 */
+	r10.field.cq_at = 0;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_LDB_CQ_AT(port->id.phys_id), r10.val);
+
+	if (vdev_req && hw->virt_mode == DLB2_VIRT_SIOV) {
+		r11.field.pasid = hw->pasid[vdev_id];
+		r11.field.fmt2 = 1;
+	}
+
+	DLB2_CSR_WR(hw,
+		    DLB2_SYS_LDB_CQ_PASID(port->id.phys_id),
+		    r11.val);
+
+	r12.field.cq2vas = domain->id.phys_id;
+
+	DLB2_CSR_WR(hw, DLB2_CHP_LDB_CQ2VAS(port->id.phys_id), r12.val);
+
+	/* Disable the port's QID mappings */
+	r13.field.v = 0;
+
+	DLB2_CSR_WR(hw, DLB2_LSP_CQ2PRIOV(port->id.phys_id), r13.val);
+
+	return 0;
+}
+
+static int dlb2_configure_ldb_port(struct dlb2_hw *hw,
+				   struct dlb2_hw_domain *domain,
+				   struct dlb2_ldb_port *port,
+				   uintptr_t cq_dma_base,
+				   struct dlb2_create_ldb_port_args *args,
+				   bool vdev_req,
+				   unsigned int vdev_id)
+{
+	int ret, i;
+
+	port->hist_list_entry_base = domain->hist_list_entry_base +
+				     domain->hist_list_entry_offset;
+	port->hist_list_entry_limit = port->hist_list_entry_base +
+				      args->cq_history_list_size;
+
+	domain->hist_list_entry_offset += args->cq_history_list_size;
+	domain->avail_hist_list_entries -= args->cq_history_list_size;
+
+	ret = dlb2_ldb_port_configure_cq(hw,
+					 domain,
+					 port,
+					 cq_dma_base,
+					 args,
+					 vdev_req,
+					 vdev_id);
+	if (ret < 0)
+		return ret;
+
+	dlb2_ldb_port_configure_pp(hw,
+				   domain,
+				   port,
+				   vdev_req,
+				   vdev_id);
+
+	dlb2_ldb_port_cq_enable(hw, port);
+
+	for (i = 0; i < DLB2_MAX_NUM_QIDS_PER_LDB_CQ; i++)
+		port->qid_map[i].state = DLB2_QUEUE_UNMAPPED;
+	port->num_mappings = 0;
+
+	port->enabled = true;
+
+	port->configured = true;
+
+	return 0;
+}
+
+static void
+dlb2_log_create_ldb_port_args(struct dlb2_hw *hw,
+			      u32 domain_id,
+			      uintptr_t cq_dma_base,
+			      struct dlb2_create_ldb_port_args *args,
+			      bool vdev_req,
+			      unsigned int vdev_id)
+{
+	DLB2_HW_DBG(hw, "DLB2 create load-balanced port arguments:\n");
+	if (vdev_req)
+		DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
+	DLB2_HW_DBG(hw, "\tDomain ID:                 %d\n",
+		    domain_id);
+	DLB2_HW_DBG(hw, "\tCQ depth:                  %d\n",
+		    args->cq_depth);
+	DLB2_HW_DBG(hw, "\tCQ hist list size:         %d\n",
+		    args->cq_history_list_size);
+	DLB2_HW_DBG(hw, "\tCQ base address:           0x%lx\n",
+		    cq_dma_base);
+	DLB2_HW_DBG(hw, "\tCoS ID:                    %u\n", args->cos_id);
+	DLB2_HW_DBG(hw, "\tStrict CoS allocation:     %u\n",
+		    args->cos_strict);
+}
+
+static int
+dlb2_verify_create_ldb_port_args(struct dlb2_hw *hw,
+				 u32 domain_id,
+				 uintptr_t cq_dma_base,
+				 struct dlb2_create_ldb_port_args *args,
+				 struct dlb2_cmd_response *resp,
+				 bool vdev_req,
+				 unsigned int vdev_id)
+{
+	struct dlb2_hw_domain *domain;
+	int i;
+
+	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
+
+	if (!domain) {
+		resp->status = DLB2_ST_INVALID_DOMAIN_ID;
+		return -EINVAL;
+	}
+
+	if (!domain->configured) {
+		resp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;
+		return -EINVAL;
+	}
+
+	if (domain->started) {
+		resp->status = DLB2_ST_DOMAIN_STARTED;
+		return -EINVAL;
+	}
+
+	if (args->cos_id >= DLB2_NUM_COS_DOMAINS) {
+		resp->status = DLB2_ST_INVALID_COS_ID;
+		return -EINVAL;
+	}
+
+	if (args->cos_strict) {
+		if (dlb2_list_empty(&domain->avail_ldb_ports[args->cos_id])) {
+			resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
+			return -EINVAL;
+		}
+	} else {
+		for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
+			if (!dlb2_list_empty(&domain->avail_ldb_ports[i]))
+				break;
+		}
+
+		if (i == DLB2_NUM_COS_DOMAINS) {
+			resp->status = DLB2_ST_LDB_PORTS_UNAVAILABLE;
+			return -EINVAL;
+		}
+	}
+
+	/* Check cache-line alignment */
+	if ((cq_dma_base & 0x3F) != 0) {
+		resp->status = DLB2_ST_INVALID_CQ_VIRT_ADDR;
+		return -EINVAL;
+	}
+
+	if (args->cq_depth != 1 &&
+	    args->cq_depth != 2 &&
+	    args->cq_depth != 4 &&
+	    args->cq_depth != 8 &&
+	    args->cq_depth != 16 &&
+	    args->cq_depth != 32 &&
+	    args->cq_depth != 64 &&
+	    args->cq_depth != 128 &&
+	    args->cq_depth != 256 &&
+	    args->cq_depth != 512 &&
+	    args->cq_depth != 1024) {
+		resp->status = DLB2_ST_INVALID_CQ_DEPTH;
+		return -EINVAL;
+	}
+
+	/* The history list size must be >= 1 */
+	if (!args->cq_history_list_size) {
+		resp->status = DLB2_ST_INVALID_HIST_LIST_DEPTH;
+		return -EINVAL;
+	}
+
+	if (args->cq_history_list_size > domain->avail_hist_list_entries) {
+		resp->status = DLB2_ST_HIST_LIST_ENTRIES_UNAVAILABLE;
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+
+/**
+ * dlb2_hw_create_ldb_port() - Allocate and initialize a load-balanced port and
+ *	its resources.
+ * @hw:	Contains the current state of the DLB2 hardware.
+ * @domain_id: Domain ID
+ * @args: User-provided arguments.
+ * @cq_dma_base: Base DMA address for consumer queue memory
+ * @resp: Response to user.
+ * @vdev_req: Request came from a virtual device.
+ * @vdev_id: If vdev_req is true, this contains the virtual device's ID.
+ *
+ * Return: returns < 0 on error, 0 otherwise. If the driver is unable to
+ * satisfy a request, resp->status will be set accordingly.
+ */
+int dlb2_hw_create_ldb_port(struct dlb2_hw *hw,
+			    u32 domain_id,
+			    struct dlb2_create_ldb_port_args *args,
+			    uintptr_t cq_dma_base,
+			    struct dlb2_cmd_response *resp,
+			    bool vdev_req,
+			    unsigned int vdev_id)
+{
+	struct dlb2_hw_domain *domain;
+	struct dlb2_ldb_port *port;
+	int ret, cos_id, i;
+
+	dlb2_log_create_ldb_port_args(hw,
+				      domain_id,
+				      cq_dma_base,
+				      args,
+				      vdev_req,
+				      vdev_id);
+
+	/*
+	 * Verify that hardware resources are available before attempting to
+	 * satisfy the request. This simplifies the error unwinding code.
+	 */
+	ret = dlb2_verify_create_ldb_port_args(hw,
+					       domain_id,
+					       cq_dma_base,
+					       args,
+					       resp,
+					       vdev_req,
+					       vdev_id);
+	if (ret)
+		return ret;
+
+	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
+	if (!domain) {
+		DLB2_HW_ERR(hw,
+			    "[%s():%d] Internal error: domain not found\n",
+			    __func__, __LINE__);
+		return -EFAULT;
+	}
+
+	if (args->cos_strict) {
+		cos_id = args->cos_id;
+
+		port = DLB2_DOM_LIST_HEAD(domain->avail_ldb_ports[cos_id],
+					  typeof(*port));
+	} else {
+		int idx;
+
+		for (i = 0; i < DLB2_NUM_COS_DOMAINS; i++) {
+			idx = (args->cos_id + i) % DLB2_NUM_COS_DOMAINS;
+
+			port = DLB2_DOM_LIST_HEAD(domain->avail_ldb_ports[idx],
+						  typeof(*port));
+			if (port)
+				break;
+		}
+
+		cos_id = idx;
+	}
+
+	if (!port) {
+		DLB2_HW_ERR(hw,
+			    "[%s():%d] Internal error: no available ldb ports\n",
+			    __func__, __LINE__);
+		return -EFAULT;
+	}
+
+	if (port->configured) {
+		DLB2_HW_ERR(hw,
+			    "[%s()] Internal error: avail_ldb_ports contains configured ports.\n",
+			    __func__);
+		return -EFAULT;
+	}
+
+	ret = dlb2_configure_ldb_port(hw,
+				      domain,
+				      port,
+				      cq_dma_base,
+				      args,
+				      vdev_req,
+				      vdev_id);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * Configuration succeeded, so move the resource from the 'avail' to
+	 * the 'used' list.
+	 */
+	dlb2_list_del(&domain->avail_ldb_ports[cos_id], &port->domain_list);
+
+	dlb2_list_add(&domain->used_ldb_ports[cos_id], &port->domain_list);
+
+	resp->status = 0;
+	resp->id = (vdev_req) ? port->id.virt_id : port->id.phys_id;
+
+	return 0;
+}
+
+static void
+dlb2_log_create_dir_port_args(struct dlb2_hw *hw,
+			      u32 domain_id,
+			      uintptr_t cq_dma_base,
+			      struct dlb2_create_dir_port_args *args,
+			      bool vdev_req,
+			      unsigned int vdev_id)
+{
+	DLB2_HW_DBG(hw, "DLB2 create directed port arguments:\n");
+	if (vdev_req)
+		DLB2_HW_DBG(hw, "(Request from vdev %d)\n", vdev_id);
+	DLB2_HW_DBG(hw, "\tDomain ID:                 %d\n",
+		    domain_id);
+	DLB2_HW_DBG(hw, "\tCQ depth:                  %d\n",
+		    args->cq_depth);
+	DLB2_HW_DBG(hw, "\tCQ base address:           0x%lx\n",
+		    cq_dma_base);
+}
+
+static struct dlb2_dir_pq_pair *
+dlb2_get_domain_used_dir_pq(u32 id,
+			    bool vdev_req,
+			    struct dlb2_hw_domain *domain)
+{
+	struct dlb2_list_entry *iter;
+	struct dlb2_dir_pq_pair *port;
+	RTE_SET_USED(iter);
+
+	if (id >= DLB2_MAX_NUM_DIR_PORTS)
+		return NULL;
+
+	DLB2_DOM_LIST_FOR(domain->used_dir_pq_pairs, port, iter)
+		if ((!vdev_req && port->id.phys_id == id) ||
+		    (vdev_req && port->id.virt_id == id))
+			return port;
+
+	return NULL;
+}
+
+static int
+dlb2_verify_create_dir_port_args(struct dlb2_hw *hw,
+				 u32 domain_id,
+				 uintptr_t cq_dma_base,
+				 struct dlb2_create_dir_port_args *args,
+				 struct dlb2_cmd_response *resp,
+				 bool vdev_req,
+				 unsigned int vdev_id)
+{
+	struct dlb2_hw_domain *domain;
+
+	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
+
+	if (!domain) {
+		resp->status = DLB2_ST_INVALID_DOMAIN_ID;
+		return -EINVAL;
+	}
+
+	if (!domain->configured) {
+		resp->status = DLB2_ST_DOMAIN_NOT_CONFIGURED;
+		return -EINVAL;
+	}
+
+	if (domain->started) {
+		resp->status = DLB2_ST_DOMAIN_STARTED;
+		return -EINVAL;
+	}
+
+	/*
+	 * If the user claims the queue is already configured, validate
+	 * the queue ID, its domain, and whether the queue is configured.
+	 */
+	if (args->queue_id != -1) {
+		struct dlb2_dir_pq_pair *queue;
+
+		queue = dlb2_get_domain_used_dir_pq(args->queue_id,
+						    vdev_req,
+						    domain);
+
+		if (!queue || queue->domain_id.phys_id != domain->id.phys_id ||
+		    !queue->queue_configured) {
+			resp->status = DLB2_ST_INVALID_DIR_QUEUE_ID;
+			return -EINVAL;
+		}
+	}
+
+	/*
+	 * If the port's queue is not configured, validate that a free
+	 * port-queue pair is available.
+	 */
+	if (args->queue_id == -1 &&
+	    dlb2_list_empty(&domain->avail_dir_pq_pairs)) {
+		resp->status = DLB2_ST_DIR_PORTS_UNAVAILABLE;
+		return -EINVAL;
+	}
+
+	/* Check cache-line alignment */
+	if ((cq_dma_base & 0x3F) != 0) {
+		resp->status = DLB2_ST_INVALID_CQ_VIRT_ADDR;
+		return -EINVAL;
+	}
+
+	if (args->cq_depth != 1 &&
+	    args->cq_depth != 2 &&
+	    args->cq_depth != 4 &&
+	    args->cq_depth != 8 &&
+	    args->cq_depth != 16 &&
+	    args->cq_depth != 32 &&
+	    args->cq_depth != 64 &&
+	    args->cq_depth != 128 &&
+	    args->cq_depth != 256 &&
+	    args->cq_depth != 512 &&
+	    args->cq_depth != 1024) {
+		resp->status = DLB2_ST_INVALID_CQ_DEPTH;
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static void dlb2_dir_port_configure_pp(struct dlb2_hw *hw,
+				       struct dlb2_hw_domain *domain,
+				       struct dlb2_dir_pq_pair *port,
+				       bool vdev_req,
+				       unsigned int vdev_id)
+{
+	union dlb2_sys_dir_pp2vas r0 = { {0} };
+	union dlb2_sys_dir_pp_v r4 = { {0} };
+
+	r0.field.vas = domain->id.phys_id;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_DIR_PP2VAS(port->id.phys_id), r0.val);
+
+	if (vdev_req) {
+		union dlb2_sys_vf_dir_vpp2pp r1 = { {0} };
+		union dlb2_sys_dir_pp2vdev r2 = { {0} };
+		union dlb2_sys_vf_dir_vpp_v r3 = { {0} };
+		unsigned int offs;
+		u32 virt_id;
+
+		/*
+		 * DLB uses producer port address bits 17:12 to determine the
+		 * producer port ID. In Scalable IOV mode, PP accesses come
+		 * through the PF MMIO window for the physical producer port,
+		 * so for translation purposes the virtual and physical port
+		 * IDs are equal.
+		 */
+		if (hw->virt_mode == DLB2_VIRT_SRIOV)
+			virt_id = port->id.virt_id;
+		else
+			virt_id = port->id.phys_id;
+
+		r1.field.pp = port->id.phys_id;
+
+		offs = vdev_id * DLB2_MAX_NUM_DIR_PORTS + virt_id;
+
+		DLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP2PP(offs), r1.val);
+
+		r2.field.vdev = vdev_id;
+
+		DLB2_CSR_WR(hw,
+			    DLB2_SYS_DIR_PP2VDEV(port->id.phys_id),
+			    r2.val);
+
+		r3.field.vpp_v = 1;
+
+		DLB2_CSR_WR(hw, DLB2_SYS_VF_DIR_VPP_V(offs), r3.val);
+	}
+
+	r4.field.pp_v = 1;
+
+	DLB2_CSR_WR(hw,
+		    DLB2_SYS_DIR_PP_V(port->id.phys_id),
+		    r4.val);
+}
+
+static int dlb2_dir_port_configure_cq(struct dlb2_hw *hw,
+				      struct dlb2_hw_domain *domain,
+				      struct dlb2_dir_pq_pair *port,
+				      uintptr_t cq_dma_base,
+				      struct dlb2_create_dir_port_args *args,
+				      bool vdev_req,
+				      unsigned int vdev_id)
+{
+	union dlb2_sys_dir_cq_addr_l r0 = { {0} };
+	union dlb2_sys_dir_cq_addr_u r1 = { {0} };
+	union dlb2_sys_dir_cq2vf_pf_ro r2 = { {0} };
+	union dlb2_chp_dir_cq_tkn_depth_sel r3 = { {0} };
+	union dlb2_lsp_cq_dir_tkn_depth_sel_dsi r4 = { {0} };
+	union dlb2_sys_dir_cq_fmt r9 = { {0} };
+	union dlb2_sys_dir_cq_at r10 = { {0} };
+	union dlb2_sys_dir_cq_pasid r11 = { {0} };
+	union dlb2_chp_dir_cq2vas r12 = { {0} };
+
+	/* The CQ address is 64B-aligned, and the DLB only wants bits [63:6] */
+	r0.field.addr_l = cq_dma_base >> 6;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_ADDR_L(port->id.phys_id), r0.val);
+
+	r1.field.addr_u = cq_dma_base >> 32;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_ADDR_U(port->id.phys_id), r1.val);
+
+	/*
+	 * 'ro' == relaxed ordering. This setting allows DLB2 to write
+	 * cache lines out-of-order (but QEs within a cache line are always
+	 * updated in-order).
+	 */
+	r2.field.vf = vdev_id;
+	r2.field.is_pf = !vdev_req && (hw->virt_mode != DLB2_VIRT_SIOV);
+	r2.field.ro = 1;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ2VF_PF_RO(port->id.phys_id), r2.val);
+
+	if (args->cq_depth <= 8) {
+		r3.field.token_depth_select = 1;
+	} else if (args->cq_depth == 16) {
+		r3.field.token_depth_select = 2;
+	} else if (args->cq_depth == 32) {
+		r3.field.token_depth_select = 3;
+	} else if (args->cq_depth == 64) {
+		r3.field.token_depth_select = 4;
+	} else if (args->cq_depth == 128) {
+		r3.field.token_depth_select = 5;
+	} else if (args->cq_depth == 256) {
+		r3.field.token_depth_select = 6;
+	} else if (args->cq_depth == 512) {
+		r3.field.token_depth_select = 7;
+	} else if (args->cq_depth == 1024) {
+		r3.field.token_depth_select = 8;
+	} else {
+		DLB2_HW_ERR(hw,
+			    "[%s():%d] Internal error: invalid CQ depth\n",
+			    __func__, __LINE__);
+		return -EFAULT;
+	}
+
+	DLB2_CSR_WR(hw,
+		    DLB2_CHP_DIR_CQ_TKN_DEPTH_SEL(port->id.phys_id),
+		    r3.val);
+
+	/*
+	 * To support CQs with depth less than 8, program the token count
+	 * register with a non-zero initial value. Operations such as domain
+	 * reset must take this initial value into account when quiescing the
+	 * CQ.
+	 */
+	port->init_tkn_cnt = 0;
+
+	if (args->cq_depth < 8) {
+		union dlb2_lsp_cq_dir_tkn_cnt r13 = { {0} };
+
+		port->init_tkn_cnt = 8 - args->cq_depth;
+
+		r13.field.count = port->init_tkn_cnt;
+
+		DLB2_CSR_WR(hw,
+			    DLB2_LSP_CQ_DIR_TKN_CNT(port->id.phys_id),
+			    r13.val);
+	} else {
+		DLB2_CSR_WR(hw,
+			    DLB2_LSP_CQ_DIR_TKN_CNT(port->id.phys_id),
+			    DLB2_LSP_CQ_DIR_TKN_CNT_RST);
+	}
+
+	r4.field.token_depth_select = r3.field.token_depth_select;
+	r4.field.disable_wb_opt = 0;
+	r4.field.ignore_depth = 0;
+
+	DLB2_CSR_WR(hw,
+		    DLB2_LSP_CQ_DIR_TKN_DEPTH_SEL_DSI(port->id.phys_id),
+		    r4.val);
+
+	/* Reset the CQ write pointer */
+	DLB2_CSR_WR(hw,
+		    DLB2_CHP_DIR_CQ_WPTR(port->id.phys_id),
+		    DLB2_CHP_DIR_CQ_WPTR_RST);
+
+	/* Virtualize the PPID */
+	r9.field.keep_pf_ppid = 0;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_FMT(port->id.phys_id), r9.val);
+
+	/*
+	 * Address translation (AT) settings: 0: untranslated, 2: translated
+	 * (see ATS spec regarding Address Type field for more details)
+	 */
+	r10.field.cq_at = 0;
+
+	DLB2_CSR_WR(hw, DLB2_SYS_DIR_CQ_AT(port->id.phys_id), r10.val);
+
+	if (vdev_req && hw->virt_mode == DLB2_VIRT_SIOV) {
+		r11.field.pasid = hw->pasid[vdev_id];
+		r11.field.fmt2 = 1;
+	}
+
+	DLB2_CSR_WR(hw,
+		    DLB2_SYS_DIR_CQ_PASID(port->id.phys_id),
+		    r11.val);
+
+	r12.field.cq2vas = domain->id.phys_id;
+
+	DLB2_CSR_WR(hw, DLB2_CHP_DIR_CQ2VAS(port->id.phys_id), r12.val);
+
+	return 0;
+}
+
+static int dlb2_configure_dir_port(struct dlb2_hw *hw,
+				   struct dlb2_hw_domain *domain,
+				   struct dlb2_dir_pq_pair *port,
+				   uintptr_t cq_dma_base,
+				   struct dlb2_create_dir_port_args *args,
+				   bool vdev_req,
+				   unsigned int vdev_id)
+{
+	int ret;
+
+	ret = dlb2_dir_port_configure_cq(hw,
+					 domain,
+					 port,
+					 cq_dma_base,
+					 args,
+					 vdev_req,
+					 vdev_id);
+
+	if (ret < 0)
+		return ret;
+
+	dlb2_dir_port_configure_pp(hw,
+				   domain,
+				   port,
+				   vdev_req,
+				   vdev_id);
+
+	dlb2_dir_port_cq_enable(hw, port);
+
+	port->enabled = true;
+
+	port->port_configured = true;
+
+	return 0;
+}
+
+/**
+ * dlb2_hw_create_dir_port() - Allocate and initialize a DLB directed port
+ *	and queue. The port/queue pair have the same ID and name.
+ * @hw:	Contains the current state of the DLB2 hardware.
+ * @domain_id: Domain ID
+ * @args: User-provided arguments.
+ * @cq_dma_base: Base DMA address for consumer queue memory
+ * @resp: Response to user.
+ * @vdev_req: Request came from a virtual device.
+ * @vdev_id: If vdev_req is true, this contains the virtual device's ID.
+ *
+ * Return: returns < 0 on error, 0 otherwise. If the driver is unable to
+ * satisfy a request, resp->status will be set accordingly.
+ */
+int dlb2_hw_create_dir_port(struct dlb2_hw *hw,
+			    u32 domain_id,
+			    struct dlb2_create_dir_port_args *args,
+			    uintptr_t cq_dma_base,
+			    struct dlb2_cmd_response *resp,
+			    bool vdev_req,
+			    unsigned int vdev_id)
+{
+	struct dlb2_dir_pq_pair *port;
+	struct dlb2_hw_domain *domain;
+	int ret;
+
+	dlb2_log_create_dir_port_args(hw,
+				      domain_id,
+				      cq_dma_base,
+				      args,
+				      vdev_req,
+				      vdev_id);
+
+	/*
+	 * Verify that hardware resources are available before attempting to
+	 * satisfy the request. This simplifies the error unwinding code.
+	 */
+	ret = dlb2_verify_create_dir_port_args(hw,
+					       domain_id,
+					       cq_dma_base,
+					       args,
+					       resp,
+					       vdev_req,
+					       vdev_id);
+	if (ret)
+		return ret;
+
+	domain = dlb2_get_domain_from_id(hw, domain_id, vdev_req, vdev_id);
+
+	if (args->queue_id != -1)
+		port = dlb2_get_domain_used_dir_pq(args->queue_id,
+						   vdev_req,
+						   domain);
+	else
+		port = DLB2_DOM_LIST_HEAD(domain->avail_dir_pq_pairs,
+					  typeof(*port));
+	if (!port) {
+		DLB2_HW_ERR(hw,
+			    "[%s():%d] Internal error: no available dir ports\n",
+			    __func__, __LINE__);
+		return -EFAULT;
+	}
+
+	ret = dlb2_configure_dir_port(hw,
+				      domain,
+				      port,
+				      cq_dma_base,
+				      args,
+				      vdev_req,
+				      vdev_id);
+	if (ret < 0)
+		return ret;
+
+	/*
+	 * Configuration succeeded, so move the resource from the 'avail' to
+	 * the 'used' list (if it's not already there).
+	 */
+	if (args->queue_id == -1) {
+		dlb2_list_del(&domain->avail_dir_pq_pairs, &port->domain_list);
+
+		dlb2_list_add(&domain->used_dir_pq_pairs, &port->domain_list);
+	}
+
+	resp->status = 0;
+	resp->id = (vdev_req) ? port->id.virt_id : port->id.phys_id;
+
+	return 0;
+}
diff --git a/drivers/event/dlb2/pf/dlb2_main.c b/drivers/event/dlb2/pf/dlb2_main.c
index b8e32ab..582ef53 100644
--- a/drivers/event/dlb2/pf/dlb2_main.c
+++ b/drivers/event/dlb2/pf/dlb2_main.c
@@ -642,3 +642,31 @@  dlb2_pf_create_ldb_queue(struct dlb2_hw *hw,
 	return dlb2_hw_create_ldb_queue(hw, id, args, resp, NOT_VF_REQ,
 					PF_ID_ZERO);
 }
+
+int
+dlb2_pf_create_ldb_port(struct dlb2_hw *hw,
+			u32 id,
+			struct dlb2_create_ldb_port_args *args,
+			uintptr_t cq_dma_base,
+			struct dlb2_cmd_response *resp)
+{
+	return dlb2_hw_create_ldb_port(hw, id, args,
+				       cq_dma_base,
+				       resp,
+				       NOT_VF_REQ,
+				       PF_ID_ZERO);
+}
+
+int
+dlb2_pf_create_dir_port(struct dlb2_hw *hw,
+			u32 id,
+			struct dlb2_create_dir_port_args *args,
+			uintptr_t cq_dma_base,
+			struct dlb2_cmd_response *resp)
+{
+	return dlb2_hw_create_dir_port(hw, id, args,
+				       cq_dma_base,
+				       resp,
+				       NOT_VF_REQ,
+				       PF_ID_ZERO);
+}
diff --git a/drivers/event/dlb2/pf/dlb2_pf.c b/drivers/event/dlb2/pf/dlb2_pf.c
index dea70e6..a6824b1 100644
--- a/drivers/event/dlb2/pf/dlb2_pf.c
+++ b/drivers/event/dlb2/pf/dlb2_pf.c
@@ -234,6 +234,183 @@  dlb2_pf_set_sn_allocation(struct dlb2_hw_dev *handle,
 	return ret;
 }
 
+static void *
+dlb2_alloc_coherent_aligned(uintptr_t *phys, size_t size, int align)
+{
+	const struct rte_memzone *mz;
+	char mz_name[RTE_MEMZONE_NAMESIZE];
+	uint32_t core_id = rte_lcore_id();
+	unsigned int socket_id;
+
+	snprintf(mz_name, sizeof(mz_name) - 1, "%lx",
+		 (unsigned long)rte_get_timer_cycles());
+	if (core_id == (unsigned int)LCORE_ID_ANY)
+		core_id = rte_get_master_lcore();
+	socket_id = rte_lcore_to_socket_id(core_id);
+	mz = rte_memzone_reserve_aligned(mz_name, size, socket_id,
+					 RTE_MEMZONE_IOVA_CONTIG, align);
+	if (!mz) {
+		DLB2_LOG_DBG("Unable to allocate DMA memory of size %zu bytes - %s\n",
+			     size, rte_strerror(rte_errno));
+		*phys = 0;
+		return NULL;
+	}
+	*phys = mz->iova;
+	return mz->addr;
+}
+
+static int
+dlb2_pf_ldb_port_create(struct dlb2_hw_dev *handle,
+			struct dlb2_create_ldb_port_args *cfg,
+			enum dlb2_cq_poll_modes poll_mode)
+{
+	struct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;
+	struct dlb2_cmd_response response = {0};
+	struct dlb2_port_memory port_memory;
+	int ret, cq_alloc_depth;
+	uint8_t *port_base;
+	int alloc_sz, qe_sz;
+	phys_addr_t cq_base;
+	phys_addr_t pp_base;
+	int is_dir = false;
+
+	DLB2_INFO(dev->dlb2_device, "Entering %s()\n", __func__);
+
+	if (poll_mode == DLB2_CQ_POLL_MODE_STD)
+		qe_sz = sizeof(struct dlb2_dequeue_qe);
+	else
+		qe_sz = RTE_CACHE_LINE_SIZE;
+
+	/* Calculate the port memory required, and round up to the nearest
+	 * cache line.
+	 */
+	cq_alloc_depth = RTE_MAX(cfg->cq_depth, DLB2_MIN_HARDWARE_CQ_DEPTH);
+	alloc_sz = cq_alloc_depth * qe_sz;
+	alloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);
+
+	port_base = dlb2_alloc_coherent_aligned(&cq_base,
+						alloc_sz,
+						PAGE_SIZE);
+	if (port_base == NULL)
+		return -ENOMEM;
+
+	/* Lock the page in memory */
+	ret = rte_mem_lock_page(port_base);
+	if (ret < 0) {
+		DLB2_LOG_ERR("dlb2 pf pmd could not lock page for device i/o\n");
+		goto create_port_err;
+	}
+
+
+	memset(port_base, 0, alloc_sz);
+
+	ret = dlb2_pf_create_ldb_port(&dlb2_dev->hw,
+				      handle->domain_id,
+				      cfg,
+				      cq_base,
+				      &response);
+	if (ret)
+		goto create_port_err;
+
+	pp_base = (uintptr_t)dlb2_dev->hw.func_kva + PP_BASE(is_dir);
+	dlb2_port[response.id][DLB2_LDB_PORT].pp_addr =
+		(void *)(uintptr_t)(pp_base + (PAGE_SIZE * response.id));
+
+	dlb2_port[response.id][DLB2_LDB_PORT].cq_base =
+		(void *)(uintptr_t)(port_base);
+	memset(&port_memory, 0, sizeof(port_memory));
+	dlb2_list_init_head(&port_memory.list);
+
+	/* Fill out the per-port memory tracking structure */
+	dlb2_dev->ldb_port_pages[response.id].valid = true;
+	dlb2_list_splice(&port_memory.list,
+			 &dlb2_dev->ldb_port_pages[response.id].list);
+
+	cfg->response = response;
+
+	DLB2_INFO(dev->dlb2_device, "Exiting %s() with ret=%d\n",
+		  __func__, ret);
+
+create_port_err:
+
+	return ret;
+}
+
+static int
+dlb2_pf_dir_port_create(struct dlb2_hw_dev *handle,
+			struct dlb2_create_dir_port_args *cfg,
+			enum dlb2_cq_poll_modes poll_mode)
+{
+	struct dlb2_dev *dlb2_dev = (struct dlb2_dev *)handle->pf_dev;
+	struct dlb2_cmd_response response = {0};
+	struct dlb2_port_memory port_memory;
+	int ret;
+	uint8_t *port_base;
+	int alloc_sz, qe_sz;
+	phys_addr_t cq_base;
+	phys_addr_t pp_base;
+	int is_dir = true;
+
+	DLB2_INFO(dev->dlb2_device, "Entering %s()\n", __func__);
+
+	if (poll_mode == DLB2_CQ_POLL_MODE_STD)
+		qe_sz = sizeof(struct dlb2_dequeue_qe);
+	else
+		qe_sz = RTE_CACHE_LINE_SIZE;
+
+	/* Calculate the port memory required, and round up to the nearest
+	 * cache line.
+	 */
+	alloc_sz = cfg->cq_depth * qe_sz;
+	alloc_sz = RTE_CACHE_LINE_ROUNDUP(alloc_sz);
+
+	port_base = dlb2_alloc_coherent_aligned(&cq_base,
+						alloc_sz,
+						PAGE_SIZE);
+	if (port_base == NULL)
+		return -ENOMEM;
+
+	/* Lock the page in memory */
+	ret = rte_mem_lock_page(port_base);
+	if (ret < 0) {
+		DLB2_LOG_ERR("dlb2 pf pmd could not lock page for device i/o\n");
+		goto create_port_err;
+	}
+
+	memset(port_base, 0, alloc_sz);
+
+	ret = dlb2_pf_create_dir_port(&dlb2_dev->hw,
+				      handle->domain_id,
+				      cfg,
+				      cq_base,
+				      &response);
+	if (ret)
+		goto create_port_err;
+
+	pp_base = (uintptr_t)dlb2_dev->hw.func_kva + PP_BASE(is_dir);
+	dlb2_port[response.id][DLB2_DIR_PORT].pp_addr =
+		(void *)(uintptr_t)(pp_base + (PAGE_SIZE * response.id));
+
+	dlb2_port[response.id][DLB2_DIR_PORT].cq_base =
+		(void *)(uintptr_t)(port_base);
+	memset(&port_memory, 0, sizeof(port_memory));
+	dlb2_list_init_head(&port_memory.list);
+
+	/* Fill out the per-port memory tracking structure */
+	dlb2_dev->dir_port_pages[response.id].valid = true;
+	dlb2_list_splice(&port_memory.list,
+			 &dlb2_dev->dir_port_pages[response.id].list);
+
+	cfg->response = response;
+
+	DLB2_INFO(dev->dlb2_device, "Exiting %s() with ret=%d\n",
+		  __func__, ret);
+
+create_port_err:
+
+	return ret;
+}
+
 static void
 dlb2_pf_iface_fn_ptrs_init(void)
 {
@@ -247,6 +424,8 @@  dlb2_pf_iface_fn_ptrs_init(void)
 	dlb2_iface_get_cq_poll_mode = dlb2_pf_get_cq_poll_mode;
 	dlb2_iface_sched_domain_create = dlb2_pf_sched_domain_create;
 	dlb2_iface_ldb_queue_create = dlb2_pf_ldb_queue_create;
+	dlb2_iface_ldb_port_create = dlb2_pf_ldb_port_create;
+	dlb2_iface_dir_port_create = dlb2_pf_dir_port_create;
 	dlb2_iface_get_sn_allocation = dlb2_pf_get_sn_allocation;
 	dlb2_iface_set_sn_allocation = dlb2_pf_set_sn_allocation;
 	dlb2_iface_get_sn_occupancy = dlb2_pf_get_sn_occupancy;