From patchwork Tue Aug 18 23:46:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chautru, Nicolas" X-Patchwork-Id: 75659 X-Patchwork-Delegate: gakhil@marvell.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 55494A04AF; Wed, 19 Aug 2020 01:48:46 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id AC7881C0B2; Wed, 19 Aug 2020 01:48:24 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 55EC45F69 for ; Wed, 19 Aug 2020 01:48:19 +0200 (CEST) IronPort-SDR: xaRiNDyJVBvBaPU6LMqpmW4PZtGElj5UWCLdQCRJCLEZ1IPetK7IJeckXH5CXhvEDLqw3mbQXk 1YfMmP9uUuIQ== X-IronPort-AV: E=McAfee;i="6000,8403,9717"; a="152642092" X-IronPort-AV: E=Sophos;i="5.76,329,1592895600"; d="scan'208";a="152642092" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 18 Aug 2020 16:48:16 -0700 IronPort-SDR: xeoTVY557ay8UktrbxDCwmw5wzH3iXetZoRz9ConMBclumBkAuV6xUq0AJa4sGAeSsE/7J28fR YLpasmvizouA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.76,329,1592895600"; d="scan'208";a="329138182" Received: from skx-5gnr-sc12-4.sc.intel.com ([172.25.69.210]) by fmsmga002.fm.intel.com with ESMTP; 18 Aug 2020 16:48:16 -0700 From: Nicolas Chautru To: dev@dpdk.org, akhil.goyal@nxp.com Cc: bruce.richardson@intel.com, Nicolas Chautru Date: Tue, 18 Aug 2020 16:46:23 -0700 Message-Id: <1597794387-37526-4-git-send-email-nicolas.chautru@intel.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1597794387-37526-1-git-send-email-nicolas.chautru@intel.com> References: <1597794387-37526-1-git-send-email-nicolas.chautru@intel.com> Subject: [dpdk-dev] [PATCH v1 3/7] app/bbdev: include explict HARQ preloading X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Run preloading explictly for unit tests. Load each code block by reusing existing input op then restore for the actual test. Signed-off-by: Nicolas Chautru --- app/test-bbdev/main.h | 1 + app/test-bbdev/test_bbdev_perf.c | 51 +++++++++++++++++++++------------------- 2 files changed, 28 insertions(+), 24 deletions(-) diff --git a/app/test-bbdev/main.h b/app/test-bbdev/main.h index fb3dec8..dc10a50 100644 --- a/app/test-bbdev/main.h +++ b/app/test-bbdev/main.h @@ -17,6 +17,7 @@ #define TEST_SKIPPED 1 #define MAX_BURST 512U +#define MAX_OPS 1024U #define DEFAULT_BURST 32U #define DEFAULT_OPS 64U #define DEFAULT_ITER 6U diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c index b0b6f18..d0d2a55 100644 --- a/app/test-bbdev/test_bbdev_perf.c +++ b/app/test-bbdev/test_bbdev_perf.c @@ -2442,20 +2442,20 @@ typedef int (test_case_function)(struct active_device *ad, bool preload) { uint16_t j; - int ret; - uint32_t harq_offset = (uint32_t) queue_id * HARQ_INCR * 1024; - struct rte_bbdev_op_data save_hc_in, save_hc_out; - struct rte_bbdev_dec_op *ops_deq[MAX_BURST]; + int deq; + uint32_t harq_offset = (uint32_t) queue_id * HARQ_INCR * MAX_OPS; + struct rte_bbdev_op_data save_hc_in[MAX_OPS], save_hc_out[MAX_OPS]; + struct rte_bbdev_dec_op *ops_deq[MAX_OPS]; uint32_t flags = ops[0]->ldpc_dec.op_flags; bool mem_in = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_IN_ENABLE; bool hc_in = flags & RTE_BBDEV_LDPC_HQ_COMBINE_IN_ENABLE; bool mem_out = flags & RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE; bool hc_out = flags & RTE_BBDEV_LDPC_HQ_COMBINE_OUT_ENABLE; bool h_comp = flags & RTE_BBDEV_LDPC_HARQ_6BIT_COMPRESSION; - for (j = 0; j < n; ++j) { - if ((mem_in || hc_in) && preload) { - save_hc_in = ops[j]->ldpc_dec.harq_combined_input; - save_hc_out = ops[j]->ldpc_dec.harq_combined_output; + if ((mem_in || hc_in) && preload) { + for (j = 0; j < n; ++j) { + save_hc_in[j] = ops[j]->ldpc_dec.harq_combined_input; + save_hc_out[j] = ops[j]->ldpc_dec.harq_combined_output; ops[j]->ldpc_dec.op_flags = RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_LOOPBACK + RTE_BBDEV_LDPC_INTERNAL_HARQ_MEMORY_OUT_ENABLE; @@ -2465,16 +2465,23 @@ typedef int (test_case_function)(struct active_device *ad, ops[j]->ldpc_dec.harq_combined_output.offset = harq_offset; ops[j]->ldpc_dec.harq_combined_input.offset = 0; - rte_bbdev_enqueue_ldpc_dec_ops(dev_id, queue_id, - &ops[j], 1); - ret = 0; - while (ret == 0) - ret = rte_bbdev_dequeue_ldpc_dec_ops( - dev_id, queue_id, &ops_deq[j], 1); + harq_offset += HARQ_INCR; + } + rte_bbdev_enqueue_ldpc_dec_ops(dev_id, queue_id, &ops[0], n); + deq = 0; + while (deq != n) + deq += rte_bbdev_dequeue_ldpc_dec_ops( + dev_id, queue_id, &ops_deq[deq], + n - deq); + /* Restore the operations */ + for (j = 0; j < n; ++j) { ops[j]->ldpc_dec.op_flags = flags; - ops[j]->ldpc_dec.harq_combined_input = save_hc_in; - ops[j]->ldpc_dec.harq_combined_output = save_hc_out; + ops[j]->ldpc_dec.harq_combined_input = save_hc_in[j]; + ops[j]->ldpc_dec.harq_combined_output = save_hc_out[j]; } + } + harq_offset = (uint32_t) queue_id * HARQ_INCR * MAX_OPS; + for (j = 0; j < n; ++j) { /* Adjust HARQ offset when we reach external DDR */ if (mem_in || hc_in) ops[j]->ldpc_dec.harq_combined_input.offset @@ -3160,11 +3167,9 @@ typedef int (test_case_function)(struct active_device *ad, mbuf_reset( ops_enq[j]->ldpc_dec.harq_combined_output.data); } - if (extDdr) { - bool preload = i == (TEST_REPETITIONS - 1); + if (extDdr) preload_harq_ddr(tp->dev_id, queue_id, ops_enq, - num_ops, preload); - } + num_ops, true); start_time = rte_rdtsc_precise(); for (enq = 0, deq = 0; enq < num_ops;) { @@ -3291,11 +3296,9 @@ typedef int (test_case_function)(struct active_device *ad, mbuf_reset( ops_enq[j]->ldpc_dec.harq_combined_output.data); } - if (extDdr) { - bool preload = i == (TEST_REPETITIONS - 1); + if (extDdr) preload_harq_ddr(tp->dev_id, queue_id, ops_enq, - num_ops, preload); - } + num_ops, true); start_time = rte_rdtsc_precise(); for (enq = 0, deq = 0; enq < num_ops;) {