From patchwork Tue Jul 21 07:20:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Junyu Jiang X-Patchwork-Id: 74522 X-Patchwork-Delegate: qi.z.zhang@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id D0EF7A0526; Tue, 21 Jul 2020 09:28:58 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 8B5331C000; Tue, 21 Jul 2020 09:28:57 +0200 (CEST) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by dpdk.org (Postfix) with ESMTP id AA0E71BFFF; Tue, 21 Jul 2020 09:28:55 +0200 (CEST) IronPort-SDR: PL1LuMyLki5XQk640Q77pUiAl0hWnIC8Q9TwssxeR+iO54Q+dWy4CJg6qX3myN7k2L99ResX8X QHPZ2B9vq8LQ== X-IronPort-AV: E=McAfee;i="6000,8403,9688"; a="234936589" X-IronPort-AV: E=Sophos;i="5.75,378,1589266800"; d="scan'208";a="234936589" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga002.jf.intel.com ([10.7.209.21]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Jul 2020 00:28:54 -0700 IronPort-SDR: HD3Pz4NPWdg+AjW3JZSawiv/KsjhsGufMKxojUHXh/oFbRAIdT37K8Lt9b+my/eD/YA88lfDfP GWlAnKLfoTsw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,378,1589266800"; d="scan'208";a="301531334" Received: from intel.sh.intel.com ([10.239.255.48]) by orsmga002.jf.intel.com with ESMTP; 21 Jul 2020 00:28:50 -0700 From: Junyu Jiang To: dev@dpdk.org Cc: Qi Zhang , Qiming Yang , Junyu Jiang , stable@dpdk.org Date: Tue, 21 Jul 2020 07:20:21 +0000 Message-Id: <20200721072021.38243-1-junyux.jiang@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200715070307.36814-1-junyux.jiang@intel.com> References: <20200715070307.36814-1-junyux.jiang@intel.com> Subject: [dpdk-dev] [PATCH v3] net/ice: fix incorrect Rx/Tx bytes statistics X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch fixed the issue that rx/tx bytes overflowed on 40 bit limitation by enlarging the limitation. Fixes: a37bde56314d ("net/ice: support statistics") Cc: stable@dpdk.org Signed-off-by: Junyu Jiang Acked-by: Qi Zhang --- drivers/net/ice/ice_ethdev.c | 28 ++++++++++++++++++++++++++++ drivers/net/ice/ice_ethdev.h | 7 +++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index 3534d18ca..950c27094 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -4156,6 +4156,13 @@ ice_update_vsi_stats(struct ice_vsi *vsi) ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx), vsi->offset_loaded, &oes->rx_broadcast, &nes->rx_broadcast); + /* enlarge the limitation when rx_bytes overflowed */ + if (vsi->offset_loaded) { + if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes) + nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; + nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes); + } + vsi->old_rx_bytes = nes->rx_bytes; /* exclude CRC bytes */ nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast + nes->rx_broadcast) * RTE_ETHER_CRC_LEN; @@ -4182,6 +4189,13 @@ ice_update_vsi_stats(struct ice_vsi *vsi) /* GLV_TDPC not supported */ ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded, &oes->tx_errors, &nes->tx_errors); + /* enlarge the limitation when tx_bytes overflowed */ + if (vsi->offset_loaded) { + if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes) + nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; + nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes); + } + vsi->old_tx_bytes = nes->tx_bytes; vsi->offset_loaded = true; PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************", @@ -4229,6 +4243,13 @@ ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) ice_stat_update_32(hw, PRTRPB_RDPC, pf->offset_loaded, &os->eth.rx_discards, &ns->eth.rx_discards); + /* enlarge the limitation when rx_bytes overflowed */ + if (pf->offset_loaded) { + if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes) + ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; + ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes); + } + pf->old_rx_bytes = ns->eth.rx_bytes; /* Workaround: CRC size should not be included in byte statistics, * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx @@ -4259,6 +4280,13 @@ ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw) GLPRT_BPTCL(hw->port_info->lport), pf->offset_loaded, &os->eth.tx_broadcast, &ns->eth.tx_broadcast); + /* enlarge the limitation when tx_bytes overflowed */ + if (pf->offset_loaded) { + if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes) + ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH; + ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes); + } + pf->old_tx_bytes = ns->eth.tx_bytes; ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast + ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN; diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 2bff735ca..87984ef9e 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -133,6 +133,9 @@ #define ICE_ETH_OVERHEAD \ (RTE_ETHER_HDR_LEN + RTE_ETHER_CRC_LEN + ICE_VLAN_TAG_SIZE * 2) +#define ICE_RXTX_BYTES_HIGH(bytes) ((bytes) & ~ICE_40_BIT_MASK) +#define ICE_RXTX_BYTES_LOW(bytes) ((bytes) & ICE_40_BIT_MASK) + /* DDP package type */ enum ice_pkg_type { ICE_PKG_TYPE_UNKNOWN, @@ -248,6 +251,8 @@ struct ice_vsi { struct ice_eth_stats eth_stats_offset; struct ice_eth_stats eth_stats; bool offset_loaded; + uint64_t old_rx_bytes; + uint64_t old_tx_bytes; }; enum proto_xtr_type { @@ -391,6 +396,8 @@ struct ice_pf { struct ice_parser_list perm_parser_list; struct ice_parser_list dist_parser_list; bool init_link_up; + uint64_t old_rx_bytes; + uint64_t old_tx_bytes; }; #define ICE_MAX_QUEUE_NUM 2048