[v2,04/20] common/mlx5: add mlx5 regex command structs
diff mbox series

Message ID 1594587541-110442-5-git-send-email-orika@mellanox.com
State Superseded
Delegated to: Thomas Monjalon
Headers show
Series
  • add Mellanox RegEx PMD
Related show

Checks

Context Check Description
ci/Intel-compilation fail apply issues
ci/checkpatch success coding style OK

Commit Message

Ori Kam July 12, 2020, 8:58 p.m. UTC
From: Yuval Avnery <yuvalav@mellanox.com>

Add regex commands structs to support regex.

Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>

---
 drivers/common/mlx5/mlx5_prm.h | 89 +++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 88 insertions(+), 1 deletion(-)

Comments

Thomas Monjalon July 15, 2020, 5:24 p.m. UTC | #1
12/07/2020 22:58, Ori Kam:
> From: Yuval Avnery <yuvalav@mellanox.com>
> 
> Add regex commands structs to support regex.

Addind data stuctures without any use of it is meaningless.
We can probably squash a lot of commits.

> Signed-off-by: Yuval Avnery <yuvalav@mellanox.com>
> Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> 
> ---
> --- a/drivers/common/mlx5/mlx5_prm.h
> +++ b/drivers/common/mlx5/mlx5_prm.h
> @@ -795,7 +795,7 @@ enum {
>  	MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
>  	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
>  	MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
> -	MLX5_CMD_SET_REGEX_PARAM = 0xb04,
> +	MLX5_CMD_SET_REGEX_PARAMS = 0xb04,

Should be part of previous patch.

>  	MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
>  	MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
>  	MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
> @@ -2526,6 +2526,93 @@ struct mlx5_ifc_query_qp_in_bits {
>  	u8 reserved_at_60[0x20];
>  };
>  
> +struct regexp_params_field_select_bits {
> +	u8 reserved_at_0[0x1e];
> +	u8 stop_engine[0x1];
> +	u8 db_umem_id[0x1];
> +};
> +
> +struct mlx5_ifc_regexp_params_bits {
> +	u8 reserved_at_0[0x1f];
> +	u8 stop_engine[0x1];
> +	u8 db_umem_id[0x20];
> +	u8 db_umem_offset[0x40];
> +	u8 reserved_at_80[0x100];
> +};
> +
> +struct mlx5_ifc_set_regexp_params_in_bits {
> +	u8 opcode[0x10];
> +	u8 uid[0x10];
> +	u8 reserved_at_20[0x10];
> +	u8 op_mod[0x10];
> +	u8 reserved_at_40[0x18];
> +	u8 engine_id[0x8];
> +	struct regexp_params_field_select_bits field_select;
> +	struct mlx5_ifc_regexp_params_bits regexp_params;
> +};
> +
> +struct mlx5_ifc_set_regexp_params_out_bits {
> +	u8 status[0x8];
> +	u8 reserved_at_8[0x18];
> +	u8 syndrome[0x20];
> +	u8 reserved_at_18[0x40];
> +};
> +
> +struct mlx5_ifc_query_regexp_params_in_bits {
> +	u8 opcode[0x10];
> +	u8 uid[0x10];
> +	u8 reserved_at_20[0x10];
> +	u8 op_mod[0x10];
> +	u8 reserved_at_40[0x18];
> +	u8 engine_id[0x8];
> +	u8 reserved[0x20];
> +};
> +
> +struct mlx5_ifc_query_regexp_params_out_bits {
> +	u8 status[0x8];
> +	u8 reserved_at_8[0x18];
> +	u8 syndrome[0x20];
> +	u8 reserved[0x40];
> +	struct mlx5_ifc_regexp_params_bits regexp_params;
> +};
> +
> +struct mlx5_ifc_set_regexp_register_in_bits {
> +	u8 opcode[0x10];
> +	u8 uid[0x10];
> +	u8 reserved_at_20[0x10];
> +	u8 op_mod[0x10];
> +	u8 reserved_at_40[0x18];
> +	u8 engine_id[0x8];
> +	u8 register_address[0x20];
> +	u8 register_data[0x20];
> +	u8 reserved[0x40];
> +};
> +
> +struct mlx5_ifc_set_regexp_register_out_bits {
> +	u8 status[0x8];
> +	u8 reserved_at_8[0x18];
> +	u8 syndrome[0x20];
> +	u8 reserved[0x40];
> +};
> +
> +struct mlx5_ifc_query_regexp_register_in_bits {
> +	u8 opcode[0x10];
> +	u8 uid[0x10];
> +	u8 reserved_at_20[0x10];
> +	u8 op_mod[0x10];
> +	u8 reserved_at_40[0x18];
> +	u8 engine_id[0x8];
> +	u8 register_address[0x20];
> +};
> +
> +struct mlx5_ifc_query_regexp_register_out_bits {
> +	u8 status[0x8];
> +	u8 reserved_at_8[0x18];
> +	u8 syndrome[0x20];
> +	u8 reserved[0x20];
> +	u8 register_data[0x20];
> +};

Patch
diff mbox series

diff --git a/drivers/common/mlx5/mlx5_prm.h b/drivers/common/mlx5/mlx5_prm.h
index c2b9a20..ede7810 100644
--- a/drivers/common/mlx5/mlx5_prm.h
+++ b/drivers/common/mlx5/mlx5_prm.h
@@ -795,7 +795,7 @@  enum {
 	MLX5_CMD_OP_CREATE_GENERAL_OBJECT = 0xa00,
 	MLX5_CMD_OP_MODIFY_GENERAL_OBJECT = 0xa01,
 	MLX5_CMD_OP_QUERY_GENERAL_OBJECT = 0xa02,
-	MLX5_CMD_SET_REGEX_PARAM = 0xb04,
+	MLX5_CMD_SET_REGEX_PARAMS = 0xb04,
 	MLX5_CMD_QUERY_REGEX_PARAMS = 0xb05,
 	MLX5_CMD_SET_REGEX_REGISTERS = 0xb06,
 	MLX5_CMD_QUERY_REGEX_REGISTERS = 0xb07,
@@ -2526,6 +2526,93 @@  struct mlx5_ifc_query_qp_in_bits {
 	u8 reserved_at_60[0x20];
 };
 
+struct regexp_params_field_select_bits {
+	u8 reserved_at_0[0x1e];
+	u8 stop_engine[0x1];
+	u8 db_umem_id[0x1];
+};
+
+struct mlx5_ifc_regexp_params_bits {
+	u8 reserved_at_0[0x1f];
+	u8 stop_engine[0x1];
+	u8 db_umem_id[0x20];
+	u8 db_umem_offset[0x40];
+	u8 reserved_at_80[0x100];
+};
+
+struct mlx5_ifc_set_regexp_params_in_bits {
+	u8 opcode[0x10];
+	u8 uid[0x10];
+	u8 reserved_at_20[0x10];
+	u8 op_mod[0x10];
+	u8 reserved_at_40[0x18];
+	u8 engine_id[0x8];
+	struct regexp_params_field_select_bits field_select;
+	struct mlx5_ifc_regexp_params_bits regexp_params;
+};
+
+struct mlx5_ifc_set_regexp_params_out_bits {
+	u8 status[0x8];
+	u8 reserved_at_8[0x18];
+	u8 syndrome[0x20];
+	u8 reserved_at_18[0x40];
+};
+
+struct mlx5_ifc_query_regexp_params_in_bits {
+	u8 opcode[0x10];
+	u8 uid[0x10];
+	u8 reserved_at_20[0x10];
+	u8 op_mod[0x10];
+	u8 reserved_at_40[0x18];
+	u8 engine_id[0x8];
+	u8 reserved[0x20];
+};
+
+struct mlx5_ifc_query_regexp_params_out_bits {
+	u8 status[0x8];
+	u8 reserved_at_8[0x18];
+	u8 syndrome[0x20];
+	u8 reserved[0x40];
+	struct mlx5_ifc_regexp_params_bits regexp_params;
+};
+
+struct mlx5_ifc_set_regexp_register_in_bits {
+	u8 opcode[0x10];
+	u8 uid[0x10];
+	u8 reserved_at_20[0x10];
+	u8 op_mod[0x10];
+	u8 reserved_at_40[0x18];
+	u8 engine_id[0x8];
+	u8 register_address[0x20];
+	u8 register_data[0x20];
+	u8 reserved[0x40];
+};
+
+struct mlx5_ifc_set_regexp_register_out_bits {
+	u8 status[0x8];
+	u8 reserved_at_8[0x18];
+	u8 syndrome[0x20];
+	u8 reserved[0x40];
+};
+
+struct mlx5_ifc_query_regexp_register_in_bits {
+	u8 opcode[0x10];
+	u8 uid[0x10];
+	u8 reserved_at_20[0x10];
+	u8 op_mod[0x10];
+	u8 reserved_at_40[0x18];
+	u8 engine_id[0x8];
+	u8 register_address[0x20];
+};
+
+struct mlx5_ifc_query_regexp_register_out_bits {
+	u8 status[0x8];
+	u8 reserved_at_8[0x18];
+	u8 syndrome[0x20];
+	u8 reserved[0x20];
+	u8 register_data[0x20];
+};
+
 /* CQE format mask. */
 #define MLX5E_CQE_FORMAT_MASK 0xc