From patchwork Fri Jul 10 09:48:44 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Slava Ovsiienko X-Patchwork-Id: 73722 X-Patchwork-Delegate: rasland@nvidia.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 19BE3A052A; Fri, 10 Jul 2020 11:50:25 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id B83791DEAB; Fri, 10 Jul 2020 11:49:13 +0200 (CEST) Received: from mellanox.co.il (mail-il-dmz.mellanox.com [193.47.165.129]) by dpdk.org (Postfix) with ESMTP id AE0291DDBF for ; Fri, 10 Jul 2020 11:49:05 +0200 (CEST) Received: from Internal Mail-Server by MTLPINE1 (envelope-from viacheslavo@mellanox.com) with SMTP; 10 Jul 2020 12:49:00 +0300 Received: from pegasus12.mtr.labs.mlnx (pegasus12.mtr.labs.mlnx [10.210.17.40]) by labmailer.mlnx (8.13.8/8.13.8) with ESMTP id 06A9n0JK012287; Fri, 10 Jul 2020 12:49:00 +0300 Received: from pegasus12.mtr.labs.mlnx (localhost [127.0.0.1]) by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7) with ESMTP id 06A9n0u6024763; Fri, 10 Jul 2020 09:49:00 GMT Received: (from viacheslavo@localhost) by pegasus12.mtr.labs.mlnx (8.14.7/8.14.7/Submit) id 06A9n02H024762; Fri, 10 Jul 2020 09:49:00 GMT X-Authentication-Warning: pegasus12.mtr.labs.mlnx: viacheslavo set sender to viacheslavo@mellanox.com using -f From: Viacheslav Ovsiienko To: dev@dpdk.org Cc: matan@mellanox.com, rasland@mellanox.com, thomas@monjalon.net, ferruh.yigit@intel.com Date: Fri, 10 Jul 2020 09:48:44 +0000 Message-Id: <1594374530-24659-10-git-send-email-viacheslavo@mellanox.com> X-Mailer: git-send-email 1.8.3.1 In-Reply-To: <1594374530-24659-1-git-send-email-viacheslavo@mellanox.com> References: <1594374530-24659-1-git-send-email-viacheslavo@mellanox.com> Subject: [dpdk-dev] [PATCH v1 10/16] net/mlx5: prepare Tx queue structures to support timestamp X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" The fields to support send scheduling on dynamic timestamp field are introduced and initialized on device start. Signed-off-by: Viacheslav Ovsiienko --- drivers/net/mlx5/mlx5_rxtx.h | 4 ++++ drivers/net/mlx5/mlx5_trigger.c | 2 ++ drivers/net/mlx5/mlx5_txq.c | 32 ++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/drivers/net/mlx5/mlx5_rxtx.h b/drivers/net/mlx5/mlx5_rxtx.h index 8a8d2b5..974a847 100644 --- a/drivers/net/mlx5/mlx5_rxtx.h +++ b/drivers/net/mlx5/mlx5_rxtx.h @@ -313,6 +313,9 @@ struct mlx5_txq_data { volatile uint32_t *cq_db; /* Completion queue doorbell. */ uint16_t port_id; /* Port ID of device. */ uint16_t idx; /* Queue index. */ + uint64_t ts_mask; /* Timestamp flag dynamic mask. */ + int32_t ts_offset; /* Timestamp field dynamic offset. */ + struct mlx5_dev_ctx_shared *sh; /* Shared context. */ struct mlx5_txq_stats stats; /* TX queue counters. */ #ifndef RTE_ARCH_64 rte_spinlock_t *uar_lock; @@ -468,6 +471,7 @@ struct mlx5_txq_ctrl *mlx5_txq_hairpin_new void txq_alloc_elts(struct mlx5_txq_ctrl *txq_ctrl); void txq_free_elts(struct mlx5_txq_ctrl *txq_ctrl); uint64_t mlx5_get_tx_port_offloads(struct rte_eth_dev *dev); +void mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev); /* mlx5_rxtx.c */ diff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c index 449dd95..b713974 100644 --- a/drivers/net/mlx5/mlx5_trigger.c +++ b/drivers/net/mlx5/mlx5_trigger.c @@ -331,6 +331,8 @@ } /* Set a mask and offset of dynamic metadata flows into Rx queues*/ mlx5_flow_rxq_dynf_metadata_set(dev); + /* Set a mask and offset of scheduling on timestamp into Tx queues*/ + mlx5_txq_dynf_timestamp_set(dev); /* * In non-cached mode, it only needs to start the default mreg copy * action and no flow created by application exists anymore. diff --git a/drivers/net/mlx5/mlx5_txq.c b/drivers/net/mlx5/mlx5_txq.c index a6f7e1c..d3b2863 100644 --- a/drivers/net/mlx5/mlx5_txq.c +++ b/drivers/net/mlx5/mlx5_txq.c @@ -1778,3 +1778,35 @@ struct mlx5_txq_ctrl * } return ret; } + +/** + * Set the Tx queue dynamic timestamp (mask and offset) + * + * @param[in] dev + * Pointer to the Ethernet device structure. + */ +void +mlx5_txq_dynf_timestamp_set(struct rte_eth_dev *dev) +{ + struct mlx5_priv *priv = dev->data->dev_private; + struct mlx5_dev_ctx_shared *sh = priv->sh; + struct mlx5_txq_data *data; + int off, nbit; + unsigned int i; + uint64_t mask = 0; + + nbit = rte_mbuf_dynflag_lookup + (RTE_MBUF_DYNFLAG_TX_TIMESTAMP_NAME, NULL); + off = rte_mbuf_dynfield_lookup + (RTE_MBUF_DYNFIELD_TIMESTAMP_NAME, NULL); + if (nbit > 0 && off >= 0 && sh->txpp.refcnt) + mask = 1ULL << nbit; + for (i = 0; i != priv->txqs_n; ++i) { + data = (*priv->txqs)[i]; + if (!data) + continue; + data->sh = sh; + data->ts_mask = mask; + data->ts_offset = off; + } +}