From patchwork Thu Jul 9 16:45:33 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Zhang, Tianfei" X-Patchwork-Id: 73622 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 5455AA0526; Thu, 9 Jul 2020 10:56:39 +0200 (CEST) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 293FC1E494; Thu, 9 Jul 2020 10:56:39 +0200 (CEST) Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by dpdk.org (Postfix) with ESMTP id A56161DFEF; Thu, 9 Jul 2020 10:56:37 +0200 (CEST) IronPort-SDR: 2IUHhbZRCnGK6US+Smwkt7Lc8/SEvmwzmd2XxR06g8bZZW5Uyy/60cDiFzanC7oyRybbuwD20Z Nx8W2ebOdamg== X-IronPort-AV: E=McAfee;i="6000,8403,9676"; a="147954723" X-IronPort-AV: E=Sophos;i="5.75,331,1589266800"; d="scan'208";a="147954723" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2020 01:56:36 -0700 IronPort-SDR: 9/dO8XQILsKK8DSWDG7gDlNktt+x55g6JdlFXpdH7MhEAxIYiVnQ0n30U4EdE13MNfcfGLiFn3 1hjMzs0o404w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,331,1589266800"; d="scan'208";a="314898816" Received: from figo-optiplex-9020.sh.intel.com ([10.238.169.50]) by orsmga008.jf.intel.com with ESMTP; 09 Jul 2020 01:56:35 -0700 From: Tianfei zhang To: dev@dpdk.org, rosen.xu@intel.com Cc: Tianfei Zhang , stable@dpdk.org Date: Fri, 10 Jul 2020 00:45:33 +0800 Message-Id: <20200709164533.13150-1-tianfei.zhang@intel.com> X-Mailer: git-send-email 2.17.1 Subject: [dpdk-dev] [PATCH v2 2/2] raw/ifpga/base: fix NIOS SPI initial X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Tianfei Zhang Add fecmode setting on NIOS SPI primary initialization. this SPI is shared by NIOS core inside FPGA, NIOS will use this SPI primary to do some one time initialization after power up, and then release the control to DPDK. Fix the timeout initialization for polling the NIOS_INIT_DONE. Fixes: bc44402f ("raw/ifpga/base: configure FEC mode") Cc: stable@dpdk.org Signed-off-by: Tianfei Zhang --- drivers/raw/ifpga/base/ifpga_fme.c | 27 ++++++++++++++++++++------- drivers/raw/ifpga/base/opae_spi.h | 1 + 2 files changed, 21 insertions(+), 7 deletions(-) diff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c index c31a94cf8..9057087b5 100644 --- a/drivers/raw/ifpga/base/ifpga_fme.c +++ b/drivers/raw/ifpga/base/ifpga_fme.c @@ -979,28 +979,32 @@ struct ifpga_feature_ops fme_spi_master_ops = { static int nios_spi_wait_init_done(struct altera_spi_device *dev) { u32 val = 0; - unsigned long timeout = msecs_to_timer_cycles(10000); + unsigned long timeout = rte_get_timer_cycles() + + msecs_to_timer_cycles(10000); unsigned long ticks; int major_version; + int fecmode = FEC_MODE_NO; if (spi_reg_read(dev, NIOS_VERSION, &val)) return -EIO; - major_version = (val >> NIOS_VERSION_MAJOR_SHIFT) & - NIOS_VERSION_MAJOR; - dev_debug(dev, "A10 NIOS FW version %d\n", major_version); + major_version = + (val & NIOS_VERSION_MAJOR) >> NIOS_VERSION_MAJOR_SHIFT; + dev_info(dev, "A10 NIOS FW version %d\n", major_version); if (major_version >= 3) { /* read NIOS_INIT to check if PKVL INIT done or not */ if (spi_reg_read(dev, NIOS_INIT, &val)) return -EIO; + dev_debug(dev, "read NIOS_INIT: 0x%x\n", val); + /* check if PKVLs are initialized already */ if (val & NIOS_INIT_DONE || val & NIOS_INIT_START) goto nios_init_done; /* start to config the default FEC mode */ - val = NIOS_INIT_START; + val = fecmode | NIOS_INIT_START; if (spi_reg_write(dev, NIOS_INIT, val)) return -EIO; @@ -1010,14 +1014,23 @@ static int nios_spi_wait_init_done(struct altera_spi_device *dev) do { if (spi_reg_read(dev, NIOS_INIT, &val)) return -EIO; - if (val) + if (val & NIOS_INIT_DONE) break; ticks = rte_get_timer_cycles(); if (time_after(ticks, timeout)) return -ETIMEDOUT; msleep(100); - } while (!val); + } while (1); + + /* get the fecmode */ + if (spi_reg_read(dev, NIOS_INIT, &val)) + return -EIO; + dev_debug(dev, "read NIOS_INIT: 0x%x\n", val); + fecmode = (val & REQ_FEC_MODE) >> REQ_FEC_MODE_SHIFT; + dev_info(dev, "fecmode: 0x%x, %s\n", fecmode, + (fecmode == FEC_MODE_KR) ? "kr" : + ((fecmode == FEC_MODE_RS) ? "rs" : "no")); return 0; } diff --git a/drivers/raw/ifpga/base/opae_spi.h b/drivers/raw/ifpga/base/opae_spi.h index d20a4c3ed..73a227673 100644 --- a/drivers/raw/ifpga/base/opae_spi.h +++ b/drivers/raw/ifpga/base/opae_spi.h @@ -153,6 +153,7 @@ int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val); #define NIOS_INIT 0x1000 #define REQ_FEC_MODE GENMASK(23, 8) +#define REQ_FEC_MODE_SHIFT 8 #define FEC_MODE_NO 0x0 #define FEC_MODE_KR 0x5555 #define FEC_MODE_RS 0xaaaa