[v2,2/2] raw/ifpga/base: fix NIOS SPI initial
diff mbox series

Message ID 20200709164533.13150-1-tianfei.zhang@intel.com
State Superseded
Delegated to: Thomas Monjalon
Headers show
Series
  • [v2,1/2] raw/ifpga/base: fix spi transaction issue
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Context Check Description
ci/Intel-compilation success Compilation OK
ci/travis-robot success Travis build: passed
ci/checkpatch warning coding style issues

Commit Message

Tianfei zhang July 9, 2020, 4:45 p.m. UTC
From: Tianfei Zhang <tianfei.zhang@intel.com>

Add fecmode setting on NIOS SPI primary initialization.
this SPI is shared by NIOS core inside FPGA, NIOS will
use this SPI primary to do some one time initialization
after power up, and then release the control to DPDK.

Fix the timeout initialization for polling the
NIOS_INIT_DONE.

Fixes: bc44402f ("raw/ifpga/base: configure FEC mode")
Cc: stable@dpdk.org

Signed-off-by: Tianfei Zhang <tianfei.zhang@intel.com>
---
 drivers/raw/ifpga/base/ifpga_fme.c | 27 ++++++++++++++++++++-------
 drivers/raw/ifpga/base/opae_spi.h  |  1 +
 2 files changed, 21 insertions(+), 7 deletions(-)

Patch
diff mbox series

diff --git a/drivers/raw/ifpga/base/ifpga_fme.c b/drivers/raw/ifpga/base/ifpga_fme.c
index c31a94cf8..9057087b5 100644
--- a/drivers/raw/ifpga/base/ifpga_fme.c
+++ b/drivers/raw/ifpga/base/ifpga_fme.c
@@ -979,28 +979,32 @@  struct ifpga_feature_ops fme_spi_master_ops = {
 static int nios_spi_wait_init_done(struct altera_spi_device *dev)
 {
 	u32 val = 0;
-	unsigned long timeout = msecs_to_timer_cycles(10000);
+	unsigned long timeout = rte_get_timer_cycles() +
+			msecs_to_timer_cycles(10000);
 	unsigned long ticks;
 	int major_version;
+	int fecmode = FEC_MODE_NO;
 
 	if (spi_reg_read(dev, NIOS_VERSION, &val))
 		return -EIO;
 
-	major_version = (val >> NIOS_VERSION_MAJOR_SHIFT) &
-		NIOS_VERSION_MAJOR;
-	dev_debug(dev, "A10 NIOS FW version %d\n", major_version);
+	major_version =
+		(val & NIOS_VERSION_MAJOR) >> NIOS_VERSION_MAJOR_SHIFT;
+	dev_info(dev, "A10 NIOS FW version %d\n", major_version);
 
 	if (major_version >= 3) {
 		/* read NIOS_INIT to check if PKVL INIT done or not */
 		if (spi_reg_read(dev, NIOS_INIT, &val))
 			return -EIO;
 
+		dev_debug(dev, "read NIOS_INIT: 0x%x\n", val);
+
 		/* check if PKVLs are initialized already */
 		if (val & NIOS_INIT_DONE || val & NIOS_INIT_START)
 			goto nios_init_done;
 
 		/* start to config the default FEC mode */
-		val = NIOS_INIT_START;
+		val = fecmode | NIOS_INIT_START;
 
 		if (spi_reg_write(dev, NIOS_INIT, val))
 			return -EIO;
@@ -1010,14 +1014,23 @@  static int nios_spi_wait_init_done(struct altera_spi_device *dev)
 	do {
 		if (spi_reg_read(dev, NIOS_INIT, &val))
 			return -EIO;
-		if (val)
+		if (val & NIOS_INIT_DONE)
 			break;
 
 		ticks = rte_get_timer_cycles();
 		if (time_after(ticks, timeout))
 			return -ETIMEDOUT;
 		msleep(100);
-	} while (!val);
+	} while (1);
+
+	/* get the fecmode */
+	if (spi_reg_read(dev, NIOS_INIT, &val))
+		return -EIO;
+	dev_debug(dev, "read NIOS_INIT: 0x%x\n", val);
+	fecmode = (val & REQ_FEC_MODE) >> REQ_FEC_MODE_SHIFT;
+	dev_info(dev, "fecmode: 0x%x, %s\n", fecmode,
+			(fecmode == FEC_MODE_KR) ? "kr" :
+			((fecmode == FEC_MODE_RS) ? "rs" : "no"));
 
 	return 0;
 }
diff --git a/drivers/raw/ifpga/base/opae_spi.h b/drivers/raw/ifpga/base/opae_spi.h
index d20a4c3ed..73a227673 100644
--- a/drivers/raw/ifpga/base/opae_spi.h
+++ b/drivers/raw/ifpga/base/opae_spi.h
@@ -153,6 +153,7 @@  int spi_reg_read(struct altera_spi_device *dev, u32 reg, u32 *val);
 
 #define NIOS_INIT		0x1000
 #define REQ_FEC_MODE		GENMASK(23, 8)
+#define REQ_FEC_MODE_SHIFT      8
 #define FEC_MODE_NO		0x0
 #define FEC_MODE_KR		0x5555
 #define FEC_MODE_RS		0xaaaa