[v3,01/19] net/ixgbe/base: fix host interface shadow RAM read
diff mbox series

Message ID 20200709080046.65879-2-guinanx.sun@intel.com
State Accepted, archived
Delegated to: Qi Zhang
Headers show
Series
  • update ixgbe base code
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Context Check Description
ci/iol-intel-Performance success Performance Testing PASS
ci/iol-testing success Testing PASS
ci/Intel-compilation success Compilation OK
ci/iol-broadcom-Performance success Performance Testing PASS
ci/checkpatch success coding style OK

Commit Message

Guinan Sun July 9, 2020, 8 a.m. UTC
Host interface Shadow RAM Read (0x31) command response
buffer length should be stored in two bytes, instead of one byte.
This patch fixes it.

Fixes: e6102361b1d4 ("net/ixgbe/base: use 2 bytes for flash read command")
Cc: stable@dpdk.org

Signed-off-by: Mateusz Kowalski <mateusz.kowalski@intel.com>
Signed-off-by: Guinan Sun <guinanx.sun@intel.com>
Reviewed-by: Wei Zhao <wei.zhao1@intel.com>
---
 drivers/net/ixgbe/base/ixgbe_common.c |  3 ++-
 drivers/net/ixgbe/base/ixgbe_type.h   | 12 ++++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

Patch
diff mbox series

diff --git a/drivers/net/ixgbe/base/ixgbe_common.c b/drivers/net/ixgbe/base/ixgbe_common.c
index 4eb98dc19..5889410f9 100644
--- a/drivers/net/ixgbe/base/ixgbe_common.c
+++ b/drivers/net/ixgbe/base/ixgbe_common.c
@@ -4600,7 +4600,8 @@  s32 ixgbe_host_interface_command(struct ixgbe_hw *hw, u32 *buffer,
 	 * Read Flash command requires reading buffer length from
 	 * two byes instead of one byte
 	 */
-	if (resp->cmd == 0x30) {
+	if (resp->cmd == IXGBE_HOST_INTERFACE_FLASH_READ_CMD ||
+	    resp->cmd == IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD) {
 		for (; bi < dword_len + 2; bi++) {
 			buffer[bi] = IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG,
 							  bi);
diff --git a/drivers/net/ixgbe/base/ixgbe_type.h b/drivers/net/ixgbe/base/ixgbe_type.h
index 15e937010..bc927a34e 100644
--- a/drivers/net/ixgbe/base/ixgbe_type.h
+++ b/drivers/net/ixgbe/base/ixgbe_type.h
@@ -4364,4 +4364,16 @@  struct ixgbe_hw {
 #define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD	\
 				(0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT)
 
+/* Code Command (Flash I/F Interface) */
+#define IXGBE_HOST_INTERFACE_FLASH_READ_CMD			0x30
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_READ_CMD		0x31
+#define IXGBE_HOST_INTERFACE_FLASH_WRITE_CMD			0x32
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_WRITE_CMD		0x33
+#define IXGBE_HOST_INTERFACE_FLASH_MODULE_UPDATE_CMD		0x34
+#define IXGBE_HOST_INTERFACE_FLASH_BLOCK_EREASE_CMD		0x35
+#define IXGBE_HOST_INTERFACE_SHADOW_RAM_DUMP_CMD		0x36
+#define IXGBE_HOST_INTERFACE_FLASH_INFO_CMD			0x37
+#define IXGBE_HOST_INTERFACE_APPLY_UPDATE_CMD			0x38
+#define IXGBE_HOST_INTERFACE_MASK_CMD				0x000000FF
+
 #endif /* _IXGBE_TYPE_H_ */