[09/20] common/mlx5: add write and read RXP registers
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Commit Message
This commits add the write and read RXP registers functionality.
Signed-off-by: Ori Kam <orika@mellanox.com>
---
drivers/common/mlx5/mlx5_devx_cmds.c | 78 +++++++++++++++++++++++++
drivers/common/mlx5/mlx5_devx_cmds.h | 10 ++++
drivers/common/mlx5/rte_common_mlx5_version.map | 2 +
3 files changed, 90 insertions(+)
Comments
Acked-by: Viacheslav Ovsiienko <viacheslavo@mellanox.com>
> -----Original Message-----
> From: Ori Kam <orika@mellanox.com>
> Sent: Sunday, July 5, 2020 12:24
> To: jerinj@marvell.com; xiang.w.wang@intel.com; Matan Azrad
> <matan@mellanox.com>; Slava Ovsiienko <viacheslavo@mellanox.com>;
> Shahaf Shuler <shahafs@mellanox.com>; Ray Kinsella <mdr@ashroe.eu>;
> Neil Horman <nhorman@tuxdriver.com>
> Cc: guyk@marvell.com; dev@dpdk.org; pbhagavatula@marvell.com;
> hemant.agrawal@nxp.com; Opher Reviv <opher@mellanox.com>; Alex
> Rosenbaum <alexr@mellanox.com>; dovrat@marvell.com;
> pkapoor@marvell.com; nipun.gupta@nxp.com;
> bruce.richardson@intel.com; yang.a.hong@intel.com;
> harry.chang@intel.com; gu.jian1@zte.com.cn;
> shanjiangh@chinatelecom.cn; zhangy.yun@chinatelecom.cn;
> lixingfu@huachentel.com; wushuai@inspur.com; yuyingxia@yxlink.com;
> fanchenggang@sunyainfo.com; davidfgao@tencent.com;
> liuzhong1@chinaunicom.cn; zhaoyong11@huawei.com; oc@yunify.com;
> jim@netgate.com; hongjun.ni@intel.com; deri@ntop.org;
> fc@napatech.com; arthur.su@lionic.com; Thomas Monjalon
> <thomas@monjalon.net>; Ori Kam <orika@mellanox.com>; Raslan
> Darawsheh <rasland@mellanox.com>
> Subject: [PATCH 09/20] common/mlx5: add write and read RXP registers
>
> This commits add the write and read RXP registers functionality.
>
> Signed-off-by: Ori Kam <orika@mellanox.com>
> ---
> drivers/common/mlx5/mlx5_devx_cmds.c | 78
> +++++++++++++++++++++++++
> drivers/common/mlx5/mlx5_devx_cmds.h | 10 ++++
> drivers/common/mlx5/rte_common_mlx5_version.map | 2 +
> 3 files changed, 90 insertions(+)
>
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
> b/drivers/common/mlx5/mlx5_devx_cmds.c
> index f8760e6..4fad7cd 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.c
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.c
> @@ -1720,3 +1720,81 @@ struct mlx5_devx_obj *
> return 0;
> }
>
> +/**
> + * Write to RXP registers.
> + *
> + * @param ctx
> + * ibv device handle
> + * @param engine_id
> + * Chooses on which engine the register will be written..
> + * @param addr
> + * Register address.
> + * @param data
> + * Data to be written to the register.
> + *
> + * @return
> + * 0 on success, a negative errno value otherwise and rte_errno is set.
> + */
> +int
> +mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
> + uint32_t addr, uint32_t data) {
> + uint32_t out[DEVX_ST_SZ_DW(set_regexp_register_out)] = {};
> + uint32_t in[DEVX_ST_SZ_DW(set_regexp_register_in)] = {};
> + int ret;
> +
> + DEVX_SET(set_regexp_register_in, in, opcode,
> + MLX5_CMD_SET_REGEX_REGISTERS);
> + DEVX_SET(set_regexp_register_in, in, engine_id, engine_id);
> + DEVX_SET(set_regexp_register_in, in, register_address, addr);
> + DEVX_SET(set_regexp_register_in, in, register_data, data);
> +
> + ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
> + sizeof(out));
> + if (ret) {
> + DRV_LOG(ERR, "Set regexp register failed %d", ret);
> + rte_errno = errno;
> + return -errno;
> + }
> + return 0;
> +}
> +
> +
> +/**
> + * Read from RXP registers
> + *
> + * @param ctx
> + * ibv device handle
> + * @param engine_id
> + * Chooses from which engine to read.
> + * @param addr
> + * Register address.
> + * @param data
> + * Output containing the pointer to the data..
> + *
> + * @return
> + * 0 on success, a negative errno value otherwise and rte_errno is set.
> + */
> +int
> +mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
> + uint32_t addr, uint32_t *data) {
> + uint32_t out[DEVX_ST_SZ_DW(query_regexp_register_out)] = {};
> + uint32_t in[DEVX_ST_SZ_DW(query_regexp_register_in)] = {};
> + int ret;
> +
> + DEVX_SET(query_regexp_register_in, in, opcode,
> + MLX5_CMD_QUERY_REGEX_REGISTERS);
> + DEVX_SET(query_regexp_register_in, in, engine_id, engine_id);
> + DEVX_SET(query_regexp_register_in, in, register_address, addr);
> +
> + ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
> + sizeof(out));
> + if (ret) {
> + DRV_LOG(ERR, "Query regexp register failed %d", ret);
> + rte_errno = errno;
> + return -errno;
> + }
> + *data = DEVX_GET(query_regexp_register_out, out, register_data);
> + return 0;
> +}
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h
> b/drivers/common/mlx5/mlx5_devx_cmds.h
> index 655e31f..a2a9045 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.h
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.h
> @@ -374,6 +374,10 @@ int mlx5_devx_cmd_modify_qp_state(struct
> mlx5_devx_obj *qp, __rte_internal int mlx5_devx_cmd_modify_rqt(struct
> mlx5_devx_obj *rqt,
> struct mlx5_devx_rqt_attr *rqt_attr);
> +int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
> + uint32_t addr, uint32_t data);
> +int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
> + uint32_t addr, uint32_t *data);
>
> /**
> * Create virtio queue counters object DevX API.
> @@ -408,4 +412,10 @@ int mlx5_devx_cmd_query_virtio_q_counters(struct
> mlx5_devx_obj *couners_obj, __rte_internal int
> mlx5_devx_regex_database_program(void *ctx, uint8_t engine,
> uint32_t umem_id, uint64_t
> umem_offset);
> +__rte_internal
> +int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
> + uint32_t addr, uint32_t *data);
> +__rte_internal
> +int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
> + uint32_t addr, uint32_t data);
> #endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */
> diff --git a/drivers/common/mlx5/rte_common_mlx5_version.map
> b/drivers/common/mlx5/rte_common_mlx5_version.map
> index 6054d39..138719d 100644
> --- a/drivers/common/mlx5/rte_common_mlx5_version.map
> +++ b/drivers/common/mlx5/rte_common_mlx5_version.map
> @@ -38,6 +38,8 @@ INTERNAL {
> mlx5_devx_regex_database_program;
> mlx5_devx_regex_database_resume;
> mlx5_devx_regex_database_stop;
> + mlx5_devx_regex_register_read;
> + mlx5_devx_regex_register_write;
>
> mlx5_get_ifname_sysfs;
> mlx5_get_dbr;
> --
> 1.8.3.1
@@ -1720,3 +1720,81 @@ struct mlx5_devx_obj *
return 0;
}
+/**
+ * Write to RXP registers.
+ *
+ * @param ctx
+ * ibv device handle
+ * @param engine_id
+ * Chooses on which engine the register will be written..
+ * @param addr
+ * Register address.
+ * @param data
+ * Data to be written to the register.
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t data)
+{
+ uint32_t out[DEVX_ST_SZ_DW(set_regexp_register_out)] = {};
+ uint32_t in[DEVX_ST_SZ_DW(set_regexp_register_in)] = {};
+ int ret;
+
+ DEVX_SET(set_regexp_register_in, in, opcode,
+ MLX5_CMD_SET_REGEX_REGISTERS);
+ DEVX_SET(set_regexp_register_in, in, engine_id, engine_id);
+ DEVX_SET(set_regexp_register_in, in, register_address, addr);
+ DEVX_SET(set_regexp_register_in, in, register_data, data);
+
+ ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
+ sizeof(out));
+ if (ret) {
+ DRV_LOG(ERR, "Set regexp register failed %d", ret);
+ rte_errno = errno;
+ return -errno;
+ }
+ return 0;
+}
+
+
+/**
+ * Read from RXP registers
+ *
+ * @param ctx
+ * ibv device handle
+ * @param engine_id
+ * Chooses from which engine to read.
+ * @param addr
+ * Register address.
+ * @param data
+ * Output containing the pointer to the data..
+ *
+ * @return
+ * 0 on success, a negative errno value otherwise and rte_errno is set.
+ */
+int
+mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t *data)
+{
+ uint32_t out[DEVX_ST_SZ_DW(query_regexp_register_out)] = {};
+ uint32_t in[DEVX_ST_SZ_DW(query_regexp_register_in)] = {};
+ int ret;
+
+ DEVX_SET(query_regexp_register_in, in, opcode,
+ MLX5_CMD_QUERY_REGEX_REGISTERS);
+ DEVX_SET(query_regexp_register_in, in, engine_id, engine_id);
+ DEVX_SET(query_regexp_register_in, in, register_address, addr);
+
+ ret = mlx5_glue->devx_general_cmd(ctx, in, sizeof(in), out,
+ sizeof(out));
+ if (ret) {
+ DRV_LOG(ERR, "Query regexp register failed %d", ret);
+ rte_errno = errno;
+ return -errno;
+ }
+ *data = DEVX_GET(query_regexp_register_out, out, register_data);
+ return 0;
+}
@@ -374,6 +374,10 @@ int mlx5_devx_cmd_modify_qp_state(struct mlx5_devx_obj *qp,
__rte_internal
int mlx5_devx_cmd_modify_rqt(struct mlx5_devx_obj *rqt,
struct mlx5_devx_rqt_attr *rqt_attr);
+int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t data);
+int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t *data);
/**
* Create virtio queue counters object DevX API.
@@ -408,4 +412,10 @@ int mlx5_devx_cmd_query_virtio_q_counters(struct mlx5_devx_obj *couners_obj,
__rte_internal
int mlx5_devx_regex_database_program(void *ctx, uint8_t engine,
uint32_t umem_id, uint64_t umem_offset);
+__rte_internal
+int mlx5_devx_regex_register_read(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t *data);
+__rte_internal
+int mlx5_devx_regex_register_write(struct ibv_context *ctx, int engine_id,
+ uint32_t addr, uint32_t data);
#endif /* RTE_PMD_MLX5_DEVX_CMDS_H_ */
@@ -38,6 +38,8 @@ INTERNAL {
mlx5_devx_regex_database_program;
mlx5_devx_regex_database_resume;
mlx5_devx_regex_database_stop;
+ mlx5_devx_regex_register_read;
+ mlx5_devx_regex_register_write;
mlx5_get_ifname_sysfs;
mlx5_get_dbr;