From patchwork Wed Sep 30 09:16:07 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chilikin, Andrey" X-Patchwork-Id: 7296 X-Patchwork-Delegate: bruce.richardson@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [IPv6:::1]) by dpdk.org (Postfix) with ESMTP id 7F14C8DA1; Wed, 30 Sep 2015 11:16:15 +0200 (CEST) Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by dpdk.org (Postfix) with ESMTP id 22DB78D90 for ; Wed, 30 Sep 2015 11:16:12 +0200 (CEST) Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by fmsmga102.fm.intel.com with ESMTP; 30 Sep 2015 02:16:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.17,611,1437462000"; d="scan'208";a="816054665" Received: from irvmail001.ir.intel.com ([163.33.26.43]) by fmsmga002.fm.intel.com with ESMTP; 30 Sep 2015 02:16:11 -0700 Received: from sivswdev02.ir.intel.com (sivswdev02.ir.intel.com [10.237.217.46]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id t8U9GAgY007768; Wed, 30 Sep 2015 10:16:10 +0100 Received: from sivswdev02.ir.intel.com (localhost [127.0.0.1]) by sivswdev02.ir.intel.com with ESMTP id t8U9GAqL024914; Wed, 30 Sep 2015 10:16:10 +0100 Received: (from achiliki@localhost) by sivswdev02.ir.intel.com with id t8U9GA3i024910; Wed, 30 Sep 2015 10:16:10 +0100 From: Andrey Chilikin To: dev@dpdk.org Date: Wed, 30 Sep 2015 10:16:07 +0100 Message-Id: <1443604567-24875-1-git-send-email-andrey.chilikin@intel.com> X-Mailer: git-send-email 1.7.4.1 Subject: [dpdk-dev] [PATCH] i40e: fix for default flexible payload registers settings X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: patches and discussions about DPDK List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" This patch applies new default values to flexible payload configuration for flow director filter Signed-off-by: Andrey Chilikin --- drivers/net/i40e/i40e_ethdev.c | 6 +++--- drivers/net/i40e/i40e_fdir.c | 20 +++++++++++++++----- 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c index 2dd9fdc..0c3b532 100644 --- a/drivers/net/i40e/i40e_ethdev.c +++ b/drivers/net/i40e/i40e_ethdev.c @@ -370,9 +370,9 @@ static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw) I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030); I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B); I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B); - I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0); - I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3); - I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000A0); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000A3); + I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000A6); I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031); I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031); I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D); diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c index c9ce98f..8f27694 100644 --- a/drivers/net/i40e/i40e_fdir.c +++ b/drivers/net/i40e/i40e_fdir.c @@ -483,13 +483,14 @@ i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf) return -EINVAL; } /* check flexible payload setting configuration */ - if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) { + if (conf->nb_payloads > I40E_MAX_FLXPLD_LAYER) { PMD_DRV_LOG(ERR, "invalid number of payload setting."); return -EINVAL; } for (i = 0; i < conf->nb_payloads; i++) { flex_cfg = &conf->flex_set[i]; - if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) { + if (flex_cfg->type < RTE_ETH_L2_PAYLOAD || + flex_cfg->type > RTE_ETH_L4_PAYLOAD) { PMD_DRV_LOG(ERR, "invalid payload type."); return -EINVAL; } @@ -528,6 +529,10 @@ i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf) return 0; } +#ifndef I40E_GLQF_ORT +#define I40E_GLQF_ORT(_i) (0x00268900 + ((_i) * 4)) +#endif + /* * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload * @pf: board private structure @@ -539,7 +544,7 @@ i40e_set_flx_pld_cfg(struct i40e_pf *pf, { struct i40e_hw *hw = I40E_PF_TO_HW(pf); struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED]; - uint32_t flx_pit; + uint32_t ort, flx_pit; uint16_t num, min_next_off; /* in words */ uint8_t field_idx = 0; uint8_t layer_idx = 0; @@ -554,8 +559,9 @@ i40e_set_flx_pld_cfg(struct i40e_pf *pf, memset(flex_pit, 0, sizeof(flex_pit)); num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit); + num = RTE_MIN(num, RTE_DIM(flex_pit)); - for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) { + for (i = 0; i < num; i++) { field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i; /* record the info in fdir structure */ pf->fdir.flex_set[field_idx].src_offset = @@ -576,12 +582,16 @@ i40e_set_flx_pld_cfg(struct i40e_pf *pf, for (; i < I40E_MAX_FLXPLD_FIED; i++) { /* set the non-used register obeying register's constrain */ flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE, - NONUSE_FLX_PIT_DEST_OFF); + NONUSE_FLX_PIT_DEST_OFF - + I40E_FLX_OFFSET_IN_FIELD_VECTOR); I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i), flx_pit); min_next_off++; } + + ort = 0x80 | (num << 5) | layer_idx * I40E_MAX_FLXPLD_FIED; + I40E_WRITE_REG(hw, I40E_GLQF_ORT(layer_idx + 33), ort); } /*