[dpdk-dev] i40e: fix for default flexible payload registers settings

Message ID 1443604567-24875-1-git-send-email-andrey.chilikin@intel.com
State Rejected, archived
Delegated to: Bruce Richardson
Headers show

Commit Message

Chilikin, Andrey Sept. 30, 2015, 9:16 a.m.
This patch applies new default values to flexible payload configuration for flow director filter

Signed-off-by: Andrey Chilikin <andrey.chilikin@intel.com>
---
 drivers/net/i40e/i40e_ethdev.c |    6 +++---
 drivers/net/i40e/i40e_fdir.c   |   20 +++++++++++++++-----
 2 files changed, 18 insertions(+), 8 deletions(-)

Comments

Thomas Monjalon Nov. 10, 2015, 3:49 p.m. | #1
2015-09-30 10:16, Andrey Chilikin:
> This patch applies new default values to flexible payload configuration for flow director filter
> 
> Signed-off-by: Andrey Chilikin <andrey.chilikin@intel.com>

Helin, could you review please?
Chilikin, Andrey Feb. 13, 2016, 10:18 a.m. | #2
> -----Original Message-----
> From: Chilikin, Andrey
> Sent: Wednesday, September 30, 2015 10:16 AM
> To: dev@dpdk.org
> Cc: Chilikin, Andrey
> Subject: [PATCH] i40e: fix for default flexible payload registers settings
> 
> This patch applies new default values to flexible payload configuration for flow
> director filter
> 
> Signed-off-by: Andrey Chilikin <andrey.chilikin@intel.com>
> ---

Self NAK. With the current default registers settings FVL handles all use cases the same way as with the new proposed configuration.

Patch

diff --git a/drivers/net/i40e/i40e_ethdev.c b/drivers/net/i40e/i40e_ethdev.c
index 2dd9fdc..0c3b532 100644
--- a/drivers/net/i40e/i40e_ethdev.c
+++ b/drivers/net/i40e/i40e_ethdev.c
@@ -370,9 +370,9 @@  static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 	I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 	I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 	I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
-	I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
-	I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
-	I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000A0);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000A3);
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000A6);
 	I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 	I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 	I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
diff --git a/drivers/net/i40e/i40e_fdir.c b/drivers/net/i40e/i40e_fdir.c
index c9ce98f..8f27694 100644
--- a/drivers/net/i40e/i40e_fdir.c
+++ b/drivers/net/i40e/i40e_fdir.c
@@ -483,13 +483,14 @@  i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 		return -EINVAL;
 	}
 	/* check flexible payload setting configuration */
-	if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
+	if (conf->nb_payloads > I40E_MAX_FLXPLD_LAYER) {
 		PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 		return -EINVAL;
 	}
 	for (i = 0; i < conf->nb_payloads; i++) {
 		flex_cfg = &conf->flex_set[i];
-		if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
+		if (flex_cfg->type < RTE_ETH_L2_PAYLOAD ||
+			flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 			PMD_DRV_LOG(ERR, "invalid payload type.");
 			return -EINVAL;
 		}
@@ -528,6 +529,10 @@  i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 	return 0;
 }
 
+#ifndef I40E_GLQF_ORT
+#define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
+#endif
+
 /*
  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
  * @pf: board private structure
@@ -539,7 +544,7 @@  i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 {
 	struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 	struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
-	uint32_t flx_pit;
+	uint32_t ort, flx_pit;
 	uint16_t num, min_next_off;  /* in words */
 	uint8_t field_idx = 0;
 	uint8_t layer_idx = 0;
@@ -554,8 +559,9 @@  i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 
 	memset(flex_pit, 0, sizeof(flex_pit));
 	num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
+	num = RTE_MIN(num, RTE_DIM(flex_pit));
 
-	for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
+	for (i = 0; i < num; i++) {
 		field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 		/* record the info in fdir structure */
 		pf->fdir.flex_set[field_idx].src_offset =
@@ -576,12 +582,16 @@  i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 	for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 		/* set the non-used register obeying register's constrain */
 		flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
-			   NONUSE_FLX_PIT_DEST_OFF);
+			   NONUSE_FLX_PIT_DEST_OFF -
+			   I40E_FLX_OFFSET_IN_FIELD_VECTOR);
 		I40E_WRITE_REG(hw,
 			I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 			flx_pit);
 		min_next_off++;
 	}
+
+	ort = 0x80 | (num << 5) | layer_idx * I40E_MAX_FLXPLD_FIED;
+	I40E_WRITE_REG(hw, I40E_GLQF_ORT(layer_idx + 33), ort);
 }
 
 /*