[RFC,v2,3/7] net/mlx5: relax barrier to order UAR writes on aarch64
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Commit Message
To order the writes to host memory and the MMIO device memory,
'DMB' is sufficient on aarch64, as a 'other-multi-copy' architecture.
'DSB' is over-killing, especially in the fast path.
Using the rte_dma_wmb can take the advantage on aarch64 while no
impacting x86 and ppc.
Fixes: 6bf10ab69be0 ("net/mlx5: support 32-bit systems")
Cc: stable@dpdk.org
Signed-off-by: Gavin Hu <gavin.hu@arm.com>
Reviewed-by: Phil Yang <phil.yang@arm.com>
---
drivers/net/mlx5/mlx5_rxtx.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
@@ -546,7 +546,7 @@ __mlx5_uar_write64_relaxed(uint64_t val, void *addr,
static __rte_always_inline void
__mlx5_uar_write64(uint64_t val, void *addr, rte_spinlock_t *lock)
{
- rte_io_wmb();
+ rte_dma_wmb();
__mlx5_uar_write64_relaxed(val, addr, lock);
}