[v3] net/octeontx2: fix PTP and HIGIG2 coexistence
diff mbox series

Message ID 20200114092622.13944-1-kirankumark@marvell.com
State Accepted, archived
Delegated to: Jerin Jacob
Headers show
Series
  • [v3] net/octeontx2: fix PTP and HIGIG2 coexistence
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Checks

Context Check Description
ci/travis-robot warning Travis build: failed
ci/Intel-compilation fail Compilation issues
ci/iol-nxp-Performance success Performance Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/iol-testing success Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/checkpatch success coding style OK

Commit Message

Kiran Kumar Kokkilagadda Jan. 14, 2020, 9:26 a.m. UTC
From: Kiran Kumar K <kirankumark@marvell.com>

octeontx2 PMD does not support both PTP and HIGIG2 together.
added a check to enforce this and updated the Rx offload capabilities when
Higig2 mode enabled

fixes: 602009ee2dfb (net/octeontx2: support HIGIG2)

Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>
---
V3 Changes:
* Fixed commit log

V2 Chanhes:
* Fixed error message

 drivers/net/octeontx2/otx2_ethdev.c | 9 ++++++++-
 drivers/net/octeontx2/otx2_ptp.c    | 5 +++++
 2 files changed, 13 insertions(+), 1 deletion(-)

--
2.17.1

Comments

Jerin Jacob Jan. 14, 2020, 2:07 p.m. UTC | #1
On Tue, Jan 14, 2020 at 2:57 PM <kirankumark@marvell.com> wrote:
>
> From: Kiran Kumar K <kirankumark@marvell.com>
>
> octeontx2 PMD does not support both PTP and HIGIG2 together.
> added a check to enforce this and updated the Rx offload capabilities when
> Higig2 mode enabled
>
> fixes: 602009ee2dfb (net/octeontx2: support HIGIG2)
>
> Signed-off-by: Kiran Kumar K <kirankumark@marvell.com>

Acked-by: Jerin Jacob <jerinj@marvell.com>

Fixed the ./devtools/check-git-log.sh issues.
Applied to dpdk-next-net-mrvl/master. Thanks


> ---
> V3 Changes:
> * Fixed commit log
>
> V2 Chanhes:
> * Fixed error message
>
>  drivers/net/octeontx2/otx2_ethdev.c | 9 ++++++++-
>  drivers/net/octeontx2/otx2_ptp.c    | 5 +++++
>  2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
> index ed329273d..2e91a5ab7 100644
> --- a/drivers/net/octeontx2/otx2_ethdev.c
> +++ b/drivers/net/octeontx2/otx2_ethdev.c
> @@ -18,7 +18,8 @@ nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
>  {
>         uint64_t capa = NIX_RX_OFFLOAD_CAPA;
>
> -       if (otx2_dev_is_vf(dev))
> +       if (otx2_dev_is_vf(dev) ||
> +           dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
>                 capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;
>
>         return capa;
> @@ -1641,6 +1642,12 @@ otx2_nix_configure(struct rte_eth_dev *eth_dev)
>                 goto fail_offloads;
>         }
>
> +       if (dev->ptp_en &&
> +           dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
> +               otx2_err("Both PTP and switch header enabled");
> +               goto free_nix_lf;
> +       }
> +
>         rc = nix_lf_switch_header_type_enable(dev);
>         if (rc) {
>                 otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
> diff --git a/drivers/net/octeontx2/otx2_ptp.c b/drivers/net/octeontx2/otx2_ptp.c
> index f34b9339c..ae5a2b7cd 100644
> --- a/drivers/net/octeontx2/otx2_ptp.c
> +++ b/drivers/net/octeontx2/otx2_ptp.c
> @@ -221,6 +221,11 @@ otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)
>                 return -EINVAL;
>         }
>
> +       if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
> +               otx2_err("Both PTP and switch header enabled");
> +               return -EINVAL;
> +       }
> +
>         /* Allocating a iova address for tx tstamp */
>         const struct rte_memzone *ts;
>         ts = rte_eth_dma_zone_reserve(eth_dev, "otx2_ts",
> --
> 2.17.1
>

Patch
diff mbox series

diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
index ed329273d..2e91a5ab7 100644
--- a/drivers/net/octeontx2/otx2_ethdev.c
+++ b/drivers/net/octeontx2/otx2_ethdev.c
@@ -18,7 +18,8 @@  nix_get_rx_offload_capa(struct otx2_eth_dev *dev)
 {
 	uint64_t capa = NIX_RX_OFFLOAD_CAPA;

-	if (otx2_dev_is_vf(dev))
+	if (otx2_dev_is_vf(dev) ||
+	    dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG)
 		capa &= ~DEV_RX_OFFLOAD_TIMESTAMP;

 	return capa;
@@ -1641,6 +1642,12 @@  otx2_nix_configure(struct rte_eth_dev *eth_dev)
 		goto fail_offloads;
 	}

+	if (dev->ptp_en &&
+	    dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+		otx2_err("Both PTP and switch header enabled");
+		goto free_nix_lf;
+	}
+
 	rc = nix_lf_switch_header_type_enable(dev);
 	if (rc) {
 		otx2_err("Failed to enable switch type nix_lf rc=%d", rc);
diff --git a/drivers/net/octeontx2/otx2_ptp.c b/drivers/net/octeontx2/otx2_ptp.c
index f34b9339c..ae5a2b7cd 100644
--- a/drivers/net/octeontx2/otx2_ptp.c
+++ b/drivers/net/octeontx2/otx2_ptp.c
@@ -221,6 +221,11 @@  otx2_nix_timesync_enable(struct rte_eth_dev *eth_dev)
 		return -EINVAL;
 	}

+	if (dev->npc_flow.switch_header_type == OTX2_PRIV_FLAGS_HIGIG) {
+		otx2_err("Both PTP and switch header enabled");
+		return -EINVAL;
+	}
+
 	/* Allocating a iova address for tx tstamp */
 	const struct rte_memzone *ts;
 	ts = rte_eth_dma_zone_reserve(eth_dev, "otx2_ts",