From patchwork Mon Dec 2 07:48:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xiaolong Ye X-Patchwork-Id: 63442 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@inbox.dpdk.org Delivered-To: patchwork@inbox.dpdk.org Received: from dpdk.org (dpdk.org [92.243.14.124]) by inbox.dpdk.org (Postfix) with ESMTP id 9003AA04B5; Mon, 2 Dec 2019 09:00:02 +0100 (CET) Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id C7D8E1BFA8; Mon, 2 Dec 2019 08:58:18 +0100 (CET) Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by dpdk.org (Postfix) with ESMTP id 5EBD558C4 for ; Mon, 2 Dec 2019 08:58:12 +0100 (CET) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 01 Dec 2019 23:58:12 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.69,268,1571727600"; d="scan'208";a="207993410" Received: from dpdk_yexl_af_xdp.sh.intel.com ([10.67.119.186]) by fmsmga008.fm.intel.com with ESMTP; 01 Dec 2019 23:58:10 -0800 From: Xiaolong Ye To: Beilei Xing , Qi Zhang Cc: dev@dpdk.org, Xiaolong Ye , Doug Dziggel , Michal Litwicki Date: Mon, 2 Dec 2019 15:48:40 +0800 Message-Id: <20191202074935.97629-15-xiaolong.ye@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191202074935.97629-1-xiaolong.ye@intel.com> References: <20191202074935.97629-1-xiaolong.ye@intel.com> Subject: [dpdk-dev] [PATCH 14/69] net/i40e/base: adding flags for PHY types X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Adding bit flags to enable/disable EEE capability on Carlsville HW for 2.5GBase-T and 5GBase-T PHY types as well as 'Set autonomous EEE for relevant enabled PHY types' flag. Signed-off-by: Doug Dziggel Signed-off-by: Michal Litwicki Reviewed-by: Paul M Stillwell Jr Reviewed-by: Michael Alice Reviewed-by: Aleksandr Loktionov Signed-off-by: Xiaolong Ye --- drivers/net/i40e/base/i40e_adminq_cmd.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/net/i40e/base/i40e_adminq_cmd.h b/drivers/net/i40e/base/i40e_adminq_cmd.h index 4454bce5a..9179bbe8f 100644 --- a/drivers/net/i40e/base/i40e_adminq_cmd.h +++ b/drivers/net/i40e/base/i40e_adminq_cmd.h @@ -2027,12 +2027,19 @@ struct i40e_aq_get_phy_abilities_resp { #define I40E_AQ_PHY_FEC_ABILITY_KR 0x40 #define I40E_AQ_PHY_FEC_ABILITY_RS 0x80 __le16 eee_capability; +#ifdef CARLSVILLE_HW +#define I40E_AQ_EEE_AUTO 0x0001 +#endif #define I40E_AQ_EEE_100BASE_TX 0x0002 #define I40E_AQ_EEE_1000BASE_T 0x0004 #define I40E_AQ_EEE_10GBASE_T 0x0008 #define I40E_AQ_EEE_1000BASE_KX 0x0010 #define I40E_AQ_EEE_10GBASE_KX4 0x0020 #define I40E_AQ_EEE_10GBASE_KR 0x0040 +#ifdef CARLSVILLE_HW +#define I40E_AQ_EEE_2_5GBASE_T 0x0100 +#define I40E_AQ_EEE_5GBASE_T 0x0200 +#endif __le32 eeer_val; u8 d3_lpan; #define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01