diff mbox series

[3/3] examples/ip_pipeline: documentation update

Message ID 20191029131942.50298-3-jasvinder.singh@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series [1/3] sched: documentation update |

Checks

Context Check Description
ci/Intel-compilation fail Compilation issues
ci/travis-robot success Travis build: passed
ci/checkpatch success coding style OK

Commit Message

Jasvinder Singh Oct. 29, 2019, 1:19 p.m. UTC 
  Updates documentation for traffic manager cli as per the changes
made to qos scheduler library.

Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
---
 doc/guides/sample_app_ug/ip_pipeline.rst | 24 ++++++++++++++++--------
 1 file changed, 16 insertions(+), 8 deletions(-)

Comments

Cristian Dumitrescu Nov. 4, 2019, 10:29 a.m. UTC | #1 
> -----Original Message-----
> From: Singh, Jasvinder <jasvinder.singh@intel.com>
> Sent: Tuesday, October 29, 2019 1:20 PM
> To: dev@dpdk.org
> Cc: Dumitrescu, Cristian <cristian.dumitrescu@intel.com>; Mcnamara, John
> <john.mcnamara@intel.com>; Kovacevic, Marko
> <marko.kovacevic@intel.com>
> Subject: [PATCH 3/3] examples/ip_pipeline: documentation update
> 
> Updates documentation for traffic manager cli as per the changes
> made to qos scheduler library.
> 
> Signed-off-by: Jasvinder Singh <jasvinder.singh@intel.com>
> ---
>  doc/guides/sample_app_ug/ip_pipeline.rst | 24 ++++++++++++++++--------
>  1 file changed, 16 insertions(+), 8 deletions(-)
> 

Acked-by: Cristian Dumitrescu <cristian.dumitrescu@intel.com>
diff mbox series

Patch

diff --git a/doc/guides/sample_app_ug/ip_pipeline.rst b/doc/guides/sample_app_ug/ip_pipeline.rst
index 4da0fcf89..56014be17 100644
--- a/doc/guides/sample_app_ug/ip_pipeline.rst
+++ b/doc/guides/sample_app_ug/ip_pipeline.rst
@@ -249,27 +249,35 @@  Traffic manager
 
   tmgr subport profile
    <tb_rate> <tb_size>
-   <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate>
+   <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate> <tc4_rate>
+   <tc5_rate> <tc6_rate> <tc7_rate> <tc8_rate>
+   <tc9_rate> <tc10_rate> <tc11_rate> <tc12_rate>
    <tc_period>
-
+   pps <n_pipes_per_subport>
+   qsize <qsize_tc0> <qsize_tc1> <qsize_tc2>
+   <qsize_tc3> <qsize_tc4> <qsize_tc5> <qsize_tc6>
+   <qsize_tc7> <qsize_tc8> <qsize_tc9> <qsize_tc10>
+   <qsize_tc11> <qsize_tc12>
 
  Add traffic manager pipe profile ::
 
   tmgr pipe profile
    <tb_rate> <tb_size>
-   <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate>
+   <tc0_rate> <tc1_rate> <tc2_rate> <tc3_rate> <tc4_rate>
+   <tc5_rate> <tc6_rate> <tc7_rate> <tc8_rate>
+   <tc9_rate> <tc10_rate> <tc11_rate> <tc12_rate>
    <tc_period>
-   <tc_ov_weight> <wrr_weight0..15>
+   <tc_ov_weight>
+   <wrr_weight0..3>
 
  Create traffic manager port ::
 
   tmgr <tmgr_name>
    rate <rate>
    spp <n_subports_per_port>
-   pps <n_pipes_per_subport>
-   qsize <qsize_tc0>
-   <qsize_tc1> <qsize_tc2> <qsize_tc3>
-   fo <frame_overhead> mtu <mtu> cpu <cpu_id>
+   fo <frame_overhead>
+   mtu <mtu>
+   cpu <cpu_id>
 
  Configure traffic manager subport ::