From patchwork Mon Sep 16 23:06:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ying Wang X-Patchwork-Id: 59301 X-Patchwork-Delegate: xiaolong.ye@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id D24B01BFC0; Tue, 17 Sep 2019 09:28:56 +0200 (CEST) Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by dpdk.org (Postfix) with ESMTP id D88F91BFB8 for ; Tue, 17 Sep 2019 09:28:51 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga007.fm.intel.com ([10.253.24.52]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 17 Sep 2019 00:28:51 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,515,1559545200"; d="scan'208";a="187384643" Received: from unknown (HELO npg-dpdk-cvl-yingwang-117d84.sh.intel.com) ([10.67.117.84]) by fmsmga007.fm.intel.com with ESMTP; 17 Sep 2019 00:28:50 -0700 From: Ying Wang To: xiaolong.ye@intel.com, qi.z.zhang@intel.com Cc: dev@dpdk.org, qiming.yang@intel.com, wei.zhao1@intel.com, ying.a.wang@intel.com Date: Tue, 17 Sep 2019 07:06:12 +0800 Message-Id: <20190916230615.411726-3-ying.a.wang@intel.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20190916230615.411726-1-ying.a.wang@intel.com> References: <20190903221522.151382-2-ying.a.wang@intel.com> <20190916230615.411726-1-ying.a.wang@intel.com> Subject: [dpdk-dev] [PATCH v2 2/5] net/ice: add devargs to control pipeline mode X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Qiming Yang Added a devarg to control the mode in generic flow API. We use none-pipeline mode by default. Signed-off-by: Qiming Yang --- doc/guides/nics/ice.rst | 19 +++++++++++++++++++ doc/guides/rel_notes/release_19_11.rst | 2 ++ drivers/net/ice/ice_ethdev.c | 11 ++++++++++- drivers/net/ice/ice_ethdev.h | 1 + 4 files changed, 32 insertions(+), 1 deletion(-) diff --git a/doc/guides/nics/ice.rst b/doc/guides/nics/ice.rst index 59a222e28..37d9054ad 100644 --- a/doc/guides/nics/ice.rst +++ b/doc/guides/nics/ice.rst @@ -61,6 +61,25 @@ Runtime Config Options NOTE: In Safe mode, only very limited features are available, features like RSS, checksum, fdir, tunneling ... are all disabled. +- ``Generic Flow Pipeline Mode Support`` (default ``0``) + + In pipeline mode, a flow can be set at one specific stage by setting parameter + ``priority``. Currently, we support two stages: priority = 0 or !0. Flows with + priority 0 located at the first pipeline stage which typically be used as a firewall + to drop the packet on a blacklist(we called it permission stage). At this stage, + flow rules are created for the device's exact match engine: switch. Flows with priority + !0 located at the second stage, typically packets are classified here and be steered to + specific queue or queue group (we called it distribution stage), At this stage, flow + rules are created for device's flow director engine. + For none-pipeline mode, ``priority`` is ignored, a flow rule can be created as a flow director + rule or a switch rule depends on its pattern/action and the resource allocation situation, + all flows are virtually at the same pipeline stage. + By default, generic flow API is enabled in none-pipeline mode, user can choose to + use pipeline mode by setting ``devargs`` parameter ``pipeline-mode-support``, + for example:: + + -w 80:00.0,pipleline-mode-support=1 + Driver compilation and testing ------------------------------ diff --git a/doc/guides/rel_notes/release_19_11.rst b/doc/guides/rel_notes/release_19_11.rst index 91c31a611..7dc4f004e 100644 --- a/doc/guides/rel_notes/release_19_11.rst +++ b/doc/guides/rel_notes/release_19_11.rst @@ -61,6 +61,8 @@ New Features Updated the Intel ice driver with new features and improvements, including: * Supported device-specific DDP package loading. + * Generic filter enhancement + - Supported pipeline mode. Removed Items ------------- diff --git a/drivers/net/ice/ice_ethdev.c b/drivers/net/ice/ice_ethdev.c index e60cc1943..740c30b1b 100644 --- a/drivers/net/ice/ice_ethdev.c +++ b/drivers/net/ice/ice_ethdev.c @@ -19,9 +19,11 @@ /* devargs */ #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support" +#define ICE_PIPELINE_MODE_SUPPORT_ARG "pipeline-mode-support" static const char * const ice_valid_args[] = { ICE_SAFE_MODE_SUPPORT_ARG, + ICE_PIPELINE_MODE_SUPPORT_ARG, NULL }; @@ -1510,7 +1512,13 @@ static int ice_parse_devargs(struct rte_eth_dev *dev) ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG, &parse_bool, &ad->devargs.safe_mode_support); + if (ret) + goto err_devargs; + + ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG, + &parse_bool, &ad->devargs.pipeline_mode_support); +err_devargs: rte_kvargs_free(kvlist); return ret; } @@ -3925,7 +3933,8 @@ RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd); RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map); RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci"); RTE_PMD_REGISTER_PARAM_STRING(net_ice, - ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"); + ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>" + ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>"); RTE_INIT(ice_init_log) { diff --git a/drivers/net/ice/ice_ethdev.h b/drivers/net/ice/ice_ethdev.h index 926db23d2..9bf5de08d 100644 --- a/drivers/net/ice/ice_ethdev.h +++ b/drivers/net/ice/ice_ethdev.h @@ -285,6 +285,7 @@ struct ice_pf { */ struct ice_devargs { int safe_mode_support; + int pipeline_mode_support; }; /**