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Mon, 26 Aug 2019 12:49:36 +0000 From: Nagadheeraj Rottela To: "akhil.goyal@nxp.com" , "pablo.de.lara.guarch@intel.com" , "mattias.ronnblom@ericsson.com" CC: "dev@dpdk.org" , Srikanth Jampala , Nagadheeraj Rottela Thread-Topic: [PATCH v4 06/11] crypto/nitrox: add hardware queue management functionality Thread-Index: AQHVXAy3HrixV02T5UC6BvF9gRsbAg== Date: Mon, 26 Aug 2019 12:49:36 +0000 Message-ID: <20190826124836.21187-7-rnagadheeraj@marvell.com> References: <4b0fc70c-768a-a474-ace4-b69513412cae@ericsson.com> <20190826124836.21187-1-rnagadheeraj@marvell.com> In-Reply-To: <20190826124836.21187-1-rnagadheeraj@marvell.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: PN1PR01CA0088.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c00:1::28) To MN2PR18MB2797.namprd18.prod.outlook.com (2603:10b6:208:a0::16) x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.13.6 x-originating-ip: [115.113.156.2] x-ms-publictraffictype: Email x-ms-office365-filtering-correlation-id: f9d02725-ee21-4880-de6f-08d72a23d994 x-microsoft-antispam: BCL:0; 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DIR:OUT; SFP:1101; SCL:1; SRVR:MN2PR18MB2512; H:MN2PR18MB2797.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: X1wYobmYBWMvT4VD3TkmR/bJ+rsSyzmcOQapsW85Po9nu1H//NZtwPL2PhzHhStrSONYHbhMHyyxs3lcUGIsqicPFcRU8h7Y/2gJsVZ0CPByEUSVcrL4f+JUMklr0xFXsF0caLR+cCK1ZKlNaBCOgBSOVlYakMUTGD9f1AnBh7LtW1Fe9fNmiCdmJap3mwLPoEK0842nosJSOe7+lJ2c54qH+YtjXVDXWluMRptY+NXVlJJv3SJKVFa87UVOE1zgnPyWKgQ25g9WHi1jOUB82PcmIkBkgdJcoubNs0EjhZ3THMCo1z6OqCX6xF0dcpj/MDFMTwf/24e755IDpJmfAHlM9nmQtNB+2ZO/vTUphaui6dwvF+hTRRBMVzwFHb84vc4G5Ksj/EsZd4T73Q64L8++1y+qEq8TNiS03SdcXwQ= MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: f9d02725-ee21-4880-de6f-08d72a23d994 X-MS-Exchange-CrossTenant-originalarrivaltime: 26 Aug 2019 12:49:36.7573 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: jW3/d+uBXPYSZAMbU/BdB0g4eSG9qgG7GIaVOs0H/hK0cA8XPzreCwcYCzeYdwcyt5JtfDqGZbgwkVdvtIqdp8PkR9WJWaGiDy9zhBmJACs= X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR18MB2512 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:5.22.84,1.0.8 definitions=2019-08-26_07:2019-08-26,2019-08-26 signatures=0 Subject: [dpdk-dev] [PATCH v4 06/11] crypto/nitrox: add hardware queue management functionality X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" Add hardware queue management code corresponding to queue pair setup and release functions. Signed-off-by: Nagadheeraj Rottela --- drivers/crypto/nitrox/nitrox_csr.h | 13 ++++ drivers/crypto/nitrox/nitrox_hal.c | 151 +++++++++++++++++++++++++++++++++++++ drivers/crypto/nitrox/nitrox_hal.h | 128 +++++++++++++++++++++++++++++++ drivers/crypto/nitrox/nitrox_qp.c | 51 ++++++++++++- drivers/crypto/nitrox/nitrox_qp.h | 8 ++ 5 files changed, 347 insertions(+), 4 deletions(-) diff --git a/drivers/crypto/nitrox/nitrox_csr.h b/drivers/crypto/nitrox/nitrox_csr.h index 879104515..fb9a34817 100644 --- a/drivers/crypto/nitrox/nitrox_csr.h +++ b/drivers/crypto/nitrox/nitrox_csr.h @@ -9,6 +9,19 @@ #include #define CSR_DELAY 30 +#define NITROX_CSR_ADDR(bar_addr, offset) (bar_addr + (offset)) + +/* NPS packet registers */ +#define NPS_PKT_IN_INSTR_CTLX(_i) (0x10060 + ((_i) * 0x40000)) +#define NPS_PKT_IN_INSTR_BADDRX(_i) (0x10068 + ((_i) * 0x40000)) +#define NPS_PKT_IN_INSTR_RSIZEX(_i) (0x10070 + ((_i) * 0x40000)) +#define NPS_PKT_IN_DONE_CNTSX(_i) (0x10080 + ((_i) * 0x40000)) +#define NPS_PKT_IN_INSTR_BAOFF_DBELLX(_i) (0x10078 + ((_i) * 0x40000)) +#define NPS_PKT_IN_INT_LEVELSX(_i) (0x10088 + ((_i) * 0x40000)) + +#define NPS_PKT_SLC_CTLX(_i) (0x10000 + ((_i) * 0x40000)) +#define NPS_PKT_SLC_CNTSX(_i) (0x10008 + ((_i) * 0x40000)) +#define NPS_PKT_SLC_INT_LEVELSX(_i) (0x10010 + ((_i) * 0x40000)) /* AQM Virtual Function Registers */ #define AQMQ_QSZX(_i) (0x20008 + ((_i)*0x40000)) diff --git a/drivers/crypto/nitrox/nitrox_hal.c b/drivers/crypto/nitrox/nitrox_hal.c index 3dee59215..3c2c24c23 100644 --- a/drivers/crypto/nitrox/nitrox_hal.c +++ b/drivers/crypto/nitrox/nitrox_hal.c @@ -12,6 +12,157 @@ #define MAX_VF_QUEUES 8 #define MAX_PF_QUEUES 64 +#define NITROX_TIMER_THOLD 0x3FFFFF +#define NITROX_COUNT_THOLD 0xFFFFFFFF + +void +nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring) +{ + union nps_pkt_in_instr_ctl pkt_in_instr_ctl; + uint64_t reg_addr; + int max_retries = 5; + + reg_addr = NPS_PKT_IN_INSTR_CTLX(ring); + pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + pkt_in_instr_ctl.s.enb = 0; + nitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_ctl.u64); + rte_delay_us_block(100); + + /* wait for enable bit to be cleared */ + pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + while (pkt_in_instr_ctl.s.enb && max_retries--) { + rte_delay_ms(10); + pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + } +} + +void +nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port) +{ + union nps_pkt_slc_ctl pkt_slc_ctl; + uint64_t reg_addr; + int max_retries = 5; + + /* clear enable bit */ + reg_addr = NPS_PKT_SLC_CTLX(port); + pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + pkt_slc_ctl.s.enb = 0; + nitrox_write_csr(bar_addr, reg_addr, pkt_slc_ctl.u64); + rte_delay_us_block(100); + + pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + while (pkt_slc_ctl.s.enb && max_retries--) { + rte_delay_ms(10); + pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + } +} + +void +setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize, + phys_addr_t raddr) +{ + union nps_pkt_in_instr_ctl pkt_in_instr_ctl; + union nps_pkt_in_instr_rsize pkt_in_instr_rsize; + union nps_pkt_in_instr_baoff_dbell pkt_in_instr_baoff_dbell; + union nps_pkt_in_done_cnts pkt_in_done_cnts; + uint64_t base_addr, reg_addr; + int max_retries = 5; + + nps_pkt_input_ring_disable(bar_addr, ring); + + /* write base address */ + reg_addr = NPS_PKT_IN_INSTR_BADDRX(ring); + base_addr = raddr; + nitrox_write_csr(bar_addr, reg_addr, base_addr); + rte_delay_us_block(CSR_DELAY); + + /* write ring size */ + reg_addr = NPS_PKT_IN_INSTR_RSIZEX(ring); + pkt_in_instr_rsize.u64 = 0; + pkt_in_instr_rsize.s.rsize = rsize; + nitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_rsize.u64); + rte_delay_us_block(CSR_DELAY); + + /* clear door bell */ + reg_addr = NPS_PKT_IN_INSTR_BAOFF_DBELLX(ring); + pkt_in_instr_baoff_dbell.u64 = 0; + pkt_in_instr_baoff_dbell.s.dbell = 0xFFFFFFFF; + nitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_baoff_dbell.u64); + rte_delay_us_block(CSR_DELAY); + + /* clear done count */ + reg_addr = NPS_PKT_IN_DONE_CNTSX(ring); + pkt_in_done_cnts.u64 = nitrox_read_csr(bar_addr, reg_addr); + nitrox_write_csr(bar_addr, reg_addr, pkt_in_done_cnts.u64); + rte_delay_us_block(CSR_DELAY); + + /* Setup PKT IN RING Interrupt Threshold */ + reg_addr = NPS_PKT_IN_INT_LEVELSX(ring); + nitrox_write_csr(bar_addr, reg_addr, 0xFFFFFFFF); + rte_delay_us_block(CSR_DELAY); + + /* enable ring */ + reg_addr = NPS_PKT_IN_INSTR_CTLX(ring); + pkt_in_instr_ctl.u64 = 0; + pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + pkt_in_instr_ctl.s.is64b = 1; + pkt_in_instr_ctl.s.enb = 1; + nitrox_write_csr(bar_addr, reg_addr, pkt_in_instr_ctl.u64); + rte_delay_us_block(100); + + pkt_in_instr_ctl.u64 = 0; + pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + /* wait for ring to be enabled */ + while (!pkt_in_instr_ctl.s.enb && max_retries--) { + rte_delay_ms(10); + pkt_in_instr_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + } +} + +void +setup_nps_pkt_solicit_output_port(uint8_t *bar_addr, uint16_t port) +{ + union nps_pkt_slc_ctl pkt_slc_ctl; + union nps_pkt_slc_cnts pkt_slc_cnts; + union nps_pkt_slc_int_levels pkt_slc_int_levels; + uint64_t reg_addr; + int max_retries = 5; + + nps_pkt_solicited_port_disable(bar_addr, port); + + /* clear pkt counts */ + reg_addr = NPS_PKT_SLC_CNTSX(port); + pkt_slc_cnts.u64 = nitrox_read_csr(bar_addr, reg_addr); + nitrox_write_csr(bar_addr, reg_addr, pkt_slc_cnts.u64); + rte_delay_us_block(CSR_DELAY); + + /* slc interrupt levels */ + reg_addr = NPS_PKT_SLC_INT_LEVELSX(port); + pkt_slc_int_levels.u64 = 0; + pkt_slc_int_levels.s.bmode = 0; + pkt_slc_int_levels.s.timet = NITROX_TIMER_THOLD; + + if (NITROX_COUNT_THOLD > 0) + pkt_slc_int_levels.s.cnt = NITROX_COUNT_THOLD - 1; + + nitrox_write_csr(bar_addr, reg_addr, pkt_slc_int_levels.u64); + rte_delay_us_block(CSR_DELAY); + + /* enable ring */ + reg_addr = NPS_PKT_SLC_CTLX(port); + pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + pkt_slc_ctl.s.rh = 1; + pkt_slc_ctl.s.z = 1; + pkt_slc_ctl.s.enb = 1; + nitrox_write_csr(bar_addr, reg_addr, pkt_slc_ctl.u64); + rte_delay_us_block(100); + + pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + while (!pkt_slc_ctl.s.enb && max_retries--) { + rte_delay_ms(10); + pkt_slc_ctl.u64 = nitrox_read_csr(bar_addr, reg_addr); + } +} int vf_get_vf_config_mode(uint8_t *bar_addr) diff --git a/drivers/crypto/nitrox/nitrox_hal.h b/drivers/crypto/nitrox/nitrox_hal.h index 6184211a5..dcfbd11d8 100644 --- a/drivers/crypto/nitrox/nitrox_hal.h +++ b/drivers/crypto/nitrox/nitrox_hal.h @@ -10,6 +10,129 @@ #include "nitrox_csr.h" +union nps_pkt_slc_cnts { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t slc_int : 1; + uint64_t uns_int : 1; + uint64_t in_int : 1; + uint64_t mbox_int : 1; + uint64_t resend : 1; + uint64_t raz : 5; + uint64_t timer : 22; + uint64_t cnt : 32; +#else + uint64_t cnt : 32; + uint64_t timer : 22; + uint64_t raz : 5; + uint64_t resend : 1; + uint64_t mbox_int : 1; + uint64_t in_int : 1; + uint64_t uns_int : 1; + uint64_t slc_int : 1; +#endif + } s; +}; + +union nps_pkt_slc_int_levels { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t bmode : 1; + uint64_t raz : 9; + uint64_t timet : 22; + uint64_t cnt : 32; +#else + uint64_t cnt : 32; + uint64_t timet : 22; + uint64_t raz : 9; + uint64_t bmode : 1; +#endif + } s; +}; + +union nps_pkt_slc_ctl { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t raz : 61; + uint64_t rh : 1; + uint64_t z : 1; + uint64_t enb : 1; +#else + uint64_t enb : 1; + uint64_t z : 1; + uint64_t rh : 1; + uint64_t raz : 61; +#endif + } s; +}; + +union nps_pkt_in_instr_ctl { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t raz : 62; + uint64_t is64b : 1; + uint64_t enb : 1; +#else + uint64_t enb : 1; + uint64_t is64b : 1; + uint64_t raz : 62; +#endif + } s; +}; + +union nps_pkt_in_instr_rsize { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t raz : 32; + uint64_t rsize : 32; +#else + uint64_t rsize : 32; + uint64_t raz : 32; +#endif + } s; +}; + +union nps_pkt_in_instr_baoff_dbell { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t aoff : 32; + uint64_t dbell : 32; +#else + uint64_t dbell : 32; + uint64_t aoff : 32; +#endif + } s; +}; + +union nps_pkt_in_done_cnts { + uint64_t u64; + struct { +#if RTE_BYTE_ORDER == RTE_BIG_ENDIAN + uint64_t slc_int : 1; + uint64_t uns_int : 1; + uint64_t in_int : 1; + uint64_t mbox_int : 1; + uint64_t resend : 1; + uint64_t raz : 27; + uint64_t cnt : 32; +#else + uint64_t cnt : 32; + uint64_t raz : 27; + uint64_t resend : 1; + uint64_t mbox_int : 1; + uint64_t in_int : 1; + uint64_t uns_int : 1; + uint64_t slc_int : 1; +#endif + } s; +}; + union aqmq_qsz { uint64_t u64; struct { @@ -33,5 +156,10 @@ enum nitrox_vf_mode { int vf_get_vf_config_mode(uint8_t *bar_addr); int vf_config_mode_to_nr_queues(enum nitrox_vf_mode vf_mode); +void setup_nps_pkt_input_ring(uint8_t *bar_addr, uint16_t ring, uint32_t rsize, + phys_addr_t raddr); +void setup_nps_pkt_solicit_output_port(uint8_t *bar_addr, uint16_t port); +void nps_pkt_input_ring_disable(uint8_t *bar_addr, uint16_t ring); +void nps_pkt_solicited_port_disable(uint8_t *bar_addr, uint16_t port); #endif /* _NITROX_HAL_H_ */ diff --git a/drivers/crypto/nitrox/nitrox_qp.c b/drivers/crypto/nitrox/nitrox_qp.c index 9673bb4f3..a56617247 100644 --- a/drivers/crypto/nitrox/nitrox_qp.c +++ b/drivers/crypto/nitrox/nitrox_qp.c @@ -10,6 +10,38 @@ #include "nitrox_logs.h" #define MAX_CMD_QLEN 16384 +#define CMDQ_PKT_IN_ALIGN 16 + +static int +nitrox_setup_cmdq(struct nitrox_qp *qp, uint8_t *bar_addr, + const char *dev_name, uint8_t instr_size, int socket_id) +{ + char mz_name[RTE_MEMZONE_NAMESIZE]; + const struct rte_memzone *mz; + size_t cmdq_size = qp->count * instr_size; + uint64_t offset; + + snprintf(mz_name, sizeof(mz_name), "%s_cmdq_%d", dev_name, qp->qno); + mz = rte_memzone_reserve_aligned(mz_name, cmdq_size, socket_id, + RTE_MEMZONE_SIZE_HINT_ONLY | + RTE_MEMZONE_256MB, + CMDQ_PKT_IN_ALIGN); + if (!mz) { + NITROX_LOG(ERR, "cmdq memzone reserve failed for %s queue\n", + mz_name); + return -ENOMEM; + } + + qp->cmdq.mz = mz; + offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(qp->qno); + qp->cmdq.dbell_csr_addr = NITROX_CSR_ADDR(bar_addr, offset); + qp->cmdq.ring = mz->addr; + qp->cmdq.instr_size = instr_size; + setup_nps_pkt_input_ring(bar_addr, qp->qno, qp->count, mz->iova); + setup_nps_pkt_solicit_output_port(bar_addr, qp->qno); + + return 0; +} static int nitrox_setup_ridq(struct nitrox_qp *qp, int socket_id) @@ -27,6 +59,15 @@ nitrox_setup_ridq(struct nitrox_qp *qp, int socket_id) return 0; } +static int +nitrox_release_cmdq(struct nitrox_qp *qp, uint8_t *bar_addr) +{ + nps_pkt_solicited_port_disable(bar_addr, qp->qno); + nps_pkt_input_ring_disable(bar_addr, qp->qno); + + return rte_memzone_free(qp->cmdq.mz); +} + int nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name, uint32_t nb_descriptors, uint8_t instr_size, int socket_id) @@ -34,8 +75,6 @@ nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name, int err; uint32_t count; - RTE_SET_USED(bar_addr); - RTE_SET_USED(instr_size); count = rte_align32pow2(nb_descriptors); if (count > MAX_CMD_QLEN) { NITROX_LOG(ERR, "%s: Number of descriptors too big %d," @@ -48,6 +87,10 @@ nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name, qp->count = count; qp->head = qp->tail = 0; rte_atomic16_init(&qp->pending_count); + err = nitrox_setup_cmdq(qp, bar_addr, dev_name, instr_size, socket_id); + if (err) + return err; + err = nitrox_setup_ridq(qp, socket_id); if (err) goto ridq_err; @@ -55,6 +98,7 @@ nitrox_qp_setup(struct nitrox_qp *qp, uint8_t *bar_addr, const char *dev_name, return 0; ridq_err: + nitrox_release_cmdq(qp, bar_addr); return err; } @@ -68,7 +112,6 @@ nitrox_release_ridq(struct nitrox_qp *qp) int nitrox_qp_release(struct nitrox_qp *qp, uint8_t *bar_addr) { - RTE_SET_USED(bar_addr); nitrox_release_ridq(qp); - return 0; + return nitrox_release_cmdq(qp, bar_addr); } diff --git a/drivers/crypto/nitrox/nitrox_qp.h b/drivers/crypto/nitrox/nitrox_qp.h index cf0102ff9..0244c4dbf 100644 --- a/drivers/crypto/nitrox/nitrox_qp.h +++ b/drivers/crypto/nitrox/nitrox_qp.h @@ -11,11 +11,19 @@ struct nitrox_softreq; +struct command_queue { + const struct rte_memzone *mz; + uint8_t *dbell_csr_addr; + uint8_t *ring; + uint8_t instr_size; +}; + struct rid { struct nitrox_softreq *sr; }; struct nitrox_qp { + struct command_queue cmdq; struct rid *ridq; uint32_t count; uint32_t head;