From patchwork Wed Jan 9 10:39:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pavan Nikhilesh Bhagavatula X-Patchwork-Id: 49515 X-Patchwork-Delegate: thomas@monjalon.net Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 6AC171B3DA; Wed, 9 Jan 2019 11:39:58 +0100 (CET) Received: from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com [67.231.156.173]) by dpdk.org (Postfix) with ESMTP id 6F6461B1F3 for ; Wed, 9 Jan 2019 11:39:55 +0100 (CET) Received: from pps.filterd (m0045851.ppops.net [127.0.0.1]) by mx0b-0016f401.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x09AUQYj020016; Wed, 9 Jan 2019 02:39:52 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h=from : to : cc : subject : date : message-id : references : in-reply-to : content-type : content-transfer-encoding : mime-version; s=pfpt0818; bh=ss9YRX/nC1dXtMqU/J+lgFdOdOQVy5xCWvlQJhOrlns=; b=cK9R0Yn37W1h0lG2mhPa0i27CDGc/SBO3PbG+fk6xUAlTkW1hFzdiQ4oXimDqCqm3MxR Zpy/3cMNav41/9KFHybcJeuQqjxbGog1cK9UcJFN4G/uLJUKyAcMIqRCMIogItO9SMl6 +OEcZJX2DMvp0oaKDw7C4eQ8hKdoJueaoQDPzvl+7dC2hfhXCGzY+brAnu1VINMXX34L Cu4Xvi0n7EbeuAGJA3EwRVdvmty0DUkeungls2S8vTf+M+3HlmNMPigdhMQa4C5VEyTW SFadhqtLfROxhLMVF3Lwcpw+GN13k5dQhNvzbLZfnhRZwg4HSnQNgnKmOgUsShSrMBA9 2g== Received: from sc-exch04.marvell.com ([199.233.58.184]) by mx0b-0016f401.pphosted.com with ESMTP id 2pw18fb9cj-4 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT); Wed, 09 Jan 2019 02:39:52 -0800 Received: from SC-EXCH01.marvell.com (10.93.176.81) by SC-EXCH04.marvell.com (10.93.176.84) with Microsoft SMTP Server (TLS) id 15.0.1367.3; Wed, 9 Jan 2019 02:39:51 -0800 Received: from NAM01-BN3-obe.outbound.protection.outlook.com (104.47.33.55) by SC-EXCH01.marvell.com (10.93.176.81) with Microsoft SMTP Server (TLS) id 15.0.1367.3 via Frontend Transport; Wed, 9 Jan 2019 02:39:51 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.onmicrosoft.com; s=selector1-marvell-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=ss9YRX/nC1dXtMqU/J+lgFdOdOQVy5xCWvlQJhOrlns=; b=P5Q8WWDWFcMsPsOj8CFJbiZQ1rwdbj7l0dTese+GY6tBHKPqtTadPGNHZ858rPX7AJoaFDamZhVW56Nmwg7N3pcwbZXumBAc6Qg8rrVLHo4NIHiiPiWBMJagzEd4AuBqCkbOZiwqABOK0VDodaf1HV5SF5RO6iwLedwWXMNXJRU= Received: from CY4PR1801MB1863.namprd18.prod.outlook.com (10.171.255.14) by CY4PR1801MB1895.namprd18.prod.outlook.com (10.171.255.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.1495.7; Wed, 9 Jan 2019 10:39:49 +0000 Received: from CY4PR1801MB1863.namprd18.prod.outlook.com ([fe80::8d37:71d9:3b0c:ad00]) by CY4PR1801MB1863.namprd18.prod.outlook.com ([fe80::8d37:71d9:3b0c:ad00%2]) with mapi id 15.20.1516.010; Wed, 9 Jan 2019 10:39:49 +0000 From: Pavan Nikhilesh Bhagavatula To: Jerin Jacob Kollanukkaran , "Gavin.Hu@arm.com" , "bruce.richardson@intel.com" , "thomas@monjalon.net" CC: "dev@dpdk.org" , Pavan Nikhilesh Bhagavatula Thread-Topic: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific flags Thread-Index: AQHUqAelDe3KUOeoh0Ky7V+4J8HQdw== Date: Wed, 9 Jan 2019 10:39:49 +0000 Message-ID: <20190109103915.29210-2-pbhagavatula@marvell.com> References: <20190106131933.7898-1-jerinj@marvell.com> <20190109103915.29210-1-pbhagavatula@marvell.com> In-Reply-To: <20190109103915.29210-1-pbhagavatula@marvell.com> Accept-Language: en-IN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: BM1PR01CA0086.INDPRD01.PROD.OUTLOOK.COM (2603:1096:b00:1::26) To CY4PR1801MB1863.namprd18.prod.outlook.com (2603:10b6:910:7a::14) x-ms-exchange-messagesentrepresentingtype: 1 x-originating-ip: [49.205.221.51] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; CY4PR1801MB1895; 20:nnW0s4Vc4YVHgA6QohmPQzdydVefB6cbl+Mi0l4VT3pe5t50fAVFoWBUKiTro5IPjPtaZCgwoW/5mBb6VB5fnKgC8QXBFowu9ROAL+Lk4B+JEprI3+QVf+UinhZAE568y1yvl/3PVHBqB41HRBzZ95PT5PG10g+OO2Xm7RdACCQ= x-ms-office365-filtering-correlation-id: 7a492624-8d04-4ec7-d900-08d6761ec787 x-microsoft-antispam: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600109)(711020)(2017052603328)(7153060)(7193020); SRVR:CY4PR1801MB1895; x-ms-traffictypediagnostic: CY4PR1801MB1895: x-microsoft-antispam-prvs: x-forefront-prvs: 0912297777 x-forefront-antispam-report: SFV:NSPM; SFS:(10009020)(39860400002)(346002)(376002)(136003)(366004)(396003)(189003)(199004)(36756003)(105586002)(106356001)(6116002)(68736007)(3846002)(5660300001)(186003)(26005)(25786009)(4326008)(102836004)(52116002)(76176011)(256004)(6506007)(386003)(486006)(81156014)(81166006)(8676002)(107886003)(2616005)(7736002)(2501003)(476003)(53936002)(6486002)(478600001)(305945005)(8936002)(1076003)(11346002)(446003)(6436002)(97736004)(14454004)(2906002)(110136005)(316002)(6512007)(54906003)(78486014)(2201001)(66066001)(71190400001)(86362001)(575784001)(71200400001)(99286004); DIR:OUT; SFP:1101; SCL:1; SRVR:CY4PR1801MB1895; H:CY4PR1801MB1863.namprd18.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: marvell.com does not designate permitted sender hosts) x-ms-exchange-senderadcheck: 1 x-microsoft-antispam-message-info: Vfx94P3W/bN/lRUzN1Qmyzly90K5phksYmj1Eys21MOFrLNr+IDMhCp6EKymiPaNYthbadVz+8Ccq6Zy3j84GycucdfVm7hSpqUU7Z4WhdEoPpyfmRm7gd9pMT9gSpqmglvLR4Oq+OrlnvBPM6T1q/3VNxhgKe0qhKzSfZnRMTFHKVuLTsYd7OI3vg4u7C66SKK7NGuLQ3b7W9zpDjSunBq+e5Xxcr0oXDr2upN7TFpMGarpvgEfHRBMkHbhjAaY3QP3+yCEP4G4vnVz5elXt/2wlcMwi1WuAiQf3xRYHqV/4MPk5yyWJc6REfkTYlkx spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM MIME-Version: 1.0 X-MS-Exchange-CrossTenant-Network-Message-Id: 7a492624-8d04-4ec7-d900-08d6761ec787 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jan 2019 10:39:49.2592 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 70e1fb47-1155-421d-87fc-2e58f638b6e0 X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY4PR1801MB1895 X-OriginatorOrg: marvell.com X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-01-09_06:, , signatures=0 X-Proofpoint-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1810050000 definitions=main-1901090090 Subject: [dpdk-dev] [PATCH v4 2/5] meson: add infra to support machine specific flags X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Pavan Nikhilesh Currently, RTE_* flags are set based on the implementer ID but there might be some micro arch specific differences from the same vendor eg. CACHE_LINESIZE. Add support to set micro arch specific flags. Signed-off-by: Jerin Jacob Signed-off-by: Pavan Nikhilesh --- config/arm/meson.build | 53 +++++++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 21 deletions(-) diff --git a/config/arm/meson.build b/config/arm/meson.build index dae55d6b2..576363fc0 100644 --- a/config/arm/meson.build +++ b/config/arm/meson.build @@ -7,23 +7,6 @@ march_opt = '-march=@0@'.format(machine) arm_force_native_march = false -machine_args_generic = [ - ['default', ['-march=armv8-a+crc+crypto']], - ['native', ['-march=native']], - ['0xd03', ['-mcpu=cortex-a53']], - ['0xd04', ['-mcpu=cortex-a35']], - ['0xd07', ['-mcpu=cortex-a57']], - ['0xd08', ['-mcpu=cortex-a72']], - ['0xd09', ['-mcpu=cortex-a73']], - ['0xd0a', ['-mcpu=cortex-a75']], -] -machine_args_cavium = [ - ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], - ['native', ['-march=native']], - ['0xa1', ['-mcpu=thunderxt88']], - ['0xa2', ['-mcpu=thunderxt81']], - ['0xa3', ['-mcpu=thunderxt83']]] - flags_common_default = [ # Accelarate rte_memcpy. Be sure to run unit test (memcpy_perf_autotest) # to determine the best threshold in code. Refer to notes in source file @@ -50,12 +33,10 @@ flags_generic = [ ['RTE_USE_C11_MEM_MODEL', true], ['RTE_CACHE_LINE_SIZE', 128]] flags_cavium = [ - ['RTE_MACHINE', '"thunderx"'], ['RTE_CACHE_LINE_SIZE', 128], ['RTE_MAX_NUMA_NODES', 2], ['RTE_MAX_LCORE', 96], - ['RTE_MAX_VFIO_GROUPS', 128], - ['RTE_USE_C11_MEM_MODEL', false]] + ['RTE_MAX_VFIO_GROUPS', 128]] flags_dpaa = [ ['RTE_MACHINE', '"dpaa"'], ['RTE_USE_C11_MEM_MODEL', true], @@ -69,6 +50,27 @@ flags_dpaa2 = [ ['RTE_MAX_NUMA_NODES', 1], ['RTE_MAX_LCORE', 16], ['RTE_LIBRTE_DPAA2_USE_PHYS_IOVA', false]] +flags_default_extra = [] +flags_thunderx_extra = [ + ['RTE_MACHINE', '"thunderx"'], + ['RTE_USE_C11_MEM_MODEL', false]] + +machine_args_generic = [ + ['default', ['-march=armv8-a+crc+crypto']], + ['native', ['-march=native']], + ['0xd03', ['-mcpu=cortex-a53']], + ['0xd04', ['-mcpu=cortex-a35']], + ['0xd07', ['-mcpu=cortex-a57']], + ['0xd08', ['-mcpu=cortex-a72']], + ['0xd09', ['-mcpu=cortex-a73']], + ['0xd0a', ['-mcpu=cortex-a75']]] + +machine_args_cavium = [ + ['default', ['-march=armv8-a+crc+crypto','-mcpu=thunderx']], + ['native', ['-march=native']], + ['0xa1', ['-mcpu=thunderxt88'], flags_thunderx_extra], + ['0xa2', ['-mcpu=thunderxt81'], flags_thunderx_extra], + ['0xa3', ['-mcpu=thunderxt83'], flags_thunderx_extra]] ## Arm implementer ID (ARM DDI 0487C.a, Section G7.2.106, Page G7-5321) impl_generic = ['Generic armv8', flags_generic, machine_args_generic] @@ -157,10 +159,19 @@ else foreach marg: machine[2] if marg[0] == impl_pn foreach f: marg[1] - machine_args += f + if cc.has_argument(f) + machine_args += f + endif endforeach endif endforeach + + # Apply any extra machine specific flags. + foreach flag: marg.get(2, flags_default_extra) + if flag.length() > 0 + dpdk_conf.set(flag[0], flag[1]) + endif + endforeach endif message(machine_args)