common/qat: add support for GEN3 devices

Message ID 1538428664-15776-1-git-send-email-fiona.trahe@intel.com
State Accepted, archived
Delegated to: akhil goyal
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Series
  • common/qat: add support for GEN3 devices
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Checks

Context Check Description
ci/Intel-compilation success Compilation OK
ci/checkpatch success coding style OK

Commit Message

Trahe, Fiona Oct. 1, 2018, 9:17 p.m.
This adds pci detection, queue-pair configuration and
documentation for Intel GEN3 QuickAssist devices.

Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
---
 doc/guides/cryptodevs/qat.rst          |  3 +++
 doc/guides/rel_notes/release_18_11.rst |  4 ++++
 drivers/common/qat/qat_common.h        |  3 ++-
 drivers/common/qat/qat_device.c        | 11 +++++++++-
 drivers/common/qat/qat_qp.c            | 38 ++++++++++++++++++++++++++++++++++
 drivers/common/qat/qat_qp.h            |  1 +
 drivers/compress/qat/qat_comp_pmd.c    |  1 +
 drivers/crypto/qat/qat_sym_pmd.c       |  1 +
 8 files changed, 60 insertions(+), 2 deletions(-)

Comments

Jozwiak, TomaszX Oct. 9, 2018, 1:19 p.m. | #1
> -----Original Message-----
> From: Trahe, Fiona
> Sent: Monday, October 1, 2018 10:18 PM
> To: dev@dpdk.org
> Cc: akhil.goyal@nxp.com; stable@dpdk.org; Jozwiak, TomaszX
> <tomaszx.jozwiak@intel.com>; Trahe, Fiona <fiona.trahe@intel.com>
> Subject: [PATCH] common/qat: add support for GEN3 devices
> 
> This adds pci detection, queue-pair configuration and documentation for
> Intel GEN3 QuickAssist devices.
> 
> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
> ---

Acked-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Akhil Goyal Oct. 10, 2018, 11:39 a.m. | #2
On 10/9/2018 6:49 PM, Jozwiak, TomaszX wrote:
>> -----Original Message-----
>> From: Trahe, Fiona
>> Sent: Monday, October 1, 2018 10:18 PM
>> To: dev@dpdk.org
>> Cc: akhil.goyal@nxp.com; stable@dpdk.org; Jozwiak, TomaszX
>> <tomaszx.jozwiak@intel.com>; Trahe, Fiona <fiona.trahe@intel.com>
>> Subject: [PATCH] common/qat: add support for GEN3 devices
>>
>> This adds pci detection, queue-pair configuration and documentation for
>> Intel GEN3 QuickAssist devices.
>>
>> Signed-off-by: Fiona Trahe <fiona.trahe@intel.com>
>> ---
> Acked-by: Tomasz Jozwiak <tomaszx.jozwiak@intel.com>
Applied to dpdk-next-crypto

Thanks.

Patch

diff --git a/doc/guides/cryptodevs/qat.rst b/doc/guides/cryptodevs/qat.rst
index 5793e36..7d51084 100644
--- a/doc/guides/cryptodevs/qat.rst
+++ b/doc/guides/cryptodevs/qat.rst
@@ -23,6 +23,7 @@  hardware accelerator devices:
 * ``Intel QuickAssist Technology C62x``
 * ``Intel QuickAssist Technology C3xxx``
 * ``Intel QuickAssist Technology D15xx``
+* ``Intel QuickAssist Technology C4xxx``
 
 
 Features
@@ -254,6 +255,8 @@  to check that the driver and device supports the service you require.
    +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
    | 2   | D15xx    | p             | qat_d15xx     | d15xx      | 6f54   | 1    | 6f55   | 16     | Yes       | No          |
    +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
+   | 3   | C4xxx    | p             | qat_c4xxx     | c4xxx      | 18a0   | 1    | 18a1   | 128    | Yes       | No          |
+   +-----+----------+---------------+---------------+------------+--------+------+--------+--------+-----------+-------------+
 
 
 The ``Driver`` column indicates either the Linux kernel version in which
diff --git a/doc/guides/rel_notes/release_18_11.rst b/doc/guides/rel_notes/release_18_11.rst
index 9c00e33..f97f39a 100644
--- a/doc/guides/rel_notes/release_18_11.rst
+++ b/doc/guides/rel_notes/release_18_11.rst
@@ -88,6 +88,10 @@  New Features
   the specified port. The port must be stopped before the command call in order
   to reconfigure queues.
 
+* **Added support for GEN3 devices to Intel QAT driver .**
+
+  Added support for the third generation of Intel QuickAssist devices.
+
 
 API Changes
 -----------
diff --git a/drivers/common/qat/qat_common.h b/drivers/common/qat/qat_common.h
index d4bef53..de9a3ba 100644
--- a/drivers/common/qat/qat_common.h
+++ b/drivers/common/qat/qat_common.h
@@ -17,7 +17,8 @@ 
  */
 enum qat_device_gen {
 	QAT_GEN1 = 1,
-	QAT_GEN2
+	QAT_GEN2,
+	QAT_GEN3
 };
 
 enum qat_service_type {
diff --git a/drivers/common/qat/qat_device.c b/drivers/common/qat/qat_device.c
index f32d723..b158fb9 100644
--- a/drivers/common/qat/qat_device.c
+++ b/drivers/common/qat/qat_device.c
@@ -20,6 +20,10 @@  struct qat_gen_hw_data qat_gen_config[] =  {
 		.qp_hw_data = qat_gen1_qps,
 		/* gen2 has same ring layout as gen1 */
 	},
+	[QAT_GEN3] = {
+		.dev_gen = QAT_GEN3,
+		.qp_hw_data = qat_gen3_qps,
+	},
 };
 
 
@@ -43,10 +47,12 @@  static const struct rte_pci_id pci_id_qat_map[] = {
 		{
 			RTE_PCI_DEVICE(0x8086, 0x6f55),
 		},
+		{
+			RTE_PCI_DEVICE(0x8086, 0x18a1),
+		},
 		{.device_id = 0},
 };
 
-
 static struct qat_pci_device *
 qat_pci_get_dev(uint8_t dev_id)
 {
@@ -130,6 +136,9 @@  qat_pci_device_allocate(struct rte_pci_device *pci_dev)
 	case 0x6f55:
 		qat_dev->qat_dev_gen = QAT_GEN2;
 		break;
+	case 0x18a1:
+		qat_dev->qat_dev_gen = QAT_GEN3;
+		break;
 	default:
 		QAT_LOG(ERR, "Invalid dev_id, can't determine generation");
 		return NULL;
diff --git a/drivers/common/qat/qat_qp.c b/drivers/common/qat/qat_qp.c
index 7ca7a45..1d83aac 100644
--- a/drivers/common/qat/qat_qp.c
+++ b/drivers/common/qat/qat_qp.c
@@ -90,6 +90,44 @@  const struct qat_qp_hw_data qat_gen1_qps[QAT_MAX_SERVICES]
 	}
 };
 
+__extension__
+const struct qat_qp_hw_data qat_gen3_qps[QAT_MAX_SERVICES]
+					 [ADF_MAX_QPS_ON_ANY_SERVICE] = {
+	/* queue pairs which provide an asymmetric crypto service */
+	[QAT_SERVICE_ASYMMETRIC] = {
+		{
+			.service_type = QAT_SERVICE_ASYMMETRIC,
+			.hw_bundle_num = 0,
+			.tx_ring_num = 0,
+			.rx_ring_num = 4,
+			.tx_msg_size = 64,
+			.rx_msg_size = 32,
+		}
+	},
+	/* queue pairs which provide a symmetric crypto service */
+	[QAT_SERVICE_SYMMETRIC] = {
+		{
+			.service_type = QAT_SERVICE_SYMMETRIC,
+			.hw_bundle_num = 0,
+			.tx_ring_num = 1,
+			.rx_ring_num = 5,
+			.tx_msg_size = 128,
+			.rx_msg_size = 32,
+		}
+	},
+	/* queue pairs which provide a compression service */
+	[QAT_SERVICE_COMPRESSION] = {
+		{
+			.service_type = QAT_SERVICE_COMPRESSION,
+			.hw_bundle_num = 0,
+			.tx_ring_num = 3,
+			.rx_ring_num = 7,
+			.tx_msg_size = 128,
+			.rx_msg_size = 32,
+		}
+	}
+};
+
 static int qat_qp_check_queue_alignment(uint64_t phys_addr,
 	uint32_t queue_size_bytes);
 static void qat_queue_delete(struct qat_queue *queue);
diff --git a/drivers/common/qat/qat_qp.h b/drivers/common/qat/qat_qp.h
index 69f8a61..6f1525e 100644
--- a/drivers/common/qat/qat_qp.h
+++ b/drivers/common/qat/qat_qp.h
@@ -85,6 +85,7 @@  struct qat_qp {
 } __rte_cache_aligned;
 
 extern const struct qat_qp_hw_data qat_gen1_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
+extern const struct qat_qp_hw_data qat_gen3_qps[][ADF_MAX_QPS_ON_ANY_SERVICE];
 
 uint16_t
 qat_enqueue_op_burst(void *qp, void **ops, uint16_t nb_ops);
diff --git a/drivers/compress/qat/qat_comp_pmd.c b/drivers/compress/qat/qat_comp_pmd.c
index 1b29540..6510cca 100644
--- a/drivers/compress/qat/qat_comp_pmd.c
+++ b/drivers/compress/qat/qat_comp_pmd.c
@@ -409,6 +409,7 @@  qat_comp_dev_create(struct qat_pci_device *qat_pci_dev)
 	switch (qat_pci_dev->qat_dev_gen) {
 	case QAT_GEN1:
 	case QAT_GEN2:
+	case QAT_GEN3:
 		comp_dev->qat_dev_capabilities = qat_comp_gen_capabilities;
 		break;
 	default:
diff --git a/drivers/crypto/qat/qat_sym_pmd.c b/drivers/crypto/qat/qat_sym_pmd.c
index fb93030..82fde16 100644
--- a/drivers/crypto/qat/qat_sym_pmd.c
+++ b/drivers/crypto/qat/qat_sym_pmd.c
@@ -292,6 +292,7 @@  qat_sym_dev_create(struct qat_pci_device *qat_pci_dev)
 		internals->qat_dev_capabilities = qat_gen1_sym_capabilities;
 		break;
 	case QAT_GEN2:
+	case QAT_GEN3:
 		internals->qat_dev_capabilities = qat_gen2_sym_capabilities;
 		break;
 	default: