diff mbox series

[v2] net/ixgbe: fix mask bits register set error for FDIR

Message ID 1528960893-18630-1-git-send-email-wei.zhao1@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Qi Zhang
Headers
Series [v2] net/ixgbe: fix mask bits register set error for FDIR |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Zhao1, Wei June 14, 2018, 7:21 a.m. UTC 
  MAC address bits in mask registers should be set to zero
when the is mac mask is 0xFF, otherwise if it is 0x0
these bits should be to 0x3F, it also support other mask
like 0xF and so on.

Fixes: 82fb702077f6 ("ixgbe: support new flow director modes for X550")

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
---

v2:
-change mask bits set method to support more mac mask.

---
 drivers/net/ixgbe/ixgbe_fdir.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/drivers/net/ixgbe/ixgbe_fdir.c b/drivers/net/ixgbe/ixgbe_fdir.c
index 3feb815..dea8862 100644
--- a/drivers/net/ixgbe/ixgbe_fdir.c
+++ b/drivers/net/ixgbe/ixgbe_fdir.c
@@ -394,9 +394,9 @@  fdir_set_input_mask_x550(struct rte_eth_dev *dev)
 				IXGBE_FDIRIP6M_TNI_VNI;
 
 	if (mode == RTE_FDIR_MODE_PERFECT_TUNNEL) {
-		mac_mask = info->mask.mac_addr_byte_mask;
-		fdiripv6m |= (mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT)
-				& IXGBE_FDIRIP6M_INNER_MAC;
+		mac_mask = info->mask.mac_addr_byte_mask & 0x3F;
+		fdiripv6m &= ~((mac_mask << IXGBE_FDIRIP6M_INNER_MAC_SHIFT) &
+				IXGBE_FDIRIP6M_INNER_MAC);
 
 		switch (info->mask.tunnel_type_mask) {
 		case 0: