From patchwork Wed Jun 13 12:14:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomasz Jozwiak X-Patchwork-Id: 41056 X-Patchwork-Delegate: pablo.de.lara.guarch@intel.com Return-Path: X-Original-To: patchwork@dpdk.org Delivered-To: patchwork@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 5C7B41EF7A; Wed, 13 Jun 2018 14:15:28 +0200 (CEST) Received: from mga12.intel.com (mga12.intel.com [192.55.52.136]) by dpdk.org (Postfix) with ESMTP id C28111EF8C for ; Wed, 13 Jun 2018 14:15:02 +0200 (CEST) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by fmsmga106.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Jun 2018 05:14:59 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.51,218,1526367600"; d="scan'208";a="63727765" Received: from tjozwiax-mobl.ger.corp.intel.com (HELO localhost.localdomain) ([10.103.104.42]) by fmsmga001.fm.intel.com with ESMTP; 13 Jun 2018 05:14:57 -0700 From: Tomasz Jozwiak To: fiona.trahe@intel.com, tomaszx.jozwiak@intel.com, dev@dpdk.org Date: Wed, 13 Jun 2018 14:14:08 +0200 Message-Id: <1528892062-4997-25-git-send-email-tomaszx.jozwiak@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com> References: <1523040732-3290-1-git-send-email-fiona.trahe@intel.com> <1528892062-4997-1-git-send-email-tomaszx.jozwiak@intel.com> Subject: [dpdk-dev] [PATCH v3 24/38] crypto/qat: add lock around csr access and change logic X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Fiona Trahe Add lock around accesses to the arbiter CSR and use & instead of ^ as ^ not safe if arb_disable called when already disabled. Signed-off-by: Fiona Trahe --- drivers/crypto/qat/qat_qp.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/crypto/qat/qat_qp.c b/drivers/crypto/qat/qat_qp.c index 7b2dc3f90..f26fd0900 100644 --- a/drivers/crypto/qat/qat_qp.c +++ b/drivers/crypto/qat/qat_qp.c @@ -107,8 +107,10 @@ static int qat_queue_create(struct qat_pci_device *qat_dev, static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num, uint32_t *queue_size_for_csr); static void adf_configure_queues(struct qat_qp *queue); -static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr); -static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr); +static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr, + rte_spinlock_t *lock); +static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr, + rte_spinlock_t *lock); int qat_qps_per_service(const struct qat_qp_hw_data *qp_hw_data, @@ -216,7 +218,8 @@ int qat_qp_setup(struct qat_pci_device *qat_dev, } adf_configure_queues(qp); - adf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr); + adf_queue_arb_enable(&qp->tx_q, qp->mmap_bar_addr, + &qat_dev->arb_csr_lock); snprintf(op_cookie_pool_name, RTE_RING_NAMESIZE, "%s%d_cookies_%s_qp%hu", @@ -282,7 +285,8 @@ int qat_qp_release(struct qat_qp **qp_addr) return -EAGAIN; } - adf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr); + adf_queue_arb_disable(&(qp->tx_q), qp->mmap_bar_addr, + &qp->qat_dev->arb_csr_lock); for (i = 0; i < qp->nb_descriptors; i++) rte_mempool_put(qp->op_cookie_pool, qp->op_cookies[i]); @@ -443,7 +447,8 @@ static int adf_verify_queue_size(uint32_t msg_size, uint32_t msg_num, return -EINVAL; } -static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr) +static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr, + rte_spinlock_t *lock) { uint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * @@ -451,12 +456,16 @@ static void adf_queue_arb_enable(struct qat_queue *txq, void *base_addr) uint32_t value; PMD_INIT_FUNC_TRACE(); + + rte_spinlock_lock(lock); value = ADF_CSR_RD(base_addr, arb_csr_offset); value |= (0x01 << txq->hw_queue_number); ADF_CSR_WR(base_addr, arb_csr_offset, value); + rte_spinlock_unlock(lock); } -static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr) +static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr, + rte_spinlock_t *lock) { uint32_t arb_csr_offset = ADF_ARB_RINGSRVARBEN_OFFSET + (ADF_ARB_REG_SLOT * @@ -464,9 +473,12 @@ static void adf_queue_arb_disable(struct qat_queue *txq, void *base_addr) uint32_t value; PMD_INIT_FUNC_TRACE(); + + rte_spinlock_lock(lock); value = ADF_CSR_RD(base_addr, arb_csr_offset); - value ^= (0x01 << txq->hw_queue_number); + value &= ~(0x01 << txq->hw_queue_number); ADF_CSR_WR(base_addr, arb_csr_offset, value); + rte_spinlock_unlock(lock); } static void adf_configure_queues(struct qat_qp *qp)