[dpdk-dev,v2,5/6] i40e: Initialize hash function during port initialization.
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Message ID 1406535955-31070-6-git-send-email-helin.zhang@intel.com
State Superseded, archived
Headers show

Commit Message

Helin Zhang July 28, 2014, 8:25 a.m. UTC
As hash function are configured in gloabal registers, those
registers will not be reloaded unless a gloabl NIC hardware
reset. That means a DPDK application launch will not load
the default configuration of hash functions. It needs an
initialization of those registers during the port
initialization to make sure all those registers are in an
expected state.

Signed-off-by: Helin Zhang <helin.zhang@intel.com>
---
 lib/librte_pmd_i40e/i40e_ethdev.c | 71 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 71 insertions(+)

Patch
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diff --git a/lib/librte_pmd_i40e/i40e_ethdev.c b/lib/librte_pmd_i40e/i40e_ethdev.c
index 87a4999..386d864 100644
--- a/lib/librte_pmd_i40e/i40e_ethdev.c
+++ b/lib/librte_pmd_i40e/i40e_ethdev.c
@@ -204,6 +204,7 @@  static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 				    struct rte_eth_rss_conf *rss_conf);
 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 				      struct rte_eth_rss_conf *rss_conf);
+static void i40e_init_hash_function(struct i40e_hw *hw);
 static int i40e_dev_is_command_supported(struct rte_eth_dev *dev __rte_unused,
 					 enum rte_eth_command cmd);
 static int i40e_rx_classification_filter_ctl(struct rte_eth_dev *dev,
@@ -392,6 +393,9 @@  eth_i40e_dev_init(__rte_unused struct eth_driver *eth_drv,
 		return ret;
 	}
 
+	/* Init hash functions */
+	i40e_init_hash_function(hw);
+
 	/* Initialize the shared code (base driver) */
 	ret = i40e_init_shared_code(hw);
 	if (ret) {
@@ -4369,3 +4373,70 @@  i40e_rx_classification_filter_ctl(struct rte_eth_dev *dev,
 
 	return ret;
 }
+
+/**
+ * Initialize hash functions. It includes,
+ * - set hash function to Toeplitz.
+ * - set the default filter swap configurations.
+ * - disable hash function enable per port.
+ * - disable hash function enable per pctype.
+ * Only global reset can reload the firmware configurations.
+ */
+static void
+i40e_init_hash_function(struct i40e_hw *hw)
+{
+	static struct rte_i40e_filter_swap_info swap_info[] = {
+		{ETH_PCTYPE_NONF_IPV4_UDP,
+			0x1e, 0x36, 0x04, 0x3a, 0x3c, 0x02},
+		{ETH_PCTYPE_NONF_IPV4_TCP,
+			0x1e, 0x36, 0x04, 0x3a, 0x3c, 0x02},
+		{ETH_PCTYPE_NONF_IPV4_SCTP,
+			0x1e, 0x36, 0x04, 0x00, 0x00, 0x00},
+		{ETH_PCTYPE_NONF_IPV4_OTHER,
+			0x1e, 0x36, 0x04, 0x00, 0x00, 0x00},
+		{ETH_PCTYPE_FRAG_IPV4,
+			0x1e, 0x36, 0x04, 0x00, 0x00, 0x00},
+		{ETH_PCTYPE_NONF_IPV6_UDP,
+			0x1a, 0x2a, 0x10, 0x3a, 0x3c, 0x02},
+		{ETH_PCTYPE_NONF_IPV6_TCP,
+			0x1a, 0x2a, 0x10, 0x3a, 0x3c, 0x02},
+		{ETH_PCTYPE_NONF_IPV6_SCTP,
+			0x1a, 0x2a, 0x10, 0x00, 0x00, 0x00},
+		{ETH_PCTYPE_NONF_IPV6_OTHER,
+			0x1a, 0x2a, 0x10, 0x00, 0x00, 0x00},
+		{ETH_PCTYPE_FRAG_IPV6,
+			0x1a, 0x2a, 0x10, 0x00, 0x00, 0x00},
+		{ETH_PCTYPE_L2_PAYLOAD,
+			0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
+	};
+	static struct rte_i40e_sym_hash_enable_info sym_hash_ena_info[] = {
+		{ETH_PCTYPE_NONF_IPV4_UDP, 0},
+		{ETH_PCTYPE_NONF_IPV4_TCP, 0},
+		{ETH_PCTYPE_NONF_IPV4_SCTP, 0},
+		{ETH_PCTYPE_NONF_IPV4_OTHER, 0},
+		{ETH_PCTYPE_FRAG_IPV4, 0},
+		{ETH_PCTYPE_NONF_IPV6_UDP, 0},
+		{ETH_PCTYPE_NONF_IPV6_TCP, 0},
+		{ETH_PCTYPE_NONF_IPV6_SCTP, 0},
+		{ETH_PCTYPE_NONF_IPV6_OTHER, 0},
+		{ETH_PCTYPE_FRAG_IPV6, 0},
+		{ETH_PCTYPE_L2_PAYLOAD, 0},
+	};
+	static enum rte_i40e_hash_function hf = rte_i40e_hash_function_toeplitz;
+	uint32_t i;
+
+	/* set hash function to Toeplitz by default */
+	i40e_set_hash_function(hw, &hf);
+
+	/* initialize filter swap */
+	for (i = 0; i < RTE_DIM(swap_info); i++)
+		i40e_set_filter_swap(hw, &swap_info[i]);
+
+	/* disable all symmetric hash per pctype */
+	for (i = 0; i < RTE_DIM(sym_hash_ena_info); i++)
+		i40e_set_symmetric_hash_enable_per_pctype(hw,
+					&sym_hash_ena_info[i]);
+
+	/* disable symmetric hash per port */
+	i40e_set_symmetric_hash_enable_per_port(hw, 0);
+}