[3/6] bus/pci: use IOVAs check when setting IOVA mode
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Commit Message
Although VT-d emulation currently only supports 39 bits, it could
be iovas being within that supported range. This patch allows
IOVA mode in such a case.
Indeed, memory initialization code can be modified for using lower
virtual addresses than those used by the kernel for 64 bits processes
by default, and therefore memsegs iovas can use 39 bits or less for
most system. And this is likely 100% true for VMs.
Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
---
drivers/bus/pci/linux/pci.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
Comments
On 02-Jul-18 6:27 PM, Alejandro Lucero wrote:
> Although VT-d emulation currently only supports 39 bits, it could
> be iovas being within that supported range. This patch allows
> IOVA mode in such a case.
>
> Indeed, memory initialization code can be modified for using lower
> virtual addresses than those used by the kernel for 64 bits processes
> by default, and therefore memsegs iovas can use 39 bits or less for
> most system. And this is likely 100% true for VMs.
>
> Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
> ---
General question - is this issue only applicable to PCI? Do other buses
need this?
On Tue, Jul 3, 2018 at 10:10 AM, Burakov, Anatoly <anatoly.burakov@intel.com
> wrote:
> On 02-Jul-18 6:27 PM, Alejandro Lucero wrote:
>
>> Although VT-d emulation currently only supports 39 bits, it could
>> be iovas being within that supported range. This patch allows
>> IOVA mode in such a case.
>>
>> Indeed, memory initialization code can be modified for using lower
>> virtual addresses than those used by the kernel for 64 bits processes
>> by default, and therefore memsegs iovas can use 39 bits or less for
>> most system. And this is likely 100% true for VMs.
>>
>> Signed-off-by: Alejandro Lucero <alejandro.lucero@netronome.com>
>> ---
>>
>
> General question - is this issue only applicable to PCI? Do other buses
> need this?
>
>
I think there could be other buses or devices with those limitations.
Ideally, we could do more things like just discarding those memsegs out of
range, but that would imply other changes.
IMHO, this is good enough and just if it turns out this is causing
problems, other solution should be implemented. But with most current
systems out there, I do not think this is a priority.
> --
> Thanks,
> Anatoly
>
@@ -43,6 +43,7 @@
#include <rte_devargs.h>
#include <rte_memcpy.h>
#include <rte_vfio.h>
+#include <rte_memory.h>
#include "eal_private.h"
#include "eal_filesystem.h"
@@ -613,10 +614,12 @@
fclose(fp);
mgaw = ((vtd_cap_reg & VTD_CAP_MGAW_MASK) >> VTD_CAP_MGAW_SHIFT) + 1;
- if (mgaw < X86_VA_WIDTH)
+
+ if (!rte_eal_check_dma_mask(mgaw))
+ return true;
+ else
return false;
- return true;
}
#elif defined(RTE_ARCH_PPC_64)
static bool
@@ -640,13 +643,17 @@
{
struct rte_pci_device *dev = NULL;
struct rte_pci_driver *drv = NULL;
+ int iommu_dma_mask_check_done = 0;
FOREACH_DRIVER_ON_PCIBUS(drv) {
FOREACH_DEVICE_ON_PCIBUS(dev) {
if (!rte_pci_match(drv, dev))
continue;
- if (!pci_one_device_iommu_support_va(dev))
- return false;
+ if (!iommu_dma_mask_check_done) {
+ if (pci_one_device_iommu_support_va(dev) < 0)
+ return false;
+ iommu_dma_mask_check_done = 1;
+ }
}
}
return true;