diff mbox

[dpdk-dev,v2] net/i40e: add fdir nvgre parameters check

Message ID 20171222051105.53722-1-wei.zhao1@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Helin Zhang
Headers

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation success Compilation OK

Commit Message

Zhao1, Wei Dec. 22, 2017, 5:11 a.m. UTC 
  Add mask parameters check in nvgre parser for flow API.

Fixes: 30965ca341278 ("net/i40e: add NVGRE flow parsing")

Signed-off-by: Wei Zhao <wei.zhao1@intel.com>

---

V2:
-change c_k_s_rsvd0_ver mask check to 0xFFFF.
---
 drivers/net/i40e/i40e_flow.c | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)

Comments

Qi Zhang Dec. 22, 2017, 6:06 a.m. UTC | #1 
> -----Original Message-----
> From: Zhao1, Wei
> Sent: Friday, December 22, 2017 1:11 PM
> To: dev@dpdk.org
> Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Zhao1, Wei <wei.zhao1@intel.com>
> Subject: [PATCH v2] net/i40e: add fdir nvgre parameters check
> 
> Add mask parameters check in nvgre parser for flow API.
> 
> Fixes: 30965ca341278 ("net/i40e: add NVGRE flow parsing")
> 
> Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
> 
> ---
> 
> V2:
> -change c_k_s_rsvd0_ver mask check to 0xFFFF.
> ---
>  drivers/net/i40e/i40e_flow.c | 35 +++++++++++++++++++++++++++++++++++
>  1 file changed, 35 insertions(+)
> 
> diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c index
> 7e4936e..fa2e168 100644
> --- a/drivers/net/i40e/i40e_flow.c
> +++ b/drivers/net/i40e/i40e_flow.c
> @@ -3610,6 +3610,41 @@ i40e_flow_parse_nvgre_pattern(__rte_unused
> struct rte_eth_dev *dev,
>  						       "Invalid TNI mask");
>  					return -rte_errno;
>  				}
> +				if (nvgre_mask->protocol &&
> +					nvgre_mask->protocol != 0xFFFF) {
> +					rte_flow_error_set(error, EINVAL,
> +						RTE_FLOW_ERROR_TYPE_ITEM,
> +						item,
> +						"Invalid NVGRE item");
> +					return -rte_errno;
> +				}
> +				if (nvgre_mask->c_k_s_rsvd0_ver &&
> +					nvgre_mask->c_k_s_rsvd0_ver !=
> +					rte_cpu_to_be_16(0xFFFF)) {
> +					rte_flow_error_set(error, EINVAL,
> +						   RTE_FLOW_ERROR_TYPE_ITEM,
> +						   item,
> +						   "Invalid NVGRE item");
> +					return -rte_errno;
> +				}
> +				if (nvgre_spec->c_k_s_rsvd0_ver !=
> +					rte_cpu_to_be_16(0x2000) &&
> +					nvgre_mask->c_k_s_rsvd0_ver) {
> +					rte_flow_error_set(error, EINVAL,
> +						   RTE_FLOW_ERROR_TYPE_ITEM,
> +						   item,
> +						   "Invalid NVGRE item");
> +					return -rte_errno;
> +				}
> +				if (nvgre_mask->protocol &&
> +					nvgre_spec->protocol !=
> +					rte_cpu_to_be_16(0x6558)) {
> +					rte_flow_error_set(error, EINVAL,
> +						   RTE_FLOW_ERROR_TYPE_ITEM,
> +						   item,
> +						   "Invalid NVGRE item");
> +					return -rte_errno;
> +				}
>  				rte_memcpy(((uint8_t *)&tenant_id_be + 1),
>  					   nvgre_spec->tni, 3);
>  				filter->tenant_id =
> --
> 2.9.3

Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Zhang, Helin Jan. 8, 2018, 6:21 a.m. UTC | #2 
> -----Original Message-----
> From: dev [mailto:dev-bounces@dpdk.org] On Behalf Of Zhang, Qi Z
> Sent: Friday, December 22, 2017 2:06 PM
> To: Zhao1, Wei; dev@dpdk.org
> Subject: Re: [dpdk-dev] [PATCH v2] net/i40e: add fdir nvgre parameters check
> 
> 
> 
> > -----Original Message-----
> > From: Zhao1, Wei
> > Sent: Friday, December 22, 2017 1:11 PM
> > To: dev@dpdk.org
> > Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Zhao1, Wei <wei.zhao1@intel.com>
> > Subject: [PATCH v2] net/i40e: add fdir nvgre parameters check
> >
> > Add mask parameters check in nvgre parser for flow API.
> >
> > Fixes: 30965ca341278 ("net/i40e: add NVGRE flow parsing")
> >
> > Signed-off-by: Wei Zhao <wei.zhao1@intel.com>
> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
Applied to dpdk-next-net-intel, thanks!

/Helin
diff mbox

Patch

diff --git a/drivers/net/i40e/i40e_flow.c b/drivers/net/i40e/i40e_flow.c
index 7e4936e..fa2e168 100644
--- a/drivers/net/i40e/i40e_flow.c
+++ b/drivers/net/i40e/i40e_flow.c
@@ -3610,6 +3610,41 @@  i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
 						       "Invalid TNI mask");
 					return -rte_errno;
 				}
+				if (nvgre_mask->protocol &&
+					nvgre_mask->protocol != 0xFFFF) {
+					rte_flow_error_set(error, EINVAL,
+						RTE_FLOW_ERROR_TYPE_ITEM,
+						item,
+						"Invalid NVGRE item");
+					return -rte_errno;
+				}
+				if (nvgre_mask->c_k_s_rsvd0_ver &&
+					nvgre_mask->c_k_s_rsvd0_ver !=
+					rte_cpu_to_be_16(0xFFFF)) {
+					rte_flow_error_set(error, EINVAL,
+						   RTE_FLOW_ERROR_TYPE_ITEM,
+						   item,
+						   "Invalid NVGRE item");
+					return -rte_errno;
+				}
+				if (nvgre_spec->c_k_s_rsvd0_ver !=
+					rte_cpu_to_be_16(0x2000) &&
+					nvgre_mask->c_k_s_rsvd0_ver) {
+					rte_flow_error_set(error, EINVAL,
+						   RTE_FLOW_ERROR_TYPE_ITEM,
+						   item,
+						   "Invalid NVGRE item");
+					return -rte_errno;
+				}
+				if (nvgre_mask->protocol &&
+					nvgre_spec->protocol !=
+					rte_cpu_to_be_16(0x6558)) {
+					rte_flow_error_set(error, EINVAL,
+						   RTE_FLOW_ERROR_TYPE_ITEM,
+						   item,
+						   "Invalid NVGRE item");
+					return -rte_errno;
+				}
 				rte_memcpy(((uint8_t *)&tenant_id_be + 1),
 					   nvgre_spec->tni, 3);
 				filter->tenant_id =