[dpdk-dev,34/53] net/sfc/base: fix build issue with PHY LED control enabled
Checks
Commit Message
From: Vijay Srivastava <vijays@solarflare.com>
Fixed build issue with the EFSYS_OPT_PHY_LED_CONTROL for Huntigton and
Medford.
Fixes: b1d06c75e32c ("net/sfc/base: import PHY LEDs control")
Fixes: 0a7864349106 ("net/sfc/base: import PHY statistics")
Cc: stable@dpdk.org
Signed-off-by: Vijay Srivastava <vijays@solarflare.com>
Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
---
drivers/net/sfc/base/ef10_phy.c | 2 ++
drivers/net/sfc/base/efx_check.h | 4 ++--
drivers/net/sfc/base/siena_nic.c | 2 ++
drivers/net/sfc/base/siena_phy.c | 2 ++
4 files changed, 8 insertions(+), 2 deletions(-)
Comments
On 11/16/2017 12:04 AM, Andrew Rybchenko wrote:
> From: Vijay Srivastava <vijays@solarflare.com>
>
> Fixed build issue with the EFSYS_OPT_PHY_LED_CONTROL for Huntigton and
> Medford.
>
> Fixes: b1d06c75e32c ("net/sfc/base: import PHY LEDs control")
> Fixes: 0a7864349106 ("net/sfc/base: import PHY statistics")
> Cc: stable@dpdk.org
>
> Signed-off-by: Vijay Srivastava <vijays@solarflare.com>
> Signed-off-by: Andrew Rybchenko <arybchenko@solarflare.com>
Welcome Vijay!
@@ -280,7 +280,9 @@ ef10_phy_reconfigure(
uint8_t payload[MAX(MC_CMD_SET_LINK_IN_LEN,
MC_CMD_SET_LINK_OUT_LEN)];
uint32_t cap_mask;
+#if EFSYS_OPT_PHY_LED_CONTROL
unsigned int led_mode;
+#endif
unsigned int speed;
boolean_t supported;
efx_rc_t rc;
@@ -224,8 +224,8 @@
#if EFSYS_OPT_PHY_LED_CONTROL
/* Support for PHY LED control */
-# if !EFSYS_OPT_SIENA
-# error "PHY_LED_CONTROL requires SIENA"
+# if !(EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
+# error "PHY_LED_CONTROL requires SIENA or HUNTINGTON or MEDFORD"
# endif
#endif /* EFSYS_OPT_PHY_LED_CONTROL */
@@ -190,7 +190,9 @@ static __checkReturn efx_rc_t
siena_phy_cfg(
__in efx_nic_t *enp)
{
+#if EFSYS_OPT_PHY_STATS
efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
+#endif /* EFSYS_OPT_PHY_STATS */
efx_rc_t rc;
/* Fill out fields in enp->en_port and enp->en_nic_cfg from MCDI */
@@ -273,7 +273,9 @@ siena_phy_reconfigure(
MAX(MC_CMD_SET_LINK_IN_LEN,
MC_CMD_SET_LINK_OUT_LEN))];
uint32_t cap_mask;
+#if EFSYS_OPT_PHY_LED_CONTROL
unsigned int led_mode;
+#endif
unsigned int speed;
efx_rc_t rc;