[v4,13/14] baseband/acc: add PF configure companion function
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Commit Message
Add configure function notably to configure the device from
the PF within DPDK and bbdev-test (without external dependency).
Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
---
app/test-bbdev/test_bbdev_perf.c | 71 ++++++
drivers/baseband/acc/meson.build | 2 +-
drivers/baseband/acc/rte_acc200_cfg.h | 48 ++++
drivers/baseband/acc/rte_acc200_pmd.c | 453 ++++++++++++++++++++++++++++++++++
drivers/baseband/acc/version.map | 1 +
5 files changed, 574 insertions(+), 1 deletion(-)
create mode 100644 drivers/baseband/acc/rte_acc200_cfg.h
Comments
On 9/22/22 02:27, Nic Chautru wrote:
> Add configure function notably to configure the device from
> the PF within DPDK and bbdev-test (without external dependency).
>
> Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
> ---
> app/test-bbdev/test_bbdev_perf.c | 71 ++++++
> drivers/baseband/acc/meson.build | 2 +-
> drivers/baseband/acc/rte_acc200_cfg.h | 48 ++++
> drivers/baseband/acc/rte_acc200_pmd.c | 453 ++++++++++++++++++++++++++++++++++
> drivers/baseband/acc/version.map | 1 +
> 5 files changed, 574 insertions(+), 1 deletion(-)
> create mode 100644 drivers/baseband/acc/rte_acc200_cfg.h
>
> diff --git a/app/test-bbdev/test_bbdev_perf.c b/app/test-bbdev/test_bbdev_perf.c
> index 41c78de..ec6ee2a 100644
> --- a/app/test-bbdev/test_bbdev_perf.c
> +++ b/app/test-bbdev/test_bbdev_perf.c
> @@ -62,6 +62,15 @@
> #define ACC100_QMGR_INVALID_IDX -1
> #define ACC100_QMGR_RR 1
> #define ACC100_QOS_GBR 0
> +#include <rte_acc200_cfg.h>
> +#define ACC200PF_DRIVER_NAME ("intel_acc200_pf")
> +#define ACC200VF_DRIVER_NAME ("intel_acc200_vf")
> +#define ACC200_QMGR_NUM_AQS 16
> +#define ACC200_QMGR_NUM_QGS 2
> +#define ACC200_QMGR_AQ_DEPTH 5
> +#define ACC200_QMGR_INVALID_IDX -1
> +#define ACC200_QMGR_RR 1
> +#define ACC200_QOS_GBR 0
> #endif
>
> #define OPS_CACHE_SIZE 256U
> @@ -761,6 +770,68 @@ typedef int (test_case_function)(struct active_device *ad,
> "Failed to configure ACC100 PF for bbdev %s",
> info->dev_name);
> }
> + if ((get_init_device() == true) &&
> + (!strcmp(info->drv.driver_name, ACC200PF_DRIVER_NAME))) {
> + struct rte_acc_conf conf;
> + unsigned int i;
> +
> + printf("Configure ACC200 FEC Driver %s with default values\n",
> + info->drv.driver_name);
> +
> + /* clear default configuration before initialization */
> + memset(&conf, 0, sizeof(struct rte_acc_conf));
> +
> + /* Always set in PF mode for built-in configuration */
> + conf.pf_mode_en = true;
> + for (i = 0; i < RTE_ACC_NUM_VFS; ++i) {
> + conf.arb_dl_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
> + conf.arb_dl_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
> + conf.arb_dl_4g[i].round_robin_weight = ACC200_QMGR_RR;
> + conf.arb_ul_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
> + conf.arb_ul_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
> + conf.arb_ul_4g[i].round_robin_weight = ACC200_QMGR_RR;
> + conf.arb_dl_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
> + conf.arb_dl_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
> + conf.arb_dl_5g[i].round_robin_weight = ACC200_QMGR_RR;
> + conf.arb_ul_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
> + conf.arb_ul_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
> + conf.arb_ul_5g[i].round_robin_weight = ACC200_QMGR_RR;
> + conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;
> + conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;
> + conf.arb_fft[i].round_robin_weight = ACC200_QMGR_RR;
> + }
> +
> + conf.input_pos_llr_1_bit = true;
> + conf.output_pos_llr_1_bit = true;
> + conf.num_vf_bundles = 1; /**< Number of VF bundles to setup */
> +
> + conf.q_ul_4g.num_qgroups = ACC200_QMGR_NUM_QGS;
> + conf.q_ul_4g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
> + conf.q_ul_4g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
> + conf.q_ul_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
> + conf.q_dl_4g.num_qgroups = ACC200_QMGR_NUM_QGS;
> + conf.q_dl_4g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
> + conf.q_dl_4g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
> + conf.q_dl_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
> + conf.q_ul_5g.num_qgroups = ACC200_QMGR_NUM_QGS;
> + conf.q_ul_5g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
> + conf.q_ul_5g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
> + conf.q_ul_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
> + conf.q_dl_5g.num_qgroups = ACC200_QMGR_NUM_QGS;
> + conf.q_dl_5g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
> + conf.q_dl_5g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
> + conf.q_dl_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
> + conf.q_fft.num_qgroups = ACC200_QMGR_NUM_QGS;
> + conf.q_fft.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
> + conf.q_fft.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
> + conf.q_fft.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
> +
> + /* setup PF with configuration information */
> + ret = rte_acc200_configure(info->dev_name, &conf);
> + TEST_ASSERT_SUCCESS(ret,
> + "Failed to configure ACC200 PF for bbdev %s",
> + info->dev_name);
> + }
> #endif
> /* Let's refresh this now this is configured */
> rte_bbdev_info_get(dev_id, info);
> diff --git a/drivers/baseband/acc/meson.build b/drivers/baseband/acc/meson.build
> index 63912f0..7ae162a 100644
> --- a/drivers/baseband/acc/meson.build
> +++ b/drivers/baseband/acc/meson.build
> @@ -5,4 +5,4 @@ deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci']
>
> sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c')
>
> -headers = files('rte_acc100_cfg.h')
> +headers = files('rte_acc100_cfg.h', 'rte_acc200_cfg.h')
> diff --git a/drivers/baseband/acc/rte_acc200_cfg.h b/drivers/baseband/acc/rte_acc200_cfg.h
> new file mode 100644
> index 0000000..8bd9b20
> --- /dev/null
> +++ b/drivers/baseband/acc/rte_acc200_cfg.h
> @@ -0,0 +1,48 @@
> +/* SPDX-License-Identifier: BSD-3-Clause
> + * Copyright(c) 2022 Intel Corporation
> + */
> +
> +#ifndef _RTE_ACC200_CFG_H_
> +#define _RTE_ACC200_CFG_H_
> +
> +/**
> + * @file rte_acc200_cfg.h
> + *
> + * Functions for configuring ACC200 HW, exposed directly to applications.
> + * Configuration related to encoding/decoding is done through the
> + * librte_bbdev library.
> + *
> + * @warning
> + * @b EXPERIMENTAL: this API may change without prior notice
> + */
> +
> +#include <stdint.h>
> +#include <stdbool.h>
> +#include "rte_acc_common_cfg.h"
> +
> +#ifdef __cplusplus
> +extern "C" {
> +#endif
> +
> +/**
> + * Configure a ACC200 device
> + *
> + * @param dev_name
> + * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
> + * It can also be retrieved for a bbdev device from the dev_name field in the
> + * rte_bbdev_info structure returned by rte_bbdev_info_get().
> + * @param conf
> + * Configuration to apply to ACC200 HW.
> + *
> + * @return
> + * Zero on success, negative value on failure.
> + */
> +__rte_experimental
> +int
> +rte_acc200_configure(const char *dev_name, struct rte_acc_conf *conf);
> +
> +#ifdef __cplusplus
> +}
> +#endif
> +
> +#endif /* _RTE_ACC200_CFG_H_ */
> diff --git a/drivers/baseband/acc/rte_acc200_pmd.c b/drivers/baseband/acc/rte_acc200_pmd.c
> index 3c2931b..21d614d 100644
> --- a/drivers/baseband/acc/rte_acc200_pmd.c
> +++ b/drivers/baseband/acc/rte_acc200_pmd.c
> @@ -43,6 +43,27 @@
>
> enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, NUM_ACC};
>
> +/* Return the accelerator enum for a Queue Group Index */
> +static inline int
> +accFromQgid(int qg_idx, const struct rte_acc_conf *acc_conf)
> +{
> + int accQg[ACC200_NUM_QGRPS];
> + int NumQGroupsPerFn[NUM_ACC];
> + int acc, qgIdx, qgIndex = 0;
> + for (qgIdx = 0; qgIdx < ACC200_NUM_QGRPS; qgIdx++)
> + accQg[qgIdx] = 0;
> + NumQGroupsPerFn[UL_4G] = acc_conf->q_ul_4g.num_qgroups;
> + NumQGroupsPerFn[UL_5G] = acc_conf->q_ul_5g.num_qgroups;
> + NumQGroupsPerFn[DL_4G] = acc_conf->q_dl_4g.num_qgroups;
> + NumQGroupsPerFn[DL_5G] = acc_conf->q_dl_5g.num_qgroups;
> + NumQGroupsPerFn[FFT] = acc_conf->q_fft.num_qgroups;
> + for (acc = UL_4G; acc < NUM_ACC; acc++)
> + for (qgIdx = 0; qgIdx < NumQGroupsPerFn[acc]; qgIdx++)
> + accQg[qgIndex++] = acc;
> + acc = accQg[qg_idx];
> + return acc;
> +}
> +
> /* Return the queue topology for a Queue Group Index */
> static inline void
> qtopFromAcc(struct rte_acc_queue_topology **qtop, int acc_enum,
> @@ -75,6 +96,30 @@
> *qtop = p_qtop;
> }
>
> +/* Return the AQ depth for a Queue Group Index */
> +static inline int
> +aqDepth(int qg_idx, struct rte_acc_conf *acc_conf)
> +{
> + struct rte_acc_queue_topology *q_top = NULL;
> + int acc_enum = accFromQgid(qg_idx, acc_conf);
> + qtopFromAcc(&q_top, acc_enum, acc_conf);
> + if (unlikely(q_top == NULL))
> + return 0;
> + return q_top->aq_depth_log2;
> +}
> +
> +/* Return the AQ depth for a Queue Group Index */
> +static inline int
> +aqNum(int qg_idx, struct rte_acc_conf *acc_conf)
> +{
> + struct rte_acc_queue_topology *q_top = NULL;
> + int acc_enum = accFromQgid(qg_idx, acc_conf);
> + qtopFromAcc(&q_top, acc_enum, acc_conf);
> + if (unlikely(q_top == NULL))
> + return 0;
> + return q_top->num_aqs_per_groups;
> +}
For the 3 functions above, please add new lines for clarity.
> +
> static void
> initQTop(struct rte_acc_conf *acc_conf)
> {
> @@ -3740,3 +3785,411 @@ static int acc200_pci_probe(struct rte_pci_driver *pci_drv,
> RTE_PMD_REGISTER_PCI_TABLE(ACC200PF_DRIVER_NAME, pci_id_acc200_pf_map);
> RTE_PMD_REGISTER_PCI(ACC200VF_DRIVER_NAME, acc200_pci_vf_driver);
> RTE_PMD_REGISTER_PCI_TABLE(ACC200VF_DRIVER_NAME, pci_id_acc200_vf_map);
> +
> +/* Initial configuration of a ACC200 device prior to running configure() */
> +int
> +rte_acc200_configure(const char *dev_name, struct rte_acc_conf *conf)
> +{
> + rte_bbdev_log(INFO, "rte_acc200_configure");
> + uint32_t value, address, status;
> + int qg_idx, template_idx, vf_idx, acc, i;
> + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> +
> + /* Compile time checks */
> + RTE_BUILD_BUG_ON(sizeof(struct acc_dma_req_desc) != 256);
> + RTE_BUILD_BUG_ON(sizeof(union acc_dma_desc) != 256);
> + RTE_BUILD_BUG_ON(sizeof(struct acc_fcw_td) != 24);
> + RTE_BUILD_BUG_ON(sizeof(struct acc_fcw_te) != 32);
> +
> + if (bbdev == NULL) {
> + rte_bbdev_log(ERR,
> + "Invalid dev_name (%s), or device is not yet initialised",
> + dev_name);
> + return -ENODEV;
> + }
> + struct acc_device *d = bbdev->data->dev_private;
> +
> + /* Store configuration */
> + rte_memcpy(&d->acc_conf, conf, sizeof(d->acc_conf));
> +
> +
> + /* Check we are already out of PG */
> + status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
> + if (status > 0) {
> + if (status != ACC200_PG_MASK_0) {
> + rte_bbdev_log(ERR, "Unexpected status %x %x",
> + status, ACC200_PG_MASK_0);
> + return -ENODEV;
> + }
> + /* Clock gate sections that will be un-PG */
> + acc_reg_write(d, HWPfHiClkGateHystReg, ACC200_CLK_DIS);
> + /* Un-PG required sections */
> + acc_reg_write(d, HWPfHiSectionPowerGatingReq,
> + ACC200_PG_MASK_1);
> + status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
> + if (status != ACC200_PG_MASK_1) {
> + rte_bbdev_log(ERR, "Unexpected status %x %x",
> + status, ACC200_PG_MASK_1);
> + return -ENODEV;
> + }
> + acc_reg_write(d, HWPfHiSectionPowerGatingReq,
> + ACC200_PG_MASK_2);
> + status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
> + if (status != ACC200_PG_MASK_2) {
> + rte_bbdev_log(ERR, "Unexpected status %x %x",
> + status, ACC200_PG_MASK_2);
> + return -ENODEV;
> + }
> + acc_reg_write(d, HWPfHiSectionPowerGatingReq,
> + ACC200_PG_MASK_3);
> + status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
> + if (status != ACC200_PG_MASK_3) {
> + rte_bbdev_log(ERR, "Unexpected status %x %x",
> + status, ACC200_PG_MASK_3);
> + return -ENODEV;
> + }
> + /* Enable clocks for all sections */
> + acc_reg_write(d, HWPfHiClkGateHystReg, ACC200_CLK_EN);
> + }
> +
> + /* Explicitly releasing AXI as this may be stopped after PF FLR/BME */
> + address = HWPfDmaAxiControl;
> + value = 1;
> + acc_reg_write(d, address, value);
> +
> + /* Set the fabric mode */
> + address = HWPfFabricM2iBufferReg;
> + value = ACC200_FABRIC_MODE;
> + acc_reg_write(d, address, value);
> +
> + /* Set default descriptor signature */
> + address = HWPfDmaDescriptorSignatuture;
> + value = 0;
> + acc_reg_write(d, address, value);
> +
> + /* Enable the Error Detection in DMA */
> + value = ACC200_CFG_DMA_ERROR;
> + address = HWPfDmaErrorDetectionEn;
> + acc_reg_write(d, address, value);
> +
> + /* AXI Cache configuration */
> + value = ACC200_CFG_AXI_CACHE;
> + address = HWPfDmaAxcacheReg;
> + acc_reg_write(d, address, value);
> +
> + /* Default DMA Configuration (Qmgr Enabled) */
> + address = HWPfDmaConfig0Reg;
> + value = 0;
> + acc_reg_write(d, address, value);
> + address = HWPfDmaQmanen;
> + value = 0;
> + acc_reg_write(d, address, value);
> +
> + /* Default RLIM/ALEN configuration */
> + int rlim = 0;
> + int alen = 1;
> + int timestamp = 0;
> + address = HWPfDmaConfig1Reg;
> + value = (1 << 31) + (rlim << 8) + (timestamp << 6) + alen;
> + acc_reg_write(d, address, value);
> +
> + /* Default FFT configuration */
> + address = HWPfFftConfig0;
> + value = ACC200_FFT_CFG_0;
> + acc_reg_write(d, address, value);
> +
> + /* Configure DMA Qmanager addresses */
> + address = HWPfDmaQmgrAddrReg;
> + value = HWPfQmgrEgressQueuesTemplate;
> + acc_reg_write(d, address, value);
> +
> + /* ===== Qmgr Configuration ===== */
> + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
> + int totalQgs = conf->q_ul_4g.num_qgroups +
> + conf->q_ul_5g.num_qgroups +
> + conf->q_dl_4g.num_qgroups +
> + conf->q_dl_5g.num_qgroups +
> + conf->q_fft.num_qgroups;
> + for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {
> + address = HWPfQmgrDepthLog2Grp +
> + ACC_BYTES_IN_WORD * qg_idx;
> + value = aqDepth(qg_idx, conf);
> + acc_reg_write(d, address, value);
> + address = HWPfQmgrTholdGrp +
> + ACC_BYTES_IN_WORD * qg_idx;
> + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
> + acc_reg_write(d, address, value);
> + }
> +
> + /* Template Priority in incremental order */
> + for (template_idx = 0; template_idx < ACC_NUM_TMPL;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg0Indx + ACC_BYTES_IN_WORD * template_idx;
> + value = ACC_TMPL_PRI_0;
> + acc_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg1Indx + ACC_BYTES_IN_WORD * template_idx;
> + value = ACC_TMPL_PRI_1;
> + acc_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg2indx + ACC_BYTES_IN_WORD * template_idx;
> + value = ACC_TMPL_PRI_2;
> + acc_reg_write(d, address, value);
> + address = HWPfQmgrGrpTmplateReg3Indx + ACC_BYTES_IN_WORD * template_idx;
> + value = ACC_TMPL_PRI_3;
> + acc_reg_write(d, address, value);
> + }
> +
> + address = HWPfQmgrGrpPriority;
> + value = ACC200_CFG_QMGR_HI_P;
> + acc_reg_write(d, address, value);
> +
> + /* Template Configuration */
> + for (template_idx = 0; template_idx < ACC_NUM_TMPL;
> + template_idx++) {
> + value = 0;
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC_BYTES_IN_WORD * template_idx;
> + acc_reg_write(d, address, value);
> + }
> + /* 4GUL */
> + int numQgs = conf->q_ul_4g.num_qgroups;
> + int numQqsAcc = 0;
Don't mix declarations & code, here and elsewhere in this function.
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC200_SIG_UL_4G;
> + template_idx <= ACC200_SIG_UL_4G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC_BYTES_IN_WORD * template_idx;
> + acc_reg_write(d, address, value);
> + }
> + /* 5GUL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_ul_5g.num_qgroups;
> + value = 0;
> + int numEngines = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC200_SIG_UL_5G;
> + template_idx <= ACC200_SIG_UL_5G_LAST;
> + template_idx++) {
> + /* Check engine power-on status */
> + address = HwPfFecUl5gIbDebugReg + ACC_ENGINE_OFFSET * template_idx;
> + status = (acc_reg_read(d, address) >> 4) & 0x7;
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC_BYTES_IN_WORD * template_idx;
> + if (status == 1) {
> + acc_reg_write(d, address, value);
> + numEngines++;
> + } else
> + acc_reg_write(d, address, 0);
> + }
> + printf("Number of 5GUL engines %d\n", numEngines);
> + /* 4GDL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_dl_4g.num_qgroups;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC200_SIG_DL_4G;
> + template_idx <= ACC200_SIG_DL_4G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC_BYTES_IN_WORD * template_idx;
> + acc_reg_write(d, address, value);
> + }
> + /* 5GDL */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_dl_5g.num_qgroups;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC200_SIG_DL_5G;
> + template_idx <= ACC200_SIG_DL_5G_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC_BYTES_IN_WORD * template_idx;
> + acc_reg_write(d, address, value);
> + }
> + /* FFT */
> + numQqsAcc += numQgs;
> + numQgs = conf->q_fft.num_qgroups;
> + value = 0;
> + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
> + value |= (1 << qg_idx);
> + for (template_idx = ACC200_SIG_FFT;
> + template_idx <= ACC200_SIG_FFT_LAST;
> + template_idx++) {
> + address = HWPfQmgrGrpTmplateReg4Indx
> + + ACC_BYTES_IN_WORD * template_idx;
> + acc_reg_write(d, address, value);
> + }
> +
> + /* Queue Group Function mapping */
> + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
> + value = 0;
> + for (qg_idx = 0; qg_idx < ACC_NUM_QGRPS_PER_WORD; qg_idx++) {
> + acc = accFromQgid(qg_idx, conf);
> + value |= qman_func_id[acc] << (qg_idx * 4);
> + }
> + acc_reg_write(d, HWPfQmgrGrpFunction0, value);
> + value = 0;
> + for (qg_idx = 0; qg_idx < ACC_NUM_QGRPS_PER_WORD; qg_idx++) {
> + acc = accFromQgid(qg_idx + ACC_NUM_QGRPS_PER_WORD, conf);
> + value |= qman_func_id[acc] << (qg_idx * 4);
> + }
> + acc_reg_write(d, HWPfQmgrGrpFunction1, value);
> +
> + /* Configuration of the Arbitration QGroup depth to 1 */
> + for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {
> + address = HWPfQmgrArbQDepthGrp +
> + ACC_BYTES_IN_WORD * qg_idx;
> + value = 0;
> + acc_reg_write(d, address, value);
> + }
> +
> + /* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */
> + uint32_t aram_address = 0;
> + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> + address = HWPfQmgrVfBaseAddr + vf_idx
> + * ACC_BYTES_IN_WORD + qg_idx
> + * ACC_BYTES_IN_WORD * 64;
> + value = aram_address;
> + acc_reg_write(d, address, value);
> + /* Offset ARAM Address for next memory bank
> + * - increment of 4B
> + */
> + aram_address += aqNum(qg_idx, conf) *
> + (1 << aqDepth(qg_idx, conf));
> + }
> + }
> +
> + if (aram_address > ACC200_WORDS_IN_ARAM_SIZE) {
> + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
> + aram_address, ACC200_WORDS_IN_ARAM_SIZE);
> + return -EINVAL;
> + }
> +
> + /* Performance tuning */
> + acc_reg_write(d, HWPfFabricI2Mdma_weight, 0x0FFF);
> + acc_reg_write(d, HWPfDma4gdlIbThld, 0x1f10);
> +
> + /* ==== HI Configuration ==== */
> +
> + /* No Info Ring/MSI by default */
> + address = HWPfHiInfoRingIntWrEnRegPf;
> + value = 0;
> + acc_reg_write(d, address, value);
> + address = HWPfHiCfgMsiIntWrEnRegPf;
> + value = 0xFFFFFFFF;
> + acc_reg_write(d, address, value);
> + /* Prevent Block on Transmit Error */
> + address = HWPfHiBlockTransmitOnErrorEn;
> + value = 0;
> + acc_reg_write(d, address, value);
> + /* Prevents to drop MSI */
> + address = HWPfHiMsiDropEnableReg;
> + value = 0;
> + acc_reg_write(d, address, value);
> + /* Set the PF Mode register */
> + address = HWPfHiPfMode;
> + value = (conf->pf_mode_en) ? ACC_PF_VAL : 0;
> + acc_reg_write(d, address, value);
> +
> + /* QoS overflow init */
> + value = 1;
> + address = HWPfQosmonAEvalOverflow0;
> + acc_reg_write(d, address, value);
> + address = HWPfQosmonBEvalOverflow0;
> + acc_reg_write(d, address, value);
> +
> + /* Configure the FFT RAM LUT */
> + uint32_t fft_lut[ACC200_FFT_RAM_SIZE] = {
> + 0x1FFFF, 0x1FFFF, 0x1FFFE, 0x1FFFA, 0x1FFF6, 0x1FFF1, 0x1FFEA, 0x1FFE2,
> + 0x1FFD9, 0x1FFCE, 0x1FFC2, 0x1FFB5, 0x1FFA7, 0x1FF98, 0x1FF87, 0x1FF75,
> + 0x1FF62, 0x1FF4E, 0x1FF38, 0x1FF21, 0x1FF09, 0x1FEF0, 0x1FED6, 0x1FEBA,
> + 0x1FE9D, 0x1FE7F, 0x1FE5F, 0x1FE3F, 0x1FE1D, 0x1FDFA, 0x1FDD5, 0x1FDB0,
> + 0x1FD89, 0x1FD61, 0x1FD38, 0x1FD0D, 0x1FCE1, 0x1FCB4, 0x1FC86, 0x1FC57,
> + 0x1FC26, 0x1FBF4, 0x1FBC1, 0x1FB8D, 0x1FB58, 0x1FB21, 0x1FAE9, 0x1FAB0,
> + 0x1FA75, 0x1FA3A, 0x1F9FD, 0x1F9BF, 0x1F980, 0x1F93F, 0x1F8FD, 0x1F8BA,
> + 0x1F876, 0x1F831, 0x1F7EA, 0x1F7A3, 0x1F75A, 0x1F70F, 0x1F6C4, 0x1F677,
> + 0x1F629, 0x1F5DA, 0x1F58A, 0x1F539, 0x1F4E6, 0x1F492, 0x1F43D, 0x1F3E7,
> + 0x1F38F, 0x1F337, 0x1F2DD, 0x1F281, 0x1F225, 0x1F1C8, 0x1F169, 0x1F109,
> + 0x1F0A8, 0x1F046, 0x1EFE2, 0x1EF7D, 0x1EF18, 0x1EEB0, 0x1EE48, 0x1EDDF,
> + 0x1ED74, 0x1ED08, 0x1EC9B, 0x1EC2D, 0x1EBBE, 0x1EB4D, 0x1EADB, 0x1EA68,
> + 0x1E9F4, 0x1E97F, 0x1E908, 0x1E891, 0x1E818, 0x1E79E, 0x1E722, 0x1E6A6,
> + 0x1E629, 0x1E5AA, 0x1E52A, 0x1E4A9, 0x1E427, 0x1E3A3, 0x1E31F, 0x1E299,
> + 0x1E212, 0x1E18A, 0x1E101, 0x1E076, 0x1DFEB, 0x1DF5E, 0x1dED0, 0x1DE41,
> + 0x1DDB1, 0x1DD20, 0x1DC8D, 0x1DBFA, 0x1DB65, 0x1DACF, 0x1DA38, 0x1D9A0,
> + 0x1D907, 0x1D86C, 0x1D7D1, 0x1D734, 0x1D696, 0x1D5F7, 0x1D557, 0x1D4B6,
> + 0x1D413, 0x1D370, 0x1D2CB, 0x1D225, 0x1D17E, 0x1D0D6, 0x1D02D, 0x1CF83,
> + 0x1CED8, 0x1CE2B, 0x1CD7E, 0x1CCCF, 0x1CC1F, 0x1CB6E, 0x1CABC, 0x1CA09,
> + 0x1C955, 0x1C89F, 0x1C7E9, 0x1C731, 0x1C679, 0x1C5BF, 0x1C504, 0x1C448,
> + 0x1C38B, 0x1C2CD, 0x1C20E, 0x1C14E, 0x1C08C, 0x1BFCA, 0x1BF06, 0x1BE42,
> + 0x1BD7C, 0x1BCB5, 0x1BBED, 0x1BB25, 0x1BA5B, 0x1B990, 0x1B8C4, 0x1B7F6,
> + 0x1B728, 0x1B659, 0x1B589, 0x1B4B7, 0x1B3E5, 0x1B311, 0x1B23D, 0x1B167,
> + 0x1B091, 0x1AFB9, 0x1AEE0, 0x1AE07, 0x1AD2C, 0x1AC50, 0x1AB73, 0x1AA95,
> + 0x1A9B6, 0x1A8D6, 0x1A7F6, 0x1A714, 0x1A631, 0x1A54D, 0x1A468, 0x1A382,
> + 0x1A29A, 0x1A1B2, 0x1A0C9, 0x19FDF, 0x19EF4, 0x19E08, 0x19D1B, 0x19C2D,
> + 0x19B3E, 0x19A4E, 0x1995D, 0x1986B, 0x19778, 0x19684, 0x1958F, 0x19499,
> + 0x193A2, 0x192AA, 0x191B1, 0x190B8, 0x18FBD, 0x18EC1, 0x18DC4, 0x18CC7,
> + 0x18BC8, 0x18AC8, 0x189C8, 0x188C6, 0x187C4, 0x186C1, 0x185BC, 0x184B7,
> + 0x183B1, 0x182AA, 0x181A2, 0x18099, 0x17F8F, 0x17E84, 0x17D78, 0x17C6C,
> + 0x17B5E, 0x17A4F, 0x17940, 0x17830, 0x1771E, 0x1760C, 0x174F9, 0x173E5,
> + 0x172D1, 0x171BB, 0x170A4, 0x16F8D, 0x16E74, 0x16D5B, 0x16C41, 0x16B26,
> + 0x16A0A, 0x168ED, 0x167CF, 0x166B1, 0x16592, 0x16471, 0x16350, 0x1622E,
> + 0x1610B, 0x15FE8, 0x15EC3, 0x15D9E, 0x15C78, 0x15B51, 0x15A29, 0x15900,
> + 0x157D7, 0x156AC, 0x15581, 0x15455, 0x15328, 0x151FB, 0x150CC, 0x14F9D,
> + 0x14E6D, 0x14D3C, 0x14C0A, 0x14AD8, 0x149A4, 0x14870, 0x1473B, 0x14606,
> + 0x144CF, 0x14398, 0x14260, 0x14127, 0x13FEE, 0x13EB3, 0x13D78, 0x13C3C,
> + 0x13B00, 0x139C2, 0x13884, 0x13745, 0x13606, 0x134C5, 0x13384, 0x13242,
> + 0x130FF, 0x12FBC, 0x12E78, 0x12D33, 0x12BEE, 0x12AA7, 0x12960, 0x12819,
> + 0x126D0, 0x12587, 0x1243D, 0x122F3, 0x121A8, 0x1205C, 0x11F0F, 0x11DC2,
> + 0x11C74, 0x11B25, 0x119D6, 0x11886, 0x11735, 0x115E3, 0x11491, 0x1133F,
> + 0x111EB, 0x11097, 0x10F42, 0x10dED, 0x10C97, 0x10B40, 0x109E9, 0x10891,
> + 0x10738, 0x105DF, 0x10485, 0x1032B, 0x101D0, 0x10074, 0x0FF18, 0x0FDBB,
> + 0x0FC5D, 0x0FAFF, 0x0F9A0, 0x0F841, 0x0F6E1, 0x0F580, 0x0F41F, 0x0F2BD,
> + 0x0F15B, 0x0EFF8, 0x0EE94, 0x0ED30, 0x0EBCC, 0x0EA67, 0x0E901, 0x0E79A,
> + 0x0E633, 0x0E4CC, 0x0E364, 0x0E1FB, 0x0E092, 0x0DF29, 0x0DDBE, 0x0DC54,
> + 0x0DAE9, 0x0D97D, 0x0D810, 0x0D6A4, 0x0D536, 0x0D3C8, 0x0D25A, 0x0D0EB,
> + 0x0CF7C, 0x0CE0C, 0x0CC9C, 0x0CB2B, 0x0C9B9, 0x0C847, 0x0C6D5, 0x0C562,
> + 0x0C3EF, 0x0C27B, 0x0C107, 0x0BF92, 0x0BE1D, 0x0BCA8, 0x0BB32, 0x0B9BB,
> + 0x0B844, 0x0B6CD, 0x0B555, 0x0B3DD, 0x0B264, 0x0B0EB, 0x0AF71, 0x0ADF7,
> + 0x0AC7D, 0x0AB02, 0x0A987, 0x0A80B, 0x0A68F, 0x0A513, 0x0A396, 0x0A219,
> + 0x0A09B, 0x09F1D, 0x09D9E, 0x09C20, 0x09AA1, 0x09921, 0x097A1, 0x09621,
> + 0x094A0, 0x0931F, 0x0919E, 0x0901C, 0x08E9A, 0x08D18, 0x08B95, 0x08A12,
> + 0x0888F, 0x0870B, 0x08587, 0x08402, 0x0827E, 0x080F9, 0x07F73, 0x07DEE,
> + 0x07C68, 0x07AE2, 0x0795B, 0x077D4, 0x0764D, 0x074C6, 0x0733E, 0x071B6,
> + 0x0702E, 0x06EA6, 0x06D1D, 0x06B94, 0x06A0B, 0x06881, 0x066F7, 0x0656D,
> + 0x063E3, 0x06258, 0x060CE, 0x05F43, 0x05DB7, 0x05C2C, 0x05AA0, 0x05914,
> + 0x05788, 0x055FC, 0x0546F, 0x052E3, 0x05156, 0x04FC9, 0x04E3B, 0x04CAE,
> + 0x04B20, 0x04992, 0x04804, 0x04676, 0x044E8, 0x04359, 0x041CB, 0x0403C,
> + 0x03EAD, 0x03D1D, 0x03B8E, 0x039FF, 0x0386F, 0x036DF, 0x0354F, 0x033BF,
> + 0x0322F, 0x0309F, 0x02F0F, 0x02D7E, 0x02BEE, 0x02A5D, 0x028CC, 0x0273B,
> + 0x025AA, 0x02419, 0x02288, 0x020F7, 0x01F65, 0x01DD4, 0x01C43, 0x01AB1,
> + 0x0191F, 0x0178E, 0x015FC, 0x0146A, 0x012D8, 0x01147, 0x00FB5, 0x00E23,
> + 0x00C91, 0x00AFF, 0x0096D, 0x007DB, 0x00648, 0x004B6, 0x00324, 0x00192};
> +
> + acc_reg_write(d, HWPfFftRamPageAccess, ACC200_FFT_RAM_EN + 64);
> + for (i = 0; i < ACC200_FFT_RAM_SIZE; i++)
> + acc_reg_write(d, HWPfFftRamOff + i * 4, fft_lut[i]);
> + acc_reg_write(d, HWPfFftRamPageAccess, ACC200_FFT_RAM_DIS);
> +
> + /* Enabling AQueues through the Queue hierarchy*/
> + for (vf_idx = 0; vf_idx < ACC200_NUM_VFS; vf_idx++) {
> + for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {
> + value = 0;
> + if (vf_idx < conf->num_vf_bundles &&
> + qg_idx < totalQgs)
> + value = (1 << aqNum(qg_idx, conf)) - 1;
> + address = HWPfQmgrAqEnableVf
> + + vf_idx * ACC_BYTES_IN_WORD;
> + value += (qg_idx << 16);
> + acc_reg_write(d, address, value);
> + }
> + }
> +
> + rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
> + return 0;
> +}
> diff --git a/drivers/baseband/acc/version.map b/drivers/baseband/acc/version.map
> index b4ff13e..27fbbe3 100644
> --- a/drivers/baseband/acc/version.map
> +++ b/drivers/baseband/acc/version.map
> @@ -6,4 +6,5 @@ EXPERIMENTAL {
> global:
>
> rte_acc10x_configure;
> + rte_acc200_configure;
> };
Hi Maxime,
Thanks will send an updated serie now. Much appreciated.
> -----Original Message-----
> From: Maxime Coquelin <maxime.coquelin@redhat.com>
> Sent: Friday, September 23, 2022 2:26 AM
> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
> thomas@monjalon.net
> Cc: trix@redhat.com; mdr@ashroe.eu; Richardson, Bruce
> <bruce.richardson@intel.com>; hemant.agrawal@nxp.com;
> david.marchand@redhat.com; stephen@networkplumber.org; Vargas,
> Hernan <hernan.vargas@intel.com>
> Subject: Re: [PATCH v4 13/14] baseband/acc: add PF configure companion
> function
>
>
>
> On 9/22/22 02:27, Nic Chautru wrote:
> > Add configure function notably to configure the device from the PF
> > within DPDK and bbdev-test (without external dependency).
> >
> > Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
> > ---
> > app/test-bbdev/test_bbdev_perf.c | 71 ++++++
> > drivers/baseband/acc/meson.build | 2 +-
> > drivers/baseband/acc/rte_acc200_cfg.h | 48 ++++
> > drivers/baseband/acc/rte_acc200_pmd.c | 453
> ++++++++++++++++++++++++++++++++++
> > drivers/baseband/acc/version.map | 1 +
> > 5 files changed, 574 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/baseband/acc/rte_acc200_cfg.h
> >
> > diff --git a/app/test-bbdev/test_bbdev_perf.c
> > b/app/test-bbdev/test_bbdev_perf.c
> > index 41c78de..ec6ee2a 100644
> > --- a/app/test-bbdev/test_bbdev_perf.c
> > +++ b/app/test-bbdev/test_bbdev_perf.c
> > @@ -62,6 +62,15 @@
> > #define ACC100_QMGR_INVALID_IDX -1
> > #define ACC100_QMGR_RR 1
> > #define ACC100_QOS_GBR 0
> > +#include <rte_acc200_cfg.h>
> > +#define ACC200PF_DRIVER_NAME ("intel_acc200_pf")
> > +#define ACC200VF_DRIVER_NAME ("intel_acc200_vf")
> > +#define ACC200_QMGR_NUM_AQS 16
> > +#define ACC200_QMGR_NUM_QGS 2
> > +#define ACC200_QMGR_AQ_DEPTH 5
> > +#define ACC200_QMGR_INVALID_IDX -1
> > +#define ACC200_QMGR_RR 1
> > +#define ACC200_QOS_GBR 0
> > #endif
> >
> > #define OPS_CACHE_SIZE 256U
> > @@ -761,6 +770,68 @@ typedef int (test_case_function)(struct
> active_device *ad,
> > "Failed to configure ACC100 PF for bbdev
> %s",
> > info->dev_name);
> > }
> > + if ((get_init_device() == true) &&
> > + (!strcmp(info->drv.driver_name, ACC200PF_DRIVER_NAME)))
> {
> > + struct rte_acc_conf conf;
> > + unsigned int i;
> > +
> > + printf("Configure ACC200 FEC Driver %s with default
> values\n",
> > + info->drv.driver_name);
> > +
> > + /* clear default configuration before initialization */
> > + memset(&conf, 0, sizeof(struct rte_acc_conf));
> > +
> > + /* Always set in PF mode for built-in configuration */
> > + conf.pf_mode_en = true;
> > + for (i = 0; i < RTE_ACC_NUM_VFS; ++i) {
> > + conf.arb_dl_4g[i].gbr_threshold1 =
> ACC200_QOS_GBR;
> > + conf.arb_dl_4g[i].gbr_threshold1 =
> ACC200_QOS_GBR;
> > + conf.arb_dl_4g[i].round_robin_weight =
> ACC200_QMGR_RR;
> > + conf.arb_ul_4g[i].gbr_threshold1 =
> ACC200_QOS_GBR;
> > + conf.arb_ul_4g[i].gbr_threshold1 =
> ACC200_QOS_GBR;
> > + conf.arb_ul_4g[i].round_robin_weight =
> ACC200_QMGR_RR;
> > + conf.arb_dl_5g[i].gbr_threshold1 =
> ACC200_QOS_GBR;
> > + conf.arb_dl_5g[i].gbr_threshold1 =
> ACC200_QOS_GBR;
> > + conf.arb_dl_5g[i].round_robin_weight =
> ACC200_QMGR_RR;
> > + conf.arb_ul_5g[i].gbr_threshold1 =
> ACC200_QOS_GBR;
> > + conf.arb_ul_5g[i].gbr_threshold1 =
> ACC200_QOS_GBR;
> > + conf.arb_ul_5g[i].round_robin_weight =
> ACC200_QMGR_RR;
> > + conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;
> > + conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;
> > + conf.arb_fft[i].round_robin_weight =
> ACC200_QMGR_RR;
> > + }
> > +
> > + conf.input_pos_llr_1_bit = true;
> > + conf.output_pos_llr_1_bit = true;
> > + conf.num_vf_bundles = 1; /**< Number of VF bundles to
> setup */
> > +
> > + conf.q_ul_4g.num_qgroups = ACC200_QMGR_NUM_QGS;
> > + conf.q_ul_4g.first_qgroup_index =
> ACC200_QMGR_INVALID_IDX;
> > + conf.q_ul_4g.num_aqs_per_groups =
> ACC200_QMGR_NUM_AQS;
> > + conf.q_ul_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
> > + conf.q_dl_4g.num_qgroups = ACC200_QMGR_NUM_QGS;
> > + conf.q_dl_4g.first_qgroup_index =
> ACC200_QMGR_INVALID_IDX;
> > + conf.q_dl_4g.num_aqs_per_groups =
> ACC200_QMGR_NUM_AQS;
> > + conf.q_dl_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
> > + conf.q_ul_5g.num_qgroups = ACC200_QMGR_NUM_QGS;
> > + conf.q_ul_5g.first_qgroup_index =
> ACC200_QMGR_INVALID_IDX;
> > + conf.q_ul_5g.num_aqs_per_groups =
> ACC200_QMGR_NUM_AQS;
> > + conf.q_ul_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
> > + conf.q_dl_5g.num_qgroups = ACC200_QMGR_NUM_QGS;
> > + conf.q_dl_5g.first_qgroup_index =
> ACC200_QMGR_INVALID_IDX;
> > + conf.q_dl_5g.num_aqs_per_groups =
> ACC200_QMGR_NUM_AQS;
> > + conf.q_dl_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
> > + conf.q_fft.num_qgroups = ACC200_QMGR_NUM_QGS;
> > + conf.q_fft.first_qgroup_index =
> ACC200_QMGR_INVALID_IDX;
> > + conf.q_fft.num_aqs_per_groups =
> ACC200_QMGR_NUM_AQS;
> > + conf.q_fft.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
> > +
> > + /* setup PF with configuration information */
> > + ret = rte_acc200_configure(info->dev_name, &conf);
> > + TEST_ASSERT_SUCCESS(ret,
> > + "Failed to configure ACC200 PF for bbdev
> %s",
> > + info->dev_name);
> > + }
> > #endif
> > /* Let's refresh this now this is configured */
> > rte_bbdev_info_get(dev_id, info);
> > diff --git a/drivers/baseband/acc/meson.build
> > b/drivers/baseband/acc/meson.build
> > index 63912f0..7ae162a 100644
> > --- a/drivers/baseband/acc/meson.build
> > +++ b/drivers/baseband/acc/meson.build
> > @@ -5,4 +5,4 @@ deps += ['bbdev', 'bus_vdev', 'ring', 'pci',
> > 'bus_pci']
> >
> > sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c')
> >
> > -headers = files('rte_acc100_cfg.h')
> > +headers = files('rte_acc100_cfg.h', 'rte_acc200_cfg.h')
> > diff --git a/drivers/baseband/acc/rte_acc200_cfg.h
> > b/drivers/baseband/acc/rte_acc200_cfg.h
> > new file mode 100644
> > index 0000000..8bd9b20
> > --- /dev/null
> > +++ b/drivers/baseband/acc/rte_acc200_cfg.h
> > @@ -0,0 +1,48 @@
> > +/* SPDX-License-Identifier: BSD-3-Clause
> > + * Copyright(c) 2022 Intel Corporation */
> > +
> > +#ifndef _RTE_ACC200_CFG_H_
> > +#define _RTE_ACC200_CFG_H_
> > +
> > +/**
> > + * @file rte_acc200_cfg.h
> > + *
> > + * Functions for configuring ACC200 HW, exposed directly to applications.
> > + * Configuration related to encoding/decoding is done through the
> > + * librte_bbdev library.
> > + *
> > + * @warning
> > + * @b EXPERIMENTAL: this API may change without prior notice */
> > +
> > +#include <stdint.h>
> > +#include <stdbool.h>
> > +#include "rte_acc_common_cfg.h"
> > +
> > +#ifdef __cplusplus
> > +extern "C" {
> > +#endif
> > +
> > +/**
> > + * Configure a ACC200 device
> > + *
> > + * @param dev_name
> > + * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
> > + * It can also be retrieved for a bbdev device from the dev_name field in
> the
> > + * rte_bbdev_info structure returned by rte_bbdev_info_get().
> > + * @param conf
> > + * Configuration to apply to ACC200 HW.
> > + *
> > + * @return
> > + * Zero on success, negative value on failure.
> > + */
> > +__rte_experimental
> > +int
> > +rte_acc200_configure(const char *dev_name, struct rte_acc_conf
> > +*conf);
> > +
> > +#ifdef __cplusplus
> > +}
> > +#endif
> > +
> > +#endif /* _RTE_ACC200_CFG_H_ */
> > diff --git a/drivers/baseband/acc/rte_acc200_pmd.c
> > b/drivers/baseband/acc/rte_acc200_pmd.c
> > index 3c2931b..21d614d 100644
> > --- a/drivers/baseband/acc/rte_acc200_pmd.c
> > +++ b/drivers/baseband/acc/rte_acc200_pmd.c
> > @@ -43,6 +43,27 @@
> >
> > enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, NUM_ACC};
> >
> > +/* Return the accelerator enum for a Queue Group Index */ static
> > +inline int accFromQgid(int qg_idx, const struct rte_acc_conf
> > +*acc_conf) {
> > + int accQg[ACC200_NUM_QGRPS];
> > + int NumQGroupsPerFn[NUM_ACC];
> > + int acc, qgIdx, qgIndex = 0;
> > + for (qgIdx = 0; qgIdx < ACC200_NUM_QGRPS; qgIdx++)
> > + accQg[qgIdx] = 0;
> > + NumQGroupsPerFn[UL_4G] = acc_conf->q_ul_4g.num_qgroups;
> > + NumQGroupsPerFn[UL_5G] = acc_conf->q_ul_5g.num_qgroups;
> > + NumQGroupsPerFn[DL_4G] = acc_conf->q_dl_4g.num_qgroups;
> > + NumQGroupsPerFn[DL_5G] = acc_conf->q_dl_5g.num_qgroups;
> > + NumQGroupsPerFn[FFT] = acc_conf->q_fft.num_qgroups;
> > + for (acc = UL_4G; acc < NUM_ACC; acc++)
> > + for (qgIdx = 0; qgIdx < NumQGroupsPerFn[acc]; qgIdx++)
> > + accQg[qgIndex++] = acc;
> > + acc = accQg[qg_idx];
> > + return acc;
> > +}
> > +
> > /* Return the queue topology for a Queue Group Index */
> > static inline void
> > qtopFromAcc(struct rte_acc_queue_topology **qtop, int acc_enum, @@
> > -75,6 +96,30 @@
> > *qtop = p_qtop;
> > }
> >
> > +/* Return the AQ depth for a Queue Group Index */ static inline int
> > +aqDepth(int qg_idx, struct rte_acc_conf *acc_conf) {
> > + struct rte_acc_queue_topology *q_top = NULL;
> > + int acc_enum = accFromQgid(qg_idx, acc_conf);
> > + qtopFromAcc(&q_top, acc_enum, acc_conf);
> > + if (unlikely(q_top == NULL))
> > + return 0;
> > + return q_top->aq_depth_log2;
> > +}
> > +
> > +/* Return the AQ depth for a Queue Group Index */ static inline int
> > +aqNum(int qg_idx, struct rte_acc_conf *acc_conf) {
> > + struct rte_acc_queue_topology *q_top = NULL;
> > + int acc_enum = accFromQgid(qg_idx, acc_conf);
> > + qtopFromAcc(&q_top, acc_enum, acc_conf);
> > + if (unlikely(q_top == NULL))
> > + return 0;
> > + return q_top->num_aqs_per_groups;
> > +}
>
>
> For the 3 functions above, please add new lines for clarity.
OK, guidelines would be good, as I am not fully convinced. But updating in new series.
>
> > +
> > static void
> > initQTop(struct rte_acc_conf *acc_conf)
> > {
> > @@ -3740,3 +3785,411 @@ static int acc200_pci_probe(struct
> rte_pci_driver *pci_drv,
> > RTE_PMD_REGISTER_PCI_TABLE(ACC200PF_DRIVER_NAME,
> pci_id_acc200_pf_map);
> > RTE_PMD_REGISTER_PCI(ACC200VF_DRIVER_NAME,
> acc200_pci_vf_driver);
> > RTE_PMD_REGISTER_PCI_TABLE(ACC200VF_DRIVER_NAME,
> > pci_id_acc200_vf_map);
> > +
> > +/* Initial configuration of a ACC200 device prior to running
> > +configure() */ int rte_acc200_configure(const char *dev_name, struct
> > +rte_acc_conf *conf) {
> > + rte_bbdev_log(INFO, "rte_acc200_configure");
> > + uint32_t value, address, status;
> > + int qg_idx, template_idx, vf_idx, acc, i;
> > + struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
> > +
> > + /* Compile time checks */
> > + RTE_BUILD_BUG_ON(sizeof(struct acc_dma_req_desc) != 256);
> > + RTE_BUILD_BUG_ON(sizeof(union acc_dma_desc) != 256);
> > + RTE_BUILD_BUG_ON(sizeof(struct acc_fcw_td) != 24);
> > + RTE_BUILD_BUG_ON(sizeof(struct acc_fcw_te) != 32);
> > +
> > + if (bbdev == NULL) {
> > + rte_bbdev_log(ERR,
> > + "Invalid dev_name (%s), or device is not yet initialised",
> > + dev_name);
> > + return -ENODEV;
> > + }
> > + struct acc_device *d = bbdev->data->dev_private;
> > +
> > + /* Store configuration */
> > + rte_memcpy(&d->acc_conf, conf, sizeof(d->acc_conf));
> > +
> > +
> > + /* Check we are already out of PG */
> > + status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
> > + if (status > 0) {
> > + if (status != ACC200_PG_MASK_0) {
> > + rte_bbdev_log(ERR, "Unexpected status %x %x",
> > + status, ACC200_PG_MASK_0);
> > + return -ENODEV;
> > + }
> > + /* Clock gate sections that will be un-PG */
> > + acc_reg_write(d, HWPfHiClkGateHystReg, ACC200_CLK_DIS);
> > + /* Un-PG required sections */
> > + acc_reg_write(d, HWPfHiSectionPowerGatingReq,
> > + ACC200_PG_MASK_1);
> > + status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
> > + if (status != ACC200_PG_MASK_1) {
> > + rte_bbdev_log(ERR, "Unexpected status %x %x",
> > + status, ACC200_PG_MASK_1);
> > + return -ENODEV;
> > + }
> > + acc_reg_write(d, HWPfHiSectionPowerGatingReq,
> > + ACC200_PG_MASK_2);
> > + status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
> > + if (status != ACC200_PG_MASK_2) {
> > + rte_bbdev_log(ERR, "Unexpected status %x %x",
> > + status, ACC200_PG_MASK_2);
> > + return -ENODEV;
> > + }
> > + acc_reg_write(d, HWPfHiSectionPowerGatingReq,
> > + ACC200_PG_MASK_3);
> > + status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
> > + if (status != ACC200_PG_MASK_3) {
> > + rte_bbdev_log(ERR, "Unexpected status %x %x",
> > + status, ACC200_PG_MASK_3);
> > + return -ENODEV;
> > + }
> > + /* Enable clocks for all sections */
> > + acc_reg_write(d, HWPfHiClkGateHystReg, ACC200_CLK_EN);
> > + }
> > +
> > + /* Explicitly releasing AXI as this may be stopped after PF FLR/BME */
> > + address = HWPfDmaAxiControl;
> > + value = 1;
> > + acc_reg_write(d, address, value);
> > +
> > + /* Set the fabric mode */
> > + address = HWPfFabricM2iBufferReg;
> > + value = ACC200_FABRIC_MODE;
> > + acc_reg_write(d, address, value);
> > +
> > + /* Set default descriptor signature */
> > + address = HWPfDmaDescriptorSignatuture;
> > + value = 0;
> > + acc_reg_write(d, address, value);
> > +
> > + /* Enable the Error Detection in DMA */
> > + value = ACC200_CFG_DMA_ERROR;
> > + address = HWPfDmaErrorDetectionEn;
> > + acc_reg_write(d, address, value);
> > +
> > + /* AXI Cache configuration */
> > + value = ACC200_CFG_AXI_CACHE;
> > + address = HWPfDmaAxcacheReg;
> > + acc_reg_write(d, address, value);
> > +
> > + /* Default DMA Configuration (Qmgr Enabled) */
> > + address = HWPfDmaConfig0Reg;
> > + value = 0;
> > + acc_reg_write(d, address, value);
> > + address = HWPfDmaQmanen;
> > + value = 0;
> > + acc_reg_write(d, address, value);
> > +
> > + /* Default RLIM/ALEN configuration */
> > + int rlim = 0;
> > + int alen = 1;
> > + int timestamp = 0;
> > + address = HWPfDmaConfig1Reg;
> > + value = (1 << 31) + (rlim << 8) + (timestamp << 6) + alen;
> > + acc_reg_write(d, address, value);
> > +
> > + /* Default FFT configuration */
> > + address = HWPfFftConfig0;
> > + value = ACC200_FFT_CFG_0;
> > + acc_reg_write(d, address, value);
> > +
> > + /* Configure DMA Qmanager addresses */
> > + address = HWPfDmaQmgrAddrReg;
> > + value = HWPfQmgrEgressQueuesTemplate;
> > + acc_reg_write(d, address, value);
> > +
> > + /* ===== Qmgr Configuration ===== */
> > + /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2
> for UL */
> > + int totalQgs = conf->q_ul_4g.num_qgroups +
> > + conf->q_ul_5g.num_qgroups +
> > + conf->q_dl_4g.num_qgroups +
> > + conf->q_dl_5g.num_qgroups +
> > + conf->q_fft.num_qgroups;
> > + for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {
> > + address = HWPfQmgrDepthLog2Grp +
> > + ACC_BYTES_IN_WORD * qg_idx;
> > + value = aqDepth(qg_idx, conf);
> > + acc_reg_write(d, address, value);
> > + address = HWPfQmgrTholdGrp +
> > + ACC_BYTES_IN_WORD * qg_idx;
> > + value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
> > + acc_reg_write(d, address, value);
> > + }
> > +
> > + /* Template Priority in incremental order */
> > + for (template_idx = 0; template_idx < ACC_NUM_TMPL;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg0Indx +
> ACC_BYTES_IN_WORD * template_idx;
> > + value = ACC_TMPL_PRI_0;
> > + acc_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg1Indx +
> ACC_BYTES_IN_WORD * template_idx;
> > + value = ACC_TMPL_PRI_1;
> > + acc_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg2indx +
> ACC_BYTES_IN_WORD * template_idx;
> > + value = ACC_TMPL_PRI_2;
> > + acc_reg_write(d, address, value);
> > + address = HWPfQmgrGrpTmplateReg3Indx +
> ACC_BYTES_IN_WORD * template_idx;
> > + value = ACC_TMPL_PRI_3;
> > + acc_reg_write(d, address, value);
> > + }
> > +
> > + address = HWPfQmgrGrpPriority;
> > + value = ACC200_CFG_QMGR_HI_P;
> > + acc_reg_write(d, address, value);
> > +
> > + /* Template Configuration */
> > + for (template_idx = 0; template_idx < ACC_NUM_TMPL;
> > + template_idx++) {
> > + value = 0;
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC_BYTES_IN_WORD * template_idx;
> > + acc_reg_write(d, address, value);
> > + }
> > + /* 4GUL */
> > + int numQgs = conf->q_ul_4g.num_qgroups;
> > + int numQqsAcc = 0;
>
> Don't mix declarations & code, here and elsewhere in this function.
OK
>
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC200_SIG_UL_4G;
> > + template_idx <= ACC200_SIG_UL_4G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC_BYTES_IN_WORD * template_idx;
> > + acc_reg_write(d, address, value);
> > + }
> > + /* 5GUL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_ul_5g.num_qgroups;
> > + value = 0;
> > + int numEngines = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC200_SIG_UL_5G;
> > + template_idx <= ACC200_SIG_UL_5G_LAST;
> > + template_idx++) {
> > + /* Check engine power-on status */
> > + address = HwPfFecUl5gIbDebugReg + ACC_ENGINE_OFFSET
> * template_idx;
> > + status = (acc_reg_read(d, address) >> 4) & 0x7;
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC_BYTES_IN_WORD * template_idx;
> > + if (status == 1) {
> > + acc_reg_write(d, address, value);
> > + numEngines++;
> > + } else
> > + acc_reg_write(d, address, 0);
> > + }
> > + printf("Number of 5GUL engines %d\n", numEngines);
> > + /* 4GDL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_dl_4g.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC200_SIG_DL_4G;
> > + template_idx <= ACC200_SIG_DL_4G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC_BYTES_IN_WORD * template_idx;
> > + acc_reg_write(d, address, value);
> > + }
> > + /* 5GDL */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_dl_5g.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC200_SIG_DL_5G;
> > + template_idx <= ACC200_SIG_DL_5G_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC_BYTES_IN_WORD * template_idx;
> > + acc_reg_write(d, address, value);
> > + }
> > + /* FFT */
> > + numQqsAcc += numQgs;
> > + numQgs = conf->q_fft.num_qgroups;
> > + value = 0;
> > + for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc);
> qg_idx++)
> > + value |= (1 << qg_idx);
> > + for (template_idx = ACC200_SIG_FFT;
> > + template_idx <= ACC200_SIG_FFT_LAST;
> > + template_idx++) {
> > + address = HWPfQmgrGrpTmplateReg4Indx
> > + + ACC_BYTES_IN_WORD * template_idx;
> > + acc_reg_write(d, address, value);
> > + }
> > +
> > + /* Queue Group Function mapping */
> > + int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
> > + value = 0;
> > + for (qg_idx = 0; qg_idx < ACC_NUM_QGRPS_PER_WORD; qg_idx++) {
> > + acc = accFromQgid(qg_idx, conf);
> > + value |= qman_func_id[acc] << (qg_idx * 4);
> > + }
> > + acc_reg_write(d, HWPfQmgrGrpFunction0, value);
> > + value = 0;
> > + for (qg_idx = 0; qg_idx < ACC_NUM_QGRPS_PER_WORD; qg_idx++) {
> > + acc = accFromQgid(qg_idx + ACC_NUM_QGRPS_PER_WORD,
> conf);
> > + value |= qman_func_id[acc] << (qg_idx * 4);
> > + }
> > + acc_reg_write(d, HWPfQmgrGrpFunction1, value);
> > +
> > + /* Configuration of the Arbitration QGroup depth to 1 */
> > + for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {
> > + address = HWPfQmgrArbQDepthGrp +
> > + ACC_BYTES_IN_WORD * qg_idx;
> > + value = 0;
> > + acc_reg_write(d, address, value);
> > + }
> > +
> > + /* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */
> > + uint32_t aram_address = 0;
> > + for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
> > + for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
> > + address = HWPfQmgrVfBaseAddr + vf_idx
> > + * ACC_BYTES_IN_WORD + qg_idx
> > + * ACC_BYTES_IN_WORD * 64;
> > + value = aram_address;
> > + acc_reg_write(d, address, value);
> > + /* Offset ARAM Address for next memory bank
> > + * - increment of 4B
> > + */
> > + aram_address += aqNum(qg_idx, conf) *
> > + (1 << aqDepth(qg_idx, conf));
> > + }
> > + }
> > +
> > + if (aram_address > ACC200_WORDS_IN_ARAM_SIZE) {
> > + rte_bbdev_log(ERR, "ARAM Configuration not fitting %d
> %d\n",
> > + aram_address,
> ACC200_WORDS_IN_ARAM_SIZE);
> > + return -EINVAL;
> > + }
> > +
> > + /* Performance tuning */
> > + acc_reg_write(d, HWPfFabricI2Mdma_weight, 0x0FFF);
> > + acc_reg_write(d, HWPfDma4gdlIbThld, 0x1f10);
> > +
> > + /* ==== HI Configuration ==== */
> > +
> > + /* No Info Ring/MSI by default */
> > + address = HWPfHiInfoRingIntWrEnRegPf;
> > + value = 0;
> > + acc_reg_write(d, address, value);
> > + address = HWPfHiCfgMsiIntWrEnRegPf;
> > + value = 0xFFFFFFFF;
> > + acc_reg_write(d, address, value);
> > + /* Prevent Block on Transmit Error */
> > + address = HWPfHiBlockTransmitOnErrorEn;
> > + value = 0;
> > + acc_reg_write(d, address, value);
> > + /* Prevents to drop MSI */
> > + address = HWPfHiMsiDropEnableReg;
> > + value = 0;
> > + acc_reg_write(d, address, value);
> > + /* Set the PF Mode register */
> > + address = HWPfHiPfMode;
> > + value = (conf->pf_mode_en) ? ACC_PF_VAL : 0;
> > + acc_reg_write(d, address, value);
> > +
> > + /* QoS overflow init */
> > + value = 1;
> > + address = HWPfQosmonAEvalOverflow0;
> > + acc_reg_write(d, address, value);
> > + address = HWPfQosmonBEvalOverflow0;
> > + acc_reg_write(d, address, value);
> > +
> > + /* Configure the FFT RAM LUT */
> > + uint32_t fft_lut[ACC200_FFT_RAM_SIZE] = {
> > + 0x1FFFF, 0x1FFFF, 0x1FFFE, 0x1FFFA, 0x1FFF6, 0x1FFF1, 0x1FFEA,
> 0x1FFE2,
> > + 0x1FFD9, 0x1FFCE, 0x1FFC2, 0x1FFB5, 0x1FFA7, 0x1FF98, 0x1FF87,
> 0x1FF75,
> > + 0x1FF62, 0x1FF4E, 0x1FF38, 0x1FF21, 0x1FF09, 0x1FEF0, 0x1FED6,
> 0x1FEBA,
> > + 0x1FE9D, 0x1FE7F, 0x1FE5F, 0x1FE3F, 0x1FE1D, 0x1FDFA, 0x1FDD5,
> 0x1FDB0,
> > + 0x1FD89, 0x1FD61, 0x1FD38, 0x1FD0D, 0x1FCE1, 0x1FCB4, 0x1FC86,
> 0x1FC57,
> > + 0x1FC26, 0x1FBF4, 0x1FBC1, 0x1FB8D, 0x1FB58, 0x1FB21, 0x1FAE9,
> 0x1FAB0,
> > + 0x1FA75, 0x1FA3A, 0x1F9FD, 0x1F9BF, 0x1F980, 0x1F93F, 0x1F8FD,
> 0x1F8BA,
> > + 0x1F876, 0x1F831, 0x1F7EA, 0x1F7A3, 0x1F75A, 0x1F70F, 0x1F6C4,
> 0x1F677,
> > + 0x1F629, 0x1F5DA, 0x1F58A, 0x1F539, 0x1F4E6, 0x1F492, 0x1F43D,
> 0x1F3E7,
> > + 0x1F38F, 0x1F337, 0x1F2DD, 0x1F281, 0x1F225, 0x1F1C8, 0x1F169,
> 0x1F109,
> > + 0x1F0A8, 0x1F046, 0x1EFE2, 0x1EF7D, 0x1EF18, 0x1EEB0, 0x1EE48,
> 0x1EDDF,
> > + 0x1ED74, 0x1ED08, 0x1EC9B, 0x1EC2D, 0x1EBBE, 0x1EB4D,
> 0x1EADB, 0x1EA68,
> > + 0x1E9F4, 0x1E97F, 0x1E908, 0x1E891, 0x1E818, 0x1E79E, 0x1E722,
> 0x1E6A6,
> > + 0x1E629, 0x1E5AA, 0x1E52A, 0x1E4A9, 0x1E427, 0x1E3A3, 0x1E31F,
> 0x1E299,
> > + 0x1E212, 0x1E18A, 0x1E101, 0x1E076, 0x1DFEB, 0x1DF5E, 0x1dED0,
> 0x1DE41,
> > + 0x1DDB1, 0x1DD20, 0x1DC8D, 0x1DBFA, 0x1DB65, 0x1DACF,
> 0x1DA38, 0x1D9A0,
> > + 0x1D907, 0x1D86C, 0x1D7D1, 0x1D734, 0x1D696, 0x1D5F7,
> 0x1D557, 0x1D4B6,
> > + 0x1D413, 0x1D370, 0x1D2CB, 0x1D225, 0x1D17E, 0x1D0D6,
> 0x1D02D, 0x1CF83,
> > + 0x1CED8, 0x1CE2B, 0x1CD7E, 0x1CCCF, 0x1CC1F, 0x1CB6E,
> 0x1CABC, 0x1CA09,
> > + 0x1C955, 0x1C89F, 0x1C7E9, 0x1C731, 0x1C679, 0x1C5BF, 0x1C504,
> 0x1C448,
> > + 0x1C38B, 0x1C2CD, 0x1C20E, 0x1C14E, 0x1C08C, 0x1BFCA, 0x1BF06,
> 0x1BE42,
> > + 0x1BD7C, 0x1BCB5, 0x1BBED, 0x1BB25, 0x1BA5B, 0x1B990,
> 0x1B8C4, 0x1B7F6,
> > + 0x1B728, 0x1B659, 0x1B589, 0x1B4B7, 0x1B3E5, 0x1B311, 0x1B23D,
> 0x1B167,
> > + 0x1B091, 0x1AFB9, 0x1AEE0, 0x1AE07, 0x1AD2C, 0x1AC50, 0x1AB73,
> 0x1AA95,
> > + 0x1A9B6, 0x1A8D6, 0x1A7F6, 0x1A714, 0x1A631, 0x1A54D, 0x1A468,
> 0x1A382,
> > + 0x1A29A, 0x1A1B2, 0x1A0C9, 0x19FDF, 0x19EF4, 0x19E08, 0x19D1B,
> 0x19C2D,
> > + 0x19B3E, 0x19A4E, 0x1995D, 0x1986B, 0x19778, 0x19684, 0x1958F,
> 0x19499,
> > + 0x193A2, 0x192AA, 0x191B1, 0x190B8, 0x18FBD, 0x18EC1, 0x18DC4,
> 0x18CC7,
> > + 0x18BC8, 0x18AC8, 0x189C8, 0x188C6, 0x187C4, 0x186C1, 0x185BC,
> 0x184B7,
> > + 0x183B1, 0x182AA, 0x181A2, 0x18099, 0x17F8F, 0x17E84, 0x17D78,
> 0x17C6C,
> > + 0x17B5E, 0x17A4F, 0x17940, 0x17830, 0x1771E, 0x1760C, 0x174F9,
> 0x173E5,
> > + 0x172D1, 0x171BB, 0x170A4, 0x16F8D, 0x16E74, 0x16D5B, 0x16C41,
> 0x16B26,
> > + 0x16A0A, 0x168ED, 0x167CF, 0x166B1, 0x16592, 0x16471, 0x16350,
> 0x1622E,
> > + 0x1610B, 0x15FE8, 0x15EC3, 0x15D9E, 0x15C78, 0x15B51, 0x15A29,
> 0x15900,
> > + 0x157D7, 0x156AC, 0x15581, 0x15455, 0x15328, 0x151FB, 0x150CC,
> 0x14F9D,
> > + 0x14E6D, 0x14D3C, 0x14C0A, 0x14AD8, 0x149A4, 0x14870, 0x1473B,
> 0x14606,
> > + 0x144CF, 0x14398, 0x14260, 0x14127, 0x13FEE, 0x13EB3, 0x13D78,
> 0x13C3C,
> > + 0x13B00, 0x139C2, 0x13884, 0x13745, 0x13606, 0x134C5, 0x13384,
> 0x13242,
> > + 0x130FF, 0x12FBC, 0x12E78, 0x12D33, 0x12BEE, 0x12AA7, 0x12960,
> 0x12819,
> > + 0x126D0, 0x12587, 0x1243D, 0x122F3, 0x121A8, 0x1205C, 0x11F0F,
> 0x11DC2,
> > + 0x11C74, 0x11B25, 0x119D6, 0x11886, 0x11735, 0x115E3, 0x11491,
> 0x1133F,
> > + 0x111EB, 0x11097, 0x10F42, 0x10dED, 0x10C97, 0x10B40, 0x109E9,
> 0x10891,
> > + 0x10738, 0x105DF, 0x10485, 0x1032B, 0x101D0, 0x10074, 0x0FF18,
> 0x0FDBB,
> > + 0x0FC5D, 0x0FAFF, 0x0F9A0, 0x0F841, 0x0F6E1, 0x0F580, 0x0F41F,
> 0x0F2BD,
> > + 0x0F15B, 0x0EFF8, 0x0EE94, 0x0ED30, 0x0EBCC, 0x0EA67, 0x0E901,
> 0x0E79A,
> > + 0x0E633, 0x0E4CC, 0x0E364, 0x0E1FB, 0x0E092, 0x0DF29, 0x0DDBE,
> 0x0DC54,
> > + 0x0DAE9, 0x0D97D, 0x0D810, 0x0D6A4, 0x0D536, 0x0D3C8,
> 0x0D25A, 0x0D0EB,
> > + 0x0CF7C, 0x0CE0C, 0x0CC9C, 0x0CB2B, 0x0C9B9, 0x0C847,
> 0x0C6D5, 0x0C562,
> > + 0x0C3EF, 0x0C27B, 0x0C107, 0x0BF92, 0x0BE1D, 0x0BCA8, 0x0BB32,
> 0x0B9BB,
> > + 0x0B844, 0x0B6CD, 0x0B555, 0x0B3DD, 0x0B264, 0x0B0EB,
> 0x0AF71, 0x0ADF7,
> > + 0x0AC7D, 0x0AB02, 0x0A987, 0x0A80B, 0x0A68F, 0x0A513, 0x0A396,
> 0x0A219,
> > + 0x0A09B, 0x09F1D, 0x09D9E, 0x09C20, 0x09AA1, 0x09921, 0x097A1,
> 0x09621,
> > + 0x094A0, 0x0931F, 0x0919E, 0x0901C, 0x08E9A, 0x08D18, 0x08B95,
> 0x08A12,
> > + 0x0888F, 0x0870B, 0x08587, 0x08402, 0x0827E, 0x080F9, 0x07F73,
> 0x07DEE,
> > + 0x07C68, 0x07AE2, 0x0795B, 0x077D4, 0x0764D, 0x074C6, 0x0733E,
> 0x071B6,
> > + 0x0702E, 0x06EA6, 0x06D1D, 0x06B94, 0x06A0B, 0x06881, 0x066F7,
> 0x0656D,
> > + 0x063E3, 0x06258, 0x060CE, 0x05F43, 0x05DB7, 0x05C2C, 0x05AA0,
> 0x05914,
> > + 0x05788, 0x055FC, 0x0546F, 0x052E3, 0x05156, 0x04FC9, 0x04E3B,
> 0x04CAE,
> > + 0x04B20, 0x04992, 0x04804, 0x04676, 0x044E8, 0x04359, 0x041CB,
> 0x0403C,
> > + 0x03EAD, 0x03D1D, 0x03B8E, 0x039FF, 0x0386F, 0x036DF, 0x0354F,
> 0x033BF,
> > + 0x0322F, 0x0309F, 0x02F0F, 0x02D7E, 0x02BEE, 0x02A5D, 0x028CC,
> 0x0273B,
> > + 0x025AA, 0x02419, 0x02288, 0x020F7, 0x01F65, 0x01DD4, 0x01C43,
> 0x01AB1,
> > + 0x0191F, 0x0178E, 0x015FC, 0x0146A, 0x012D8, 0x01147, 0x00FB5,
> 0x00E23,
> > + 0x00C91, 0x00AFF, 0x0096D, 0x007DB, 0x00648, 0x004B6, 0x00324,
> > +0x00192};
> > +
> > + acc_reg_write(d, HWPfFftRamPageAccess, ACC200_FFT_RAM_EN +
> 64);
> > + for (i = 0; i < ACC200_FFT_RAM_SIZE; i++)
> > + acc_reg_write(d, HWPfFftRamOff + i * 4, fft_lut[i]);
> > + acc_reg_write(d, HWPfFftRamPageAccess, ACC200_FFT_RAM_DIS);
> > +
> > + /* Enabling AQueues through the Queue hierarchy*/
> > + for (vf_idx = 0; vf_idx < ACC200_NUM_VFS; vf_idx++) {
> > + for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {
> > + value = 0;
> > + if (vf_idx < conf->num_vf_bundles &&
> > + qg_idx < totalQgs)
> > + value = (1 << aqNum(qg_idx, conf)) - 1;
> > + address = HWPfQmgrAqEnableVf
> > + + vf_idx * ACC_BYTES_IN_WORD;
> > + value += (qg_idx << 16);
> > + acc_reg_write(d, address, value);
> > + }
> > + }
> > +
> > + rte_bbdev_log_debug("PF Tip configuration complete for %s",
> dev_name);
> > + return 0;
> > +}
> > diff --git a/drivers/baseband/acc/version.map
> > b/drivers/baseband/acc/version.map
> > index b4ff13e..27fbbe3 100644
> > --- a/drivers/baseband/acc/version.map
> > +++ b/drivers/baseband/acc/version.map
> > @@ -6,4 +6,5 @@ EXPERIMENTAL {
> > global:
> >
> > rte_acc10x_configure;
> > + rte_acc200_configure;
> > };
On 9/24/22 02:20, Chautru, Nicolas wrote:
> Hi Maxime,
> Thanks will send an updated serie now. Much appreciated.
>
>> -----Original Message-----
>> From: Maxime Coquelin <maxime.coquelin@redhat.com>
>> Sent: Friday, September 23, 2022 2:26 AM
>> To: Chautru, Nicolas <nicolas.chautru@intel.com>; dev@dpdk.org;
>> thomas@monjalon.net
>> Cc: trix@redhat.com; mdr@ashroe.eu; Richardson, Bruce
>> <bruce.richardson@intel.com>; hemant.agrawal@nxp.com;
>> david.marchand@redhat.com; stephen@networkplumber.org; Vargas,
>> Hernan <hernan.vargas@intel.com>
>> Subject: Re: [PATCH v4 13/14] baseband/acc: add PF configure companion
>> function
>>
>>
>>
>> On 9/22/22 02:27, Nic Chautru wrote:
>>> Add configure function notably to configure the device from the PF
>>> within DPDK and bbdev-test (without external dependency).
>>>
>>> Signed-off-by: Nic Chautru <nicolas.chautru@intel.com>
>>> ---
>>> app/test-bbdev/test_bbdev_perf.c | 71 ++++++
>>> drivers/baseband/acc/meson.build | 2 +-
>>> drivers/baseband/acc/rte_acc200_cfg.h | 48 ++++
>>> drivers/baseband/acc/rte_acc200_pmd.c | 453
>> ++++++++++++++++++++++++++++++++++
>>> drivers/baseband/acc/version.map | 1 +
>>> 5 files changed, 574 insertions(+), 1 deletion(-)
>>> create mode 100644 drivers/baseband/acc/rte_acc200_cfg.h
>>>
>>> diff --git a/app/test-bbdev/test_bbdev_perf.c
>>> b/app/test-bbdev/test_bbdev_perf.c
>>> index 41c78de..ec6ee2a 100644
>>> --- a/app/test-bbdev/test_bbdev_perf.c
>>> +++ b/app/test-bbdev/test_bbdev_perf.c
>>> @@ -62,6 +62,15 @@
>>> #define ACC100_QMGR_INVALID_IDX -1
>>> #define ACC100_QMGR_RR 1
>>> #define ACC100_QOS_GBR 0
>>> +#include <rte_acc200_cfg.h>
>>> +#define ACC200PF_DRIVER_NAME ("intel_acc200_pf")
>>> +#define ACC200VF_DRIVER_NAME ("intel_acc200_vf")
>>> +#define ACC200_QMGR_NUM_AQS 16
>>> +#define ACC200_QMGR_NUM_QGS 2
>>> +#define ACC200_QMGR_AQ_DEPTH 5
>>> +#define ACC200_QMGR_INVALID_IDX -1
>>> +#define ACC200_QMGR_RR 1
>>> +#define ACC200_QOS_GBR 0
>>> #endif
>>>
>>> #define OPS_CACHE_SIZE 256U
>>> @@ -761,6 +770,68 @@ typedef int (test_case_function)(struct
>> active_device *ad,
>>> "Failed to configure ACC100 PF for bbdev
>> %s",
>>> info->dev_name);
>>> }
>>> + if ((get_init_device() == true) &&
>>> + (!strcmp(info->drv.driver_name, ACC200PF_DRIVER_NAME)))
>> {
>>> + struct rte_acc_conf conf;
>>> + unsigned int i;
>>> +
>>> + printf("Configure ACC200 FEC Driver %s with default
>> values\n",
>>> + info->drv.driver_name);
>>> +
>>> + /* clear default configuration before initialization */
>>> + memset(&conf, 0, sizeof(struct rte_acc_conf));
>>> +
>>> + /* Always set in PF mode for built-in configuration */
>>> + conf.pf_mode_en = true;
>>> + for (i = 0; i < RTE_ACC_NUM_VFS; ++i) {
>>> + conf.arb_dl_4g[i].gbr_threshold1 =
>> ACC200_QOS_GBR;
>>> + conf.arb_dl_4g[i].gbr_threshold1 =
>> ACC200_QOS_GBR;
>>> + conf.arb_dl_4g[i].round_robin_weight =
>> ACC200_QMGR_RR;
>>> + conf.arb_ul_4g[i].gbr_threshold1 =
>> ACC200_QOS_GBR;
>>> + conf.arb_ul_4g[i].gbr_threshold1 =
>> ACC200_QOS_GBR;
>>> + conf.arb_ul_4g[i].round_robin_weight =
>> ACC200_QMGR_RR;
>>> + conf.arb_dl_5g[i].gbr_threshold1 =
>> ACC200_QOS_GBR;
>>> + conf.arb_dl_5g[i].gbr_threshold1 =
>> ACC200_QOS_GBR;
>>> + conf.arb_dl_5g[i].round_robin_weight =
>> ACC200_QMGR_RR;
>>> + conf.arb_ul_5g[i].gbr_threshold1 =
>> ACC200_QOS_GBR;
>>> + conf.arb_ul_5g[i].gbr_threshold1 =
>> ACC200_QOS_GBR;
>>> + conf.arb_ul_5g[i].round_robin_weight =
>> ACC200_QMGR_RR;
>>> + conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;
>>> + conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;
>>> + conf.arb_fft[i].round_robin_weight =
>> ACC200_QMGR_RR;
>>> + }
>>> +
>>> + conf.input_pos_llr_1_bit = true;
>>> + conf.output_pos_llr_1_bit = true;
>>> + conf.num_vf_bundles = 1; /**< Number of VF bundles to
>> setup */
>>> +
>>> + conf.q_ul_4g.num_qgroups = ACC200_QMGR_NUM_QGS;
>>> + conf.q_ul_4g.first_qgroup_index =
>> ACC200_QMGR_INVALID_IDX;
>>> + conf.q_ul_4g.num_aqs_per_groups =
>> ACC200_QMGR_NUM_AQS;
>>> + conf.q_ul_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
>>> + conf.q_dl_4g.num_qgroups = ACC200_QMGR_NUM_QGS;
>>> + conf.q_dl_4g.first_qgroup_index =
>> ACC200_QMGR_INVALID_IDX;
>>> + conf.q_dl_4g.num_aqs_per_groups =
>> ACC200_QMGR_NUM_AQS;
>>> + conf.q_dl_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
>>> + conf.q_ul_5g.num_qgroups = ACC200_QMGR_NUM_QGS;
>>> + conf.q_ul_5g.first_qgroup_index =
>> ACC200_QMGR_INVALID_IDX;
>>> + conf.q_ul_5g.num_aqs_per_groups =
>> ACC200_QMGR_NUM_AQS;
>>> + conf.q_ul_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
>>> + conf.q_dl_5g.num_qgroups = ACC200_QMGR_NUM_QGS;
>>> + conf.q_dl_5g.first_qgroup_index =
>> ACC200_QMGR_INVALID_IDX;
>>> + conf.q_dl_5g.num_aqs_per_groups =
>> ACC200_QMGR_NUM_AQS;
>>> + conf.q_dl_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
>>> + conf.q_fft.num_qgroups = ACC200_QMGR_NUM_QGS;
>>> + conf.q_fft.first_qgroup_index =
>> ACC200_QMGR_INVALID_IDX;
>>> + conf.q_fft.num_aqs_per_groups =
>> ACC200_QMGR_NUM_AQS;
>>> + conf.q_fft.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
>>> +
>>> + /* setup PF with configuration information */
>>> + ret = rte_acc200_configure(info->dev_name, &conf);
>>> + TEST_ASSERT_SUCCESS(ret,
>>> + "Failed to configure ACC200 PF for bbdev
>> %s",
>>> + info->dev_name);
>>> + }
>>> #endif
>>> /* Let's refresh this now this is configured */
>>> rte_bbdev_info_get(dev_id, info);
>>> diff --git a/drivers/baseband/acc/meson.build
>>> b/drivers/baseband/acc/meson.build
>>> index 63912f0..7ae162a 100644
>>> --- a/drivers/baseband/acc/meson.build
>>> +++ b/drivers/baseband/acc/meson.build
>>> @@ -5,4 +5,4 @@ deps += ['bbdev', 'bus_vdev', 'ring', 'pci',
>>> 'bus_pci']
>>>
>>> sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c')
>>>
>>> -headers = files('rte_acc100_cfg.h')
>>> +headers = files('rte_acc100_cfg.h', 'rte_acc200_cfg.h')
>>> diff --git a/drivers/baseband/acc/rte_acc200_cfg.h
>>> b/drivers/baseband/acc/rte_acc200_cfg.h
>>> new file mode 100644
>>> index 0000000..8bd9b20
>>> --- /dev/null
>>> +++ b/drivers/baseband/acc/rte_acc200_cfg.h
>>> @@ -0,0 +1,48 @@
>>> +/* SPDX-License-Identifier: BSD-3-Clause
>>> + * Copyright(c) 2022 Intel Corporation */
>>> +
>>> +#ifndef _RTE_ACC200_CFG_H_
>>> +#define _RTE_ACC200_CFG_H_
>>> +
>>> +/**
>>> + * @file rte_acc200_cfg.h
>>> + *
>>> + * Functions for configuring ACC200 HW, exposed directly to applications.
>>> + * Configuration related to encoding/decoding is done through the
>>> + * librte_bbdev library.
>>> + *
>>> + * @warning
>>> + * @b EXPERIMENTAL: this API may change without prior notice */
>>> +
>>> +#include <stdint.h>
>>> +#include <stdbool.h>
>>> +#include "rte_acc_common_cfg.h"
>>> +
>>> +#ifdef __cplusplus
>>> +extern "C" {
>>> +#endif
>>> +
>>> +/**
>>> + * Configure a ACC200 device
>>> + *
>>> + * @param dev_name
>>> + * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
>>> + * It can also be retrieved for a bbdev device from the dev_name field in
>> the
>>> + * rte_bbdev_info structure returned by rte_bbdev_info_get().
>>> + * @param conf
>>> + * Configuration to apply to ACC200 HW.
>>> + *
>>> + * @return
>>> + * Zero on success, negative value on failure.
>>> + */
>>> +__rte_experimental
>>> +int
>>> +rte_acc200_configure(const char *dev_name, struct rte_acc_conf
>>> +*conf);
>>> +
>>> +#ifdef __cplusplus
>>> +}
>>> +#endif
>>> +
>>> +#endif /* _RTE_ACC200_CFG_H_ */
>>> diff --git a/drivers/baseband/acc/rte_acc200_pmd.c
>>> b/drivers/baseband/acc/rte_acc200_pmd.c
>>> index 3c2931b..21d614d 100644
>>> --- a/drivers/baseband/acc/rte_acc200_pmd.c
>>> +++ b/drivers/baseband/acc/rte_acc200_pmd.c
>>> @@ -43,6 +43,27 @@
>>>
>>> enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, NUM_ACC};
>>>
>>> +/* Return the accelerator enum for a Queue Group Index */ static
>>> +inline int accFromQgid(int qg_idx, const struct rte_acc_conf
>>> +*acc_conf) {
>>> + int accQg[ACC200_NUM_QGRPS];
>>> + int NumQGroupsPerFn[NUM_ACC];
>>> + int acc, qgIdx, qgIndex = 0;
>>> + for (qgIdx = 0; qgIdx < ACC200_NUM_QGRPS; qgIdx++)
>>> + accQg[qgIdx] = 0;
>>> + NumQGroupsPerFn[UL_4G] = acc_conf->q_ul_4g.num_qgroups;
>>> + NumQGroupsPerFn[UL_5G] = acc_conf->q_ul_5g.num_qgroups;
>>> + NumQGroupsPerFn[DL_4G] = acc_conf->q_dl_4g.num_qgroups;
>>> + NumQGroupsPerFn[DL_5G] = acc_conf->q_dl_5g.num_qgroups;
>>> + NumQGroupsPerFn[FFT] = acc_conf->q_fft.num_qgroups;
>>> + for (acc = UL_4G; acc < NUM_ACC; acc++)
>>> + for (qgIdx = 0; qgIdx < NumQGroupsPerFn[acc]; qgIdx++)
>>> + accQg[qgIndex++] = acc;
>>> + acc = accQg[qg_idx];
>>> + return acc;
>>> +}
>>> +
>>> /* Return the queue topology for a Queue Group Index */
>>> static inline void
>>> qtopFromAcc(struct rte_acc_queue_topology **qtop, int acc_enum, @@
>>> -75,6 +96,30 @@
>>> *qtop = p_qtop;
>>> }
>>>
>>> +/* Return the AQ depth for a Queue Group Index */ static inline int
>>> +aqDepth(int qg_idx, struct rte_acc_conf *acc_conf) {
>>> + struct rte_acc_queue_topology *q_top = NULL;
>>> + int acc_enum = accFromQgid(qg_idx, acc_conf);
>>> + qtopFromAcc(&q_top, acc_enum, acc_conf);
>>> + if (unlikely(q_top == NULL))
>>> + return 0;
>>> + return q_top->aq_depth_log2;
>>> +}
>>> +
>>> +/* Return the AQ depth for a Queue Group Index */ static inline int
>>> +aqNum(int qg_idx, struct rte_acc_conf *acc_conf) {
>>> + struct rte_acc_queue_topology *q_top = NULL;
>>> + int acc_enum = accFromQgid(qg_idx, acc_conf);
>>> + qtopFromAcc(&q_top, acc_enum, acc_conf);
>>> + if (unlikely(q_top == NULL))
>>> + return 0;
>>> + return q_top->num_aqs_per_groups;
>>> +}
>>
>>
>> For the 3 functions above, please add new lines for clarity.
>
> OK, guidelines would be good, as I am not fully convinced. But updating in new series.
>
I have not checked whether it is in the contribution guidelines, but
having new lines between the variables declarations and code is
a common rules that makes the code more readable. So is having new lines
before the returns.
@@ -62,6 +62,15 @@
#define ACC100_QMGR_INVALID_IDX -1
#define ACC100_QMGR_RR 1
#define ACC100_QOS_GBR 0
+#include <rte_acc200_cfg.h>
+#define ACC200PF_DRIVER_NAME ("intel_acc200_pf")
+#define ACC200VF_DRIVER_NAME ("intel_acc200_vf")
+#define ACC200_QMGR_NUM_AQS 16
+#define ACC200_QMGR_NUM_QGS 2
+#define ACC200_QMGR_AQ_DEPTH 5
+#define ACC200_QMGR_INVALID_IDX -1
+#define ACC200_QMGR_RR 1
+#define ACC200_QOS_GBR 0
#endif
#define OPS_CACHE_SIZE 256U
@@ -761,6 +770,68 @@ typedef int (test_case_function)(struct active_device *ad,
"Failed to configure ACC100 PF for bbdev %s",
info->dev_name);
}
+ if ((get_init_device() == true) &&
+ (!strcmp(info->drv.driver_name, ACC200PF_DRIVER_NAME))) {
+ struct rte_acc_conf conf;
+ unsigned int i;
+
+ printf("Configure ACC200 FEC Driver %s with default values\n",
+ info->drv.driver_name);
+
+ /* clear default configuration before initialization */
+ memset(&conf, 0, sizeof(struct rte_acc_conf));
+
+ /* Always set in PF mode for built-in configuration */
+ conf.pf_mode_en = true;
+ for (i = 0; i < RTE_ACC_NUM_VFS; ++i) {
+ conf.arb_dl_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
+ conf.arb_dl_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
+ conf.arb_dl_4g[i].round_robin_weight = ACC200_QMGR_RR;
+ conf.arb_ul_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
+ conf.arb_ul_4g[i].gbr_threshold1 = ACC200_QOS_GBR;
+ conf.arb_ul_4g[i].round_robin_weight = ACC200_QMGR_RR;
+ conf.arb_dl_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
+ conf.arb_dl_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
+ conf.arb_dl_5g[i].round_robin_weight = ACC200_QMGR_RR;
+ conf.arb_ul_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
+ conf.arb_ul_5g[i].gbr_threshold1 = ACC200_QOS_GBR;
+ conf.arb_ul_5g[i].round_robin_weight = ACC200_QMGR_RR;
+ conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;
+ conf.arb_fft[i].gbr_threshold1 = ACC200_QOS_GBR;
+ conf.arb_fft[i].round_robin_weight = ACC200_QMGR_RR;
+ }
+
+ conf.input_pos_llr_1_bit = true;
+ conf.output_pos_llr_1_bit = true;
+ conf.num_vf_bundles = 1; /**< Number of VF bundles to setup */
+
+ conf.q_ul_4g.num_qgroups = ACC200_QMGR_NUM_QGS;
+ conf.q_ul_4g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
+ conf.q_ul_4g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
+ conf.q_ul_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
+ conf.q_dl_4g.num_qgroups = ACC200_QMGR_NUM_QGS;
+ conf.q_dl_4g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
+ conf.q_dl_4g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
+ conf.q_dl_4g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
+ conf.q_ul_5g.num_qgroups = ACC200_QMGR_NUM_QGS;
+ conf.q_ul_5g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
+ conf.q_ul_5g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
+ conf.q_ul_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
+ conf.q_dl_5g.num_qgroups = ACC200_QMGR_NUM_QGS;
+ conf.q_dl_5g.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
+ conf.q_dl_5g.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
+ conf.q_dl_5g.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
+ conf.q_fft.num_qgroups = ACC200_QMGR_NUM_QGS;
+ conf.q_fft.first_qgroup_index = ACC200_QMGR_INVALID_IDX;
+ conf.q_fft.num_aqs_per_groups = ACC200_QMGR_NUM_AQS;
+ conf.q_fft.aq_depth_log2 = ACC200_QMGR_AQ_DEPTH;
+
+ /* setup PF with configuration information */
+ ret = rte_acc200_configure(info->dev_name, &conf);
+ TEST_ASSERT_SUCCESS(ret,
+ "Failed to configure ACC200 PF for bbdev %s",
+ info->dev_name);
+ }
#endif
/* Let's refresh this now this is configured */
rte_bbdev_info_get(dev_id, info);
@@ -5,4 +5,4 @@ deps += ['bbdev', 'bus_vdev', 'ring', 'pci', 'bus_pci']
sources = files('rte_acc100_pmd.c', 'rte_acc200_pmd.c')
-headers = files('rte_acc100_cfg.h')
+headers = files('rte_acc100_cfg.h', 'rte_acc200_cfg.h')
new file mode 100644
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: BSD-3-Clause
+ * Copyright(c) 2022 Intel Corporation
+ */
+
+#ifndef _RTE_ACC200_CFG_H_
+#define _RTE_ACC200_CFG_H_
+
+/**
+ * @file rte_acc200_cfg.h
+ *
+ * Functions for configuring ACC200 HW, exposed directly to applications.
+ * Configuration related to encoding/decoding is done through the
+ * librte_bbdev library.
+ *
+ * @warning
+ * @b EXPERIMENTAL: this API may change without prior notice
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "rte_acc_common_cfg.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * Configure a ACC200 device
+ *
+ * @param dev_name
+ * The name of the device. This is the short form of PCI BDF, e.g. 00:01.0.
+ * It can also be retrieved for a bbdev device from the dev_name field in the
+ * rte_bbdev_info structure returned by rte_bbdev_info_get().
+ * @param conf
+ * Configuration to apply to ACC200 HW.
+ *
+ * @return
+ * Zero on success, negative value on failure.
+ */
+__rte_experimental
+int
+rte_acc200_configure(const char *dev_name, struct rte_acc_conf *conf);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_ACC200_CFG_H_ */
@@ -43,6 +43,27 @@
enum {UL_4G = 0, UL_5G, DL_4G, DL_5G, FFT, NUM_ACC};
+/* Return the accelerator enum for a Queue Group Index */
+static inline int
+accFromQgid(int qg_idx, const struct rte_acc_conf *acc_conf)
+{
+ int accQg[ACC200_NUM_QGRPS];
+ int NumQGroupsPerFn[NUM_ACC];
+ int acc, qgIdx, qgIndex = 0;
+ for (qgIdx = 0; qgIdx < ACC200_NUM_QGRPS; qgIdx++)
+ accQg[qgIdx] = 0;
+ NumQGroupsPerFn[UL_4G] = acc_conf->q_ul_4g.num_qgroups;
+ NumQGroupsPerFn[UL_5G] = acc_conf->q_ul_5g.num_qgroups;
+ NumQGroupsPerFn[DL_4G] = acc_conf->q_dl_4g.num_qgroups;
+ NumQGroupsPerFn[DL_5G] = acc_conf->q_dl_5g.num_qgroups;
+ NumQGroupsPerFn[FFT] = acc_conf->q_fft.num_qgroups;
+ for (acc = UL_4G; acc < NUM_ACC; acc++)
+ for (qgIdx = 0; qgIdx < NumQGroupsPerFn[acc]; qgIdx++)
+ accQg[qgIndex++] = acc;
+ acc = accQg[qg_idx];
+ return acc;
+}
+
/* Return the queue topology for a Queue Group Index */
static inline void
qtopFromAcc(struct rte_acc_queue_topology **qtop, int acc_enum,
@@ -75,6 +96,30 @@
*qtop = p_qtop;
}
+/* Return the AQ depth for a Queue Group Index */
+static inline int
+aqDepth(int qg_idx, struct rte_acc_conf *acc_conf)
+{
+ struct rte_acc_queue_topology *q_top = NULL;
+ int acc_enum = accFromQgid(qg_idx, acc_conf);
+ qtopFromAcc(&q_top, acc_enum, acc_conf);
+ if (unlikely(q_top == NULL))
+ return 0;
+ return q_top->aq_depth_log2;
+}
+
+/* Return the AQ depth for a Queue Group Index */
+static inline int
+aqNum(int qg_idx, struct rte_acc_conf *acc_conf)
+{
+ struct rte_acc_queue_topology *q_top = NULL;
+ int acc_enum = accFromQgid(qg_idx, acc_conf);
+ qtopFromAcc(&q_top, acc_enum, acc_conf);
+ if (unlikely(q_top == NULL))
+ return 0;
+ return q_top->num_aqs_per_groups;
+}
+
static void
initQTop(struct rte_acc_conf *acc_conf)
{
@@ -3740,3 +3785,411 @@ static int acc200_pci_probe(struct rte_pci_driver *pci_drv,
RTE_PMD_REGISTER_PCI_TABLE(ACC200PF_DRIVER_NAME, pci_id_acc200_pf_map);
RTE_PMD_REGISTER_PCI(ACC200VF_DRIVER_NAME, acc200_pci_vf_driver);
RTE_PMD_REGISTER_PCI_TABLE(ACC200VF_DRIVER_NAME, pci_id_acc200_vf_map);
+
+/* Initial configuration of a ACC200 device prior to running configure() */
+int
+rte_acc200_configure(const char *dev_name, struct rte_acc_conf *conf)
+{
+ rte_bbdev_log(INFO, "rte_acc200_configure");
+ uint32_t value, address, status;
+ int qg_idx, template_idx, vf_idx, acc, i;
+ struct rte_bbdev *bbdev = rte_bbdev_get_named_dev(dev_name);
+
+ /* Compile time checks */
+ RTE_BUILD_BUG_ON(sizeof(struct acc_dma_req_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(union acc_dma_desc) != 256);
+ RTE_BUILD_BUG_ON(sizeof(struct acc_fcw_td) != 24);
+ RTE_BUILD_BUG_ON(sizeof(struct acc_fcw_te) != 32);
+
+ if (bbdev == NULL) {
+ rte_bbdev_log(ERR,
+ "Invalid dev_name (%s), or device is not yet initialised",
+ dev_name);
+ return -ENODEV;
+ }
+ struct acc_device *d = bbdev->data->dev_private;
+
+ /* Store configuration */
+ rte_memcpy(&d->acc_conf, conf, sizeof(d->acc_conf));
+
+
+ /* Check we are already out of PG */
+ status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
+ if (status > 0) {
+ if (status != ACC200_PG_MASK_0) {
+ rte_bbdev_log(ERR, "Unexpected status %x %x",
+ status, ACC200_PG_MASK_0);
+ return -ENODEV;
+ }
+ /* Clock gate sections that will be un-PG */
+ acc_reg_write(d, HWPfHiClkGateHystReg, ACC200_CLK_DIS);
+ /* Un-PG required sections */
+ acc_reg_write(d, HWPfHiSectionPowerGatingReq,
+ ACC200_PG_MASK_1);
+ status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
+ if (status != ACC200_PG_MASK_1) {
+ rte_bbdev_log(ERR, "Unexpected status %x %x",
+ status, ACC200_PG_MASK_1);
+ return -ENODEV;
+ }
+ acc_reg_write(d, HWPfHiSectionPowerGatingReq,
+ ACC200_PG_MASK_2);
+ status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
+ if (status != ACC200_PG_MASK_2) {
+ rte_bbdev_log(ERR, "Unexpected status %x %x",
+ status, ACC200_PG_MASK_2);
+ return -ENODEV;
+ }
+ acc_reg_write(d, HWPfHiSectionPowerGatingReq,
+ ACC200_PG_MASK_3);
+ status = acc_reg_read(d, HWPfHiSectionPowerGatingAck);
+ if (status != ACC200_PG_MASK_3) {
+ rte_bbdev_log(ERR, "Unexpected status %x %x",
+ status, ACC200_PG_MASK_3);
+ return -ENODEV;
+ }
+ /* Enable clocks for all sections */
+ acc_reg_write(d, HWPfHiClkGateHystReg, ACC200_CLK_EN);
+ }
+
+ /* Explicitly releasing AXI as this may be stopped after PF FLR/BME */
+ address = HWPfDmaAxiControl;
+ value = 1;
+ acc_reg_write(d, address, value);
+
+ /* Set the fabric mode */
+ address = HWPfFabricM2iBufferReg;
+ value = ACC200_FABRIC_MODE;
+ acc_reg_write(d, address, value);
+
+ /* Set default descriptor signature */
+ address = HWPfDmaDescriptorSignatuture;
+ value = 0;
+ acc_reg_write(d, address, value);
+
+ /* Enable the Error Detection in DMA */
+ value = ACC200_CFG_DMA_ERROR;
+ address = HWPfDmaErrorDetectionEn;
+ acc_reg_write(d, address, value);
+
+ /* AXI Cache configuration */
+ value = ACC200_CFG_AXI_CACHE;
+ address = HWPfDmaAxcacheReg;
+ acc_reg_write(d, address, value);
+
+ /* Default DMA Configuration (Qmgr Enabled) */
+ address = HWPfDmaConfig0Reg;
+ value = 0;
+ acc_reg_write(d, address, value);
+ address = HWPfDmaQmanen;
+ value = 0;
+ acc_reg_write(d, address, value);
+
+ /* Default RLIM/ALEN configuration */
+ int rlim = 0;
+ int alen = 1;
+ int timestamp = 0;
+ address = HWPfDmaConfig1Reg;
+ value = (1 << 31) + (rlim << 8) + (timestamp << 6) + alen;
+ acc_reg_write(d, address, value);
+
+ /* Default FFT configuration */
+ address = HWPfFftConfig0;
+ value = ACC200_FFT_CFG_0;
+ acc_reg_write(d, address, value);
+
+ /* Configure DMA Qmanager addresses */
+ address = HWPfDmaQmgrAddrReg;
+ value = HWPfQmgrEgressQueuesTemplate;
+ acc_reg_write(d, address, value);
+
+ /* ===== Qmgr Configuration ===== */
+ /* Configuration of the AQueue Depth QMGR_GRP_0_DEPTH_LOG2 for UL */
+ int totalQgs = conf->q_ul_4g.num_qgroups +
+ conf->q_ul_5g.num_qgroups +
+ conf->q_dl_4g.num_qgroups +
+ conf->q_dl_5g.num_qgroups +
+ conf->q_fft.num_qgroups;
+ for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {
+ address = HWPfQmgrDepthLog2Grp +
+ ACC_BYTES_IN_WORD * qg_idx;
+ value = aqDepth(qg_idx, conf);
+ acc_reg_write(d, address, value);
+ address = HWPfQmgrTholdGrp +
+ ACC_BYTES_IN_WORD * qg_idx;
+ value = (1 << 16) + (1 << (aqDepth(qg_idx, conf) - 1));
+ acc_reg_write(d, address, value);
+ }
+
+ /* Template Priority in incremental order */
+ for (template_idx = 0; template_idx < ACC_NUM_TMPL;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg0Indx + ACC_BYTES_IN_WORD * template_idx;
+ value = ACC_TMPL_PRI_0;
+ acc_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg1Indx + ACC_BYTES_IN_WORD * template_idx;
+ value = ACC_TMPL_PRI_1;
+ acc_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg2indx + ACC_BYTES_IN_WORD * template_idx;
+ value = ACC_TMPL_PRI_2;
+ acc_reg_write(d, address, value);
+ address = HWPfQmgrGrpTmplateReg3Indx + ACC_BYTES_IN_WORD * template_idx;
+ value = ACC_TMPL_PRI_3;
+ acc_reg_write(d, address, value);
+ }
+
+ address = HWPfQmgrGrpPriority;
+ value = ACC200_CFG_QMGR_HI_P;
+ acc_reg_write(d, address, value);
+
+ /* Template Configuration */
+ for (template_idx = 0; template_idx < ACC_NUM_TMPL;
+ template_idx++) {
+ value = 0;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC_BYTES_IN_WORD * template_idx;
+ acc_reg_write(d, address, value);
+ }
+ /* 4GUL */
+ int numQgs = conf->q_ul_4g.num_qgroups;
+ int numQqsAcc = 0;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC200_SIG_UL_4G;
+ template_idx <= ACC200_SIG_UL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC_BYTES_IN_WORD * template_idx;
+ acc_reg_write(d, address, value);
+ }
+ /* 5GUL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_ul_5g.num_qgroups;
+ value = 0;
+ int numEngines = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC200_SIG_UL_5G;
+ template_idx <= ACC200_SIG_UL_5G_LAST;
+ template_idx++) {
+ /* Check engine power-on status */
+ address = HwPfFecUl5gIbDebugReg + ACC_ENGINE_OFFSET * template_idx;
+ status = (acc_reg_read(d, address) >> 4) & 0x7;
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC_BYTES_IN_WORD * template_idx;
+ if (status == 1) {
+ acc_reg_write(d, address, value);
+ numEngines++;
+ } else
+ acc_reg_write(d, address, 0);
+ }
+ printf("Number of 5GUL engines %d\n", numEngines);
+ /* 4GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_4g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC200_SIG_DL_4G;
+ template_idx <= ACC200_SIG_DL_4G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC_BYTES_IN_WORD * template_idx;
+ acc_reg_write(d, address, value);
+ }
+ /* 5GDL */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_dl_5g.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC200_SIG_DL_5G;
+ template_idx <= ACC200_SIG_DL_5G_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC_BYTES_IN_WORD * template_idx;
+ acc_reg_write(d, address, value);
+ }
+ /* FFT */
+ numQqsAcc += numQgs;
+ numQgs = conf->q_fft.num_qgroups;
+ value = 0;
+ for (qg_idx = numQqsAcc; qg_idx < (numQgs + numQqsAcc); qg_idx++)
+ value |= (1 << qg_idx);
+ for (template_idx = ACC200_SIG_FFT;
+ template_idx <= ACC200_SIG_FFT_LAST;
+ template_idx++) {
+ address = HWPfQmgrGrpTmplateReg4Indx
+ + ACC_BYTES_IN_WORD * template_idx;
+ acc_reg_write(d, address, value);
+ }
+
+ /* Queue Group Function mapping */
+ int qman_func_id[8] = {0, 2, 1, 3, 4, 0, 0, 0};
+ value = 0;
+ for (qg_idx = 0; qg_idx < ACC_NUM_QGRPS_PER_WORD; qg_idx++) {
+ acc = accFromQgid(qg_idx, conf);
+ value |= qman_func_id[acc] << (qg_idx * 4);
+ }
+ acc_reg_write(d, HWPfQmgrGrpFunction0, value);
+ value = 0;
+ for (qg_idx = 0; qg_idx < ACC_NUM_QGRPS_PER_WORD; qg_idx++) {
+ acc = accFromQgid(qg_idx + ACC_NUM_QGRPS_PER_WORD, conf);
+ value |= qman_func_id[acc] << (qg_idx * 4);
+ }
+ acc_reg_write(d, HWPfQmgrGrpFunction1, value);
+
+ /* Configuration of the Arbitration QGroup depth to 1 */
+ for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {
+ address = HWPfQmgrArbQDepthGrp +
+ ACC_BYTES_IN_WORD * qg_idx;
+ value = 0;
+ acc_reg_write(d, address, value);
+ }
+
+ /* This pointer to ARAM (256kB) is shifted by 2 (4B per register) */
+ uint32_t aram_address = 0;
+ for (qg_idx = 0; qg_idx < totalQgs; qg_idx++) {
+ for (vf_idx = 0; vf_idx < conf->num_vf_bundles; vf_idx++) {
+ address = HWPfQmgrVfBaseAddr + vf_idx
+ * ACC_BYTES_IN_WORD + qg_idx
+ * ACC_BYTES_IN_WORD * 64;
+ value = aram_address;
+ acc_reg_write(d, address, value);
+ /* Offset ARAM Address for next memory bank
+ * - increment of 4B
+ */
+ aram_address += aqNum(qg_idx, conf) *
+ (1 << aqDepth(qg_idx, conf));
+ }
+ }
+
+ if (aram_address > ACC200_WORDS_IN_ARAM_SIZE) {
+ rte_bbdev_log(ERR, "ARAM Configuration not fitting %d %d\n",
+ aram_address, ACC200_WORDS_IN_ARAM_SIZE);
+ return -EINVAL;
+ }
+
+ /* Performance tuning */
+ acc_reg_write(d, HWPfFabricI2Mdma_weight, 0x0FFF);
+ acc_reg_write(d, HWPfDma4gdlIbThld, 0x1f10);
+
+ /* ==== HI Configuration ==== */
+
+ /* No Info Ring/MSI by default */
+ address = HWPfHiInfoRingIntWrEnRegPf;
+ value = 0;
+ acc_reg_write(d, address, value);
+ address = HWPfHiCfgMsiIntWrEnRegPf;
+ value = 0xFFFFFFFF;
+ acc_reg_write(d, address, value);
+ /* Prevent Block on Transmit Error */
+ address = HWPfHiBlockTransmitOnErrorEn;
+ value = 0;
+ acc_reg_write(d, address, value);
+ /* Prevents to drop MSI */
+ address = HWPfHiMsiDropEnableReg;
+ value = 0;
+ acc_reg_write(d, address, value);
+ /* Set the PF Mode register */
+ address = HWPfHiPfMode;
+ value = (conf->pf_mode_en) ? ACC_PF_VAL : 0;
+ acc_reg_write(d, address, value);
+
+ /* QoS overflow init */
+ value = 1;
+ address = HWPfQosmonAEvalOverflow0;
+ acc_reg_write(d, address, value);
+ address = HWPfQosmonBEvalOverflow0;
+ acc_reg_write(d, address, value);
+
+ /* Configure the FFT RAM LUT */
+ uint32_t fft_lut[ACC200_FFT_RAM_SIZE] = {
+ 0x1FFFF, 0x1FFFF, 0x1FFFE, 0x1FFFA, 0x1FFF6, 0x1FFF1, 0x1FFEA, 0x1FFE2,
+ 0x1FFD9, 0x1FFCE, 0x1FFC2, 0x1FFB5, 0x1FFA7, 0x1FF98, 0x1FF87, 0x1FF75,
+ 0x1FF62, 0x1FF4E, 0x1FF38, 0x1FF21, 0x1FF09, 0x1FEF0, 0x1FED6, 0x1FEBA,
+ 0x1FE9D, 0x1FE7F, 0x1FE5F, 0x1FE3F, 0x1FE1D, 0x1FDFA, 0x1FDD5, 0x1FDB0,
+ 0x1FD89, 0x1FD61, 0x1FD38, 0x1FD0D, 0x1FCE1, 0x1FCB4, 0x1FC86, 0x1FC57,
+ 0x1FC26, 0x1FBF4, 0x1FBC1, 0x1FB8D, 0x1FB58, 0x1FB21, 0x1FAE9, 0x1FAB0,
+ 0x1FA75, 0x1FA3A, 0x1F9FD, 0x1F9BF, 0x1F980, 0x1F93F, 0x1F8FD, 0x1F8BA,
+ 0x1F876, 0x1F831, 0x1F7EA, 0x1F7A3, 0x1F75A, 0x1F70F, 0x1F6C4, 0x1F677,
+ 0x1F629, 0x1F5DA, 0x1F58A, 0x1F539, 0x1F4E6, 0x1F492, 0x1F43D, 0x1F3E7,
+ 0x1F38F, 0x1F337, 0x1F2DD, 0x1F281, 0x1F225, 0x1F1C8, 0x1F169, 0x1F109,
+ 0x1F0A8, 0x1F046, 0x1EFE2, 0x1EF7D, 0x1EF18, 0x1EEB0, 0x1EE48, 0x1EDDF,
+ 0x1ED74, 0x1ED08, 0x1EC9B, 0x1EC2D, 0x1EBBE, 0x1EB4D, 0x1EADB, 0x1EA68,
+ 0x1E9F4, 0x1E97F, 0x1E908, 0x1E891, 0x1E818, 0x1E79E, 0x1E722, 0x1E6A6,
+ 0x1E629, 0x1E5AA, 0x1E52A, 0x1E4A9, 0x1E427, 0x1E3A3, 0x1E31F, 0x1E299,
+ 0x1E212, 0x1E18A, 0x1E101, 0x1E076, 0x1DFEB, 0x1DF5E, 0x1dED0, 0x1DE41,
+ 0x1DDB1, 0x1DD20, 0x1DC8D, 0x1DBFA, 0x1DB65, 0x1DACF, 0x1DA38, 0x1D9A0,
+ 0x1D907, 0x1D86C, 0x1D7D1, 0x1D734, 0x1D696, 0x1D5F7, 0x1D557, 0x1D4B6,
+ 0x1D413, 0x1D370, 0x1D2CB, 0x1D225, 0x1D17E, 0x1D0D6, 0x1D02D, 0x1CF83,
+ 0x1CED8, 0x1CE2B, 0x1CD7E, 0x1CCCF, 0x1CC1F, 0x1CB6E, 0x1CABC, 0x1CA09,
+ 0x1C955, 0x1C89F, 0x1C7E9, 0x1C731, 0x1C679, 0x1C5BF, 0x1C504, 0x1C448,
+ 0x1C38B, 0x1C2CD, 0x1C20E, 0x1C14E, 0x1C08C, 0x1BFCA, 0x1BF06, 0x1BE42,
+ 0x1BD7C, 0x1BCB5, 0x1BBED, 0x1BB25, 0x1BA5B, 0x1B990, 0x1B8C4, 0x1B7F6,
+ 0x1B728, 0x1B659, 0x1B589, 0x1B4B7, 0x1B3E5, 0x1B311, 0x1B23D, 0x1B167,
+ 0x1B091, 0x1AFB9, 0x1AEE0, 0x1AE07, 0x1AD2C, 0x1AC50, 0x1AB73, 0x1AA95,
+ 0x1A9B6, 0x1A8D6, 0x1A7F6, 0x1A714, 0x1A631, 0x1A54D, 0x1A468, 0x1A382,
+ 0x1A29A, 0x1A1B2, 0x1A0C9, 0x19FDF, 0x19EF4, 0x19E08, 0x19D1B, 0x19C2D,
+ 0x19B3E, 0x19A4E, 0x1995D, 0x1986B, 0x19778, 0x19684, 0x1958F, 0x19499,
+ 0x193A2, 0x192AA, 0x191B1, 0x190B8, 0x18FBD, 0x18EC1, 0x18DC4, 0x18CC7,
+ 0x18BC8, 0x18AC8, 0x189C8, 0x188C6, 0x187C4, 0x186C1, 0x185BC, 0x184B7,
+ 0x183B1, 0x182AA, 0x181A2, 0x18099, 0x17F8F, 0x17E84, 0x17D78, 0x17C6C,
+ 0x17B5E, 0x17A4F, 0x17940, 0x17830, 0x1771E, 0x1760C, 0x174F9, 0x173E5,
+ 0x172D1, 0x171BB, 0x170A4, 0x16F8D, 0x16E74, 0x16D5B, 0x16C41, 0x16B26,
+ 0x16A0A, 0x168ED, 0x167CF, 0x166B1, 0x16592, 0x16471, 0x16350, 0x1622E,
+ 0x1610B, 0x15FE8, 0x15EC3, 0x15D9E, 0x15C78, 0x15B51, 0x15A29, 0x15900,
+ 0x157D7, 0x156AC, 0x15581, 0x15455, 0x15328, 0x151FB, 0x150CC, 0x14F9D,
+ 0x14E6D, 0x14D3C, 0x14C0A, 0x14AD8, 0x149A4, 0x14870, 0x1473B, 0x14606,
+ 0x144CF, 0x14398, 0x14260, 0x14127, 0x13FEE, 0x13EB3, 0x13D78, 0x13C3C,
+ 0x13B00, 0x139C2, 0x13884, 0x13745, 0x13606, 0x134C5, 0x13384, 0x13242,
+ 0x130FF, 0x12FBC, 0x12E78, 0x12D33, 0x12BEE, 0x12AA7, 0x12960, 0x12819,
+ 0x126D0, 0x12587, 0x1243D, 0x122F3, 0x121A8, 0x1205C, 0x11F0F, 0x11DC2,
+ 0x11C74, 0x11B25, 0x119D6, 0x11886, 0x11735, 0x115E3, 0x11491, 0x1133F,
+ 0x111EB, 0x11097, 0x10F42, 0x10dED, 0x10C97, 0x10B40, 0x109E9, 0x10891,
+ 0x10738, 0x105DF, 0x10485, 0x1032B, 0x101D0, 0x10074, 0x0FF18, 0x0FDBB,
+ 0x0FC5D, 0x0FAFF, 0x0F9A0, 0x0F841, 0x0F6E1, 0x0F580, 0x0F41F, 0x0F2BD,
+ 0x0F15B, 0x0EFF8, 0x0EE94, 0x0ED30, 0x0EBCC, 0x0EA67, 0x0E901, 0x0E79A,
+ 0x0E633, 0x0E4CC, 0x0E364, 0x0E1FB, 0x0E092, 0x0DF29, 0x0DDBE, 0x0DC54,
+ 0x0DAE9, 0x0D97D, 0x0D810, 0x0D6A4, 0x0D536, 0x0D3C8, 0x0D25A, 0x0D0EB,
+ 0x0CF7C, 0x0CE0C, 0x0CC9C, 0x0CB2B, 0x0C9B9, 0x0C847, 0x0C6D5, 0x0C562,
+ 0x0C3EF, 0x0C27B, 0x0C107, 0x0BF92, 0x0BE1D, 0x0BCA8, 0x0BB32, 0x0B9BB,
+ 0x0B844, 0x0B6CD, 0x0B555, 0x0B3DD, 0x0B264, 0x0B0EB, 0x0AF71, 0x0ADF7,
+ 0x0AC7D, 0x0AB02, 0x0A987, 0x0A80B, 0x0A68F, 0x0A513, 0x0A396, 0x0A219,
+ 0x0A09B, 0x09F1D, 0x09D9E, 0x09C20, 0x09AA1, 0x09921, 0x097A1, 0x09621,
+ 0x094A0, 0x0931F, 0x0919E, 0x0901C, 0x08E9A, 0x08D18, 0x08B95, 0x08A12,
+ 0x0888F, 0x0870B, 0x08587, 0x08402, 0x0827E, 0x080F9, 0x07F73, 0x07DEE,
+ 0x07C68, 0x07AE2, 0x0795B, 0x077D4, 0x0764D, 0x074C6, 0x0733E, 0x071B6,
+ 0x0702E, 0x06EA6, 0x06D1D, 0x06B94, 0x06A0B, 0x06881, 0x066F7, 0x0656D,
+ 0x063E3, 0x06258, 0x060CE, 0x05F43, 0x05DB7, 0x05C2C, 0x05AA0, 0x05914,
+ 0x05788, 0x055FC, 0x0546F, 0x052E3, 0x05156, 0x04FC9, 0x04E3B, 0x04CAE,
+ 0x04B20, 0x04992, 0x04804, 0x04676, 0x044E8, 0x04359, 0x041CB, 0x0403C,
+ 0x03EAD, 0x03D1D, 0x03B8E, 0x039FF, 0x0386F, 0x036DF, 0x0354F, 0x033BF,
+ 0x0322F, 0x0309F, 0x02F0F, 0x02D7E, 0x02BEE, 0x02A5D, 0x028CC, 0x0273B,
+ 0x025AA, 0x02419, 0x02288, 0x020F7, 0x01F65, 0x01DD4, 0x01C43, 0x01AB1,
+ 0x0191F, 0x0178E, 0x015FC, 0x0146A, 0x012D8, 0x01147, 0x00FB5, 0x00E23,
+ 0x00C91, 0x00AFF, 0x0096D, 0x007DB, 0x00648, 0x004B6, 0x00324, 0x00192};
+
+ acc_reg_write(d, HWPfFftRamPageAccess, ACC200_FFT_RAM_EN + 64);
+ for (i = 0; i < ACC200_FFT_RAM_SIZE; i++)
+ acc_reg_write(d, HWPfFftRamOff + i * 4, fft_lut[i]);
+ acc_reg_write(d, HWPfFftRamPageAccess, ACC200_FFT_RAM_DIS);
+
+ /* Enabling AQueues through the Queue hierarchy*/
+ for (vf_idx = 0; vf_idx < ACC200_NUM_VFS; vf_idx++) {
+ for (qg_idx = 0; qg_idx < ACC200_NUM_QGRPS; qg_idx++) {
+ value = 0;
+ if (vf_idx < conf->num_vf_bundles &&
+ qg_idx < totalQgs)
+ value = (1 << aqNum(qg_idx, conf)) - 1;
+ address = HWPfQmgrAqEnableVf
+ + vf_idx * ACC_BYTES_IN_WORD;
+ value += (qg_idx << 16);
+ acc_reg_write(d, address, value);
+ }
+ }
+
+ rte_bbdev_log_debug("PF Tip configuration complete for %s", dev_name);
+ return 0;
+}
@@ -6,4 +6,5 @@ EXPERIMENTAL {
global:
rte_acc10x_configure;
+ rte_acc200_configure;
};