[v3] net/iavf: fix QFI field bit check for GTPU EH

Message ID 20211008104143.236289-1-junfeng.guo@intel.com (mailing list archive)
State Accepted, archived
Delegated to: Qi Zhang
Headers
Series [v3] net/iavf: fix QFI field bit check for GTPU EH |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-broadcom-Functional success Functional Testing PASS
ci/iol-aarch64-compile-testing success Testing PASS
ci/iol-broadcom-Performance success Performance Testing PASS
ci/iol-intel-Functional success Functional Testing PASS
ci/iol-intel-Performance success Performance Testing PASS
ci/github-robot: build success github build: passed
ci/iol-x86_64-unit-testing fail Testing issues
ci/iol-x86_64-compile-testing success Testing PASS
ci/iol-mellanox-Performance success Performance Testing PASS
ci/Intel-compilation success Compilation OK
ci/intel-Testing success Testing PASS

Commit Message

Junfeng Guo Oct. 8, 2021, 10:41 a.m. UTC
  If GTPU Extionsion header has no pdu_type setting, the parsed value of
gtp_psc_spec->hdr.type will be 0, which is same as IAVF_GTPU_EH_DWLINK.
Thus, for this case, we should check gtp_psc_mask->hdr.type instead,
to set QFI field bit of GTPU_EH first.

Fixes: cd212c466992 ("net/iavf: fix QFI fields of GTPU UL/DL for flow director")
Cc: stable@dpdk.org

Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
---
 drivers/net/iavf/iavf_fdir.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
  

Comments

Qi Zhang Oct. 8, 2021, 6:09 a.m. UTC | #1
> -----Original Message-----
> From: Guo, Junfeng <junfeng.guo@intel.com>
> Sent: Friday, October 8, 2021 6:42 PM
> To: Zhang, Qi Z <qi.z.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>;
> Xing, Beilei <beilei.xing@intel.com>
> Cc: dev@dpdk.org; Yigit, Ferruh <ferruh.yigit@intel.com>; Guo, Junfeng
> <junfeng.guo@intel.com>; stable@dpdk.org
> Subject: [PATCH v3] net/iavf: fix QFI field bit check for GTPU EH
> 
> If GTPU Extionsion header has no pdu_type setting, the parsed value of
> gtp_psc_spec->hdr.type will be 0, which is same as IAVF_GTPU_EH_DWLINK.
> Thus, for this case, we should check gtp_psc_mask->hdr.type instead, to set
> QFI field bit of GTPU_EH first.
> 
> Fixes: cd212c466992 ("net/iavf: fix QFI fields of GTPU UL/DL for flow director")
> Cc: stable@dpdk.org
> 
> Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>

Acked-by: Qi Zhang <qi.z.zhang@intel.com>

Applied to dpdk-next-net-intel.

Thanks
Qi
  
David Marchand Oct. 8, 2021, 11:01 a.m. UTC | #2
On Fri, Oct 8, 2021 at 8:09 AM Zhang, Qi Z <qi.z.zhang@intel.com> wrote:
> > -----Original Message-----
> > From: Guo, Junfeng <junfeng.guo@intel.com>
> > Sent: Friday, October 8, 2021 6:42 PM
> > To: Zhang, Qi Z <qi.z.zhang@intel.com>; Wu, Jingjing <jingjing.wu@intel.com>;
> > Xing, Beilei <beilei.xing@intel.com>
> > Cc: dev@dpdk.org; Yigit, Ferruh <ferruh.yigit@intel.com>; Guo, Junfeng
> > <junfeng.guo@intel.com>; stable@dpdk.org
> > Subject: [PATCH v3] net/iavf: fix QFI field bit check for GTPU EH
> >
> > If GTPU Extionsion header has no pdu_type setting, the parsed value of

extension.

> > gtp_psc_spec->hdr.type will be 0, which is same as IAVF_GTPU_EH_DWLINK.
> > Thus, for this case, we should check gtp_psc_mask->hdr.type instead, to set
> > QFI field bit of GTPU_EH first.
> >
> > Fixes: cd212c466992 ("net/iavf: fix QFI fields of GTPU UL/DL for flow director")

This patch fixes a 3 weeks old patch that was itself fixing.
    Fixes: 78e8a87f6324 ("net/iavf: fix GTPU UL and DL support for
flow director")

I hope all tests are now fine.

> > Cc: stable@dpdk.org
> >
> > Signed-off-by: Junfeng Guo <junfeng.guo@intel.com>
>
> Acked-by: Qi Zhang <qi.z.zhang@intel.com>
>
> Applied to dpdk-next-net-intel.
  

Patch

diff --git a/drivers/net/iavf/iavf_fdir.c b/drivers/net/iavf/iavf_fdir.c
index ea2b692712..ea99806330 100644
--- a/drivers/net/iavf/iavf_fdir.c
+++ b/drivers/net/iavf/iavf_fdir.c
@@ -1172,7 +1172,10 @@  iavf_fdir_parse_pattern(__rte_unused struct iavf_adapter *ad,
 			if (gtp_psc_spec && gtp_psc_mask) {
 				if (gtp_psc_mask->hdr.qfi == 0x3F) {
 					input_set |= IAVF_INSET_GTPU_QFI;
-					if (gtp_psc_spec->hdr.type ==
+					if (!gtp_psc_mask->hdr.type)
+						VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr,
+										 GTPU_EH, QFI);
+					else if (gtp_psc_spec->hdr.type ==
 								IAVF_GTPU_EH_UPLINK)
 						VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr,
 										 GTPU_UP, QFI);
@@ -1180,9 +1183,6 @@  iavf_fdir_parse_pattern(__rte_unused struct iavf_adapter *ad,
 								IAVF_GTPU_EH_DWLINK)
 						VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr,
 										 GTPU_DWN, QFI);
-					else
-						VIRTCHNL_ADD_PROTO_HDR_FIELD_BIT(hdr,
-										 GTPU_EH, QFI);
 				}
 
 				rte_memcpy(hdr->buffer, gtp_psc_spec,