net/cnxk: fix default MCAM allocation size

Message ID 20210706081918.1596477-1-psatheesh@marvell.com (mailing list archive)
State Accepted, archived
Delegated to: Jerin Jacob
Headers
Series net/cnxk: fix default MCAM allocation size |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/iol-testing warning apply patch failure
ci/Intel-compilation warning apply issues

Commit Message

Satheesh Paul Antonysamy July 6, 2021, 8:19 a.m. UTC
  From: Satheesh Paul <psatheesh@marvell.com>

Preallocation of MCAM entries is not valid anymore since the
AF side MCAM allocation scheme has changed. This patch disables
preallocation by changing the default MCAM preallocation size
from 8 to 1.

Fixes: 168c59cfe42 ("net/octeontx2: add flow MCAM utility functions")

Signed-off-by: Satheesh Paul <psatheesh@marvell.com>
---
 drivers/net/cnxk/cnxk_ethdev_devargs.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
  

Comments

Jerin Jacob July 12, 2021, 4:06 p.m. UTC | #1
On Tue, Jul 6, 2021 at 1:49 PM <psatheesh@marvell.com> wrote:
>
> From: Satheesh Paul <psatheesh@marvell.com>
>
> Preallocation of MCAM entries is not valid anymore since the
> AF side MCAM allocation scheme has changed. This patch disables
> preallocation by changing the default MCAM preallocation size
> from 8 to 1.
>
> Fixes: 168c59cfe42 ("net/octeontx2: add flow MCAM utility functions")
>
> Signed-off-by: Satheesh Paul <psatheesh@marvell.com>

Acked-by: Jerin Jacob <jerinj@marvell.com>
Applied to dpdk-next-net-mrvl/for-next-net. Thanks
> ---
>  drivers/net/cnxk/cnxk_ethdev_devargs.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
> index c76b6281c..7f20e9228 100644
> --- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
> +++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
> @@ -116,7 +116,7 @@ cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
>  {
>         uint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64;
>         uint16_t sqb_count = CNXK_NIX_TX_MAX_SQB;
> -       uint16_t flow_prealloc_size = 8;
> +       uint16_t flow_prealloc_size = 1;
>         uint16_t switch_header_type = 0;
>         uint16_t flow_max_priority = 3;
>         uint16_t rss_tag_as_xor = 0;
> --
> 2.25.4
>
  

Patch

diff --git a/drivers/net/cnxk/cnxk_ethdev_devargs.c b/drivers/net/cnxk/cnxk_ethdev_devargs.c
index c76b6281c..7f20e9228 100644
--- a/drivers/net/cnxk/cnxk_ethdev_devargs.c
+++ b/drivers/net/cnxk/cnxk_ethdev_devargs.c
@@ -116,7 +116,7 @@  cnxk_ethdev_parse_devargs(struct rte_devargs *devargs, struct cnxk_eth_dev *dev)
 {
 	uint16_t reta_sz = ROC_NIX_RSS_RETA_SZ_64;
 	uint16_t sqb_count = CNXK_NIX_TX_MAX_SQB;
-	uint16_t flow_prealloc_size = 8;
+	uint16_t flow_prealloc_size = 1;
 	uint16_t switch_header_type = 0;
 	uint16_t flow_max_priority = 3;
 	uint16_t rss_tag_as_xor = 0;