[v2,1/3] bus/pci: enable PCI master in command register
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Commit Message
This adds the support to set 'Bus Master Enable' bit in the PCI command
register.
Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
Tested-by: Qi Zhang <qi.z.zhang@intel.com>
---
drivers/bus/pci/pci_common.c | 20 ++++++++++++++++++++
drivers/bus/pci/rte_bus_pci.h | 12 ++++++++++++
drivers/bus/pci/version.map | 1 +
lib/pci/rte_pci.h | 4 ++++
4 files changed, 37 insertions(+)
Comments
On 22/04/2021 02:18, Haiyue Wang wrote:
> This adds the support to set 'Bus Master Enable' bit in the PCI command
> register.
>
> Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
> Tested-by: Qi Zhang <qi.z.zhang@intel.com>
> ---
> drivers/bus/pci/pci_common.c | 20 ++++++++++++++++++++
> drivers/bus/pci/rte_bus_pci.h | 12 ++++++++++++
> drivers/bus/pci/version.map | 1 +
> lib/pci/rte_pci.h | 4 ++++
> 4 files changed, 37 insertions(+)
>
> diff --git a/drivers/bus/pci/pci_common.c b/drivers/bus/pci/pci_common.c
> index ee7f96635..b631cb9c7 100644
> --- a/drivers/bus/pci/pci_common.c
> +++ b/drivers/bus/pci/pci_common.c
> @@ -746,6 +746,26 @@ rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap)
> return 0;
> }
>
> +int
> +rte_pci_enable_bus_master(struct rte_pci_device *dev)
> +{
> + uint16_t cmd;
> +
> + if (rte_pci_read_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {
> + RTE_LOG(ERR, EAL, "error in reading PCI command register\n");
> + return -1;
> + }
> +
> + cmd |= RTE_PCI_COMMAND_MASTER;
> +
> + if (rte_pci_write_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {
> + RTE_LOG(ERR, EAL, "error in writing PCI command register\n");
> + return -1;
> + }
> +
> + return 0;
> +}
> +
> struct rte_pci_bus rte_pci_bus = {
> .bus = {
> .scan = rte_pci_scan,
> diff --git a/drivers/bus/pci/rte_bus_pci.h b/drivers/bus/pci/rte_bus_pci.h
> index 64886b473..83caf477b 100644
> --- a/drivers/bus/pci/rte_bus_pci.h
> +++ b/drivers/bus/pci/rte_bus_pci.h
> @@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f);
> __rte_experimental
> off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
>
> +/**
> + * Enables Bus Master for device's PCI command register.
> + *
> + * @param dev
> + * A pointer to rte_pci_device structure.
> + *
> + * @return
> + * 0 on success, -1 on error in PCI config space read/write.
> + */
> +__rte_experimental
> +int rte_pci_enable_bus_master(struct rte_pci_device *dev);
> +
> /**
> * Register a PCI driver.
> *
> diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map
> index f33ed0abd..b271e48a8 100644
> --- a/drivers/bus/pci/version.map
> +++ b/drivers/bus/pci/version.map
> @@ -20,5 +20,6 @@ DPDK_21 {
> EXPERIMENTAL {
> global:
>
Please annotate when the symbol was added.
> + rte_pci_enable_bus_master;
> rte_pci_find_ext_capability;
> };
> diff --git a/lib/pci/rte_pci.h b/lib/pci/rte_pci.h
> index a8f8e404a..1f33d687f 100644
> --- a/lib/pci/rte_pci.h
> +++ b/lib/pci/rte_pci.h
> @@ -32,6 +32,10 @@ extern "C" {
>
> #define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
> #define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
> +#define RTE_PCI_COMMAND 0x04 /* 16 bits */
> +
> +/* PCI Command Register */
> +#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */
>
> /* PCI Express capability registers */
> #define RTE_PCI_EXP_DEVCTL 8 /* Device Control */
>
> -----Original Message-----
> From: Kinsella, Ray <mdr@ashroe.eu>
> Sent: Friday, April 23, 2021 18:44
> To: Wang, Haiyue <haiyue.wang@intel.com>; dev@dpdk.org
> Cc: Zhang, Qi Z <qi.z.zhang@intel.com>; Wang, Liang-min <liang-min.wang@intel.com>; Neil Horman
> <nhorman@tuxdriver.com>; Gaetan Rivet <grive@u256.net>
> Subject: Re: [PATCH v2 1/3] bus/pci: enable PCI master in command register
>
>
>
> On 22/04/2021 02:18, Haiyue Wang wrote:
> > This adds the support to set 'Bus Master Enable' bit in the PCI command
> > register.
> >
> > Signed-off-by: Haiyue Wang <haiyue.wang@intel.com>
> > Tested-by: Qi Zhang <qi.z.zhang@intel.com>
> > ---
> > drivers/bus/pci/pci_common.c | 20 ++++++++++++++++++++
> > drivers/bus/pci/rte_bus_pci.h | 12 ++++++++++++
> > drivers/bus/pci/version.map | 1 +
> > lib/pci/rte_pci.h | 4 ++++
> > 4 files changed, 37 insertions(+)
> >
> > *
> > diff --git a/drivers/bus/pci/version.map b/drivers/bus/pci/version.map
> > index f33ed0abd..b271e48a8 100644
> > --- a/drivers/bus/pci/version.map
> > +++ b/drivers/bus/pci/version.map
> > @@ -20,5 +20,6 @@ DPDK_21 {
> > EXPERIMENTAL {
> > global:
> >
>
> Please annotate when the symbol was added.
>
Fixed in v3.
> >
@@ -746,6 +746,26 @@ rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap)
return 0;
}
+int
+rte_pci_enable_bus_master(struct rte_pci_device *dev)
+{
+ uint16_t cmd;
+
+ if (rte_pci_read_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {
+ RTE_LOG(ERR, EAL, "error in reading PCI command register\n");
+ return -1;
+ }
+
+ cmd |= RTE_PCI_COMMAND_MASTER;
+
+ if (rte_pci_write_config(dev, &cmd, sizeof(cmd), RTE_PCI_COMMAND) < 0) {
+ RTE_LOG(ERR, EAL, "error in writing PCI command register\n");
+ return -1;
+ }
+
+ return 0;
+}
+
struct rte_pci_bus rte_pci_bus = {
.bus = {
.scan = rte_pci_scan,
@@ -249,6 +249,18 @@ void rte_pci_dump(FILE *f);
__rte_experimental
off_t rte_pci_find_ext_capability(struct rte_pci_device *dev, uint32_t cap);
+/**
+ * Enables Bus Master for device's PCI command register.
+ *
+ * @param dev
+ * A pointer to rte_pci_device structure.
+ *
+ * @return
+ * 0 on success, -1 on error in PCI config space read/write.
+ */
+__rte_experimental
+int rte_pci_enable_bus_master(struct rte_pci_device *dev);
+
/**
* Register a PCI driver.
*
@@ -20,5 +20,6 @@ DPDK_21 {
EXPERIMENTAL {
global:
+ rte_pci_enable_bus_master;
rte_pci_find_ext_capability;
};
@@ -32,6 +32,10 @@ extern "C" {
#define RTE_PCI_VENDOR_ID 0x00 /* 16 bits */
#define RTE_PCI_DEVICE_ID 0x02 /* 16 bits */
+#define RTE_PCI_COMMAND 0x04 /* 16 bits */
+
+/* PCI Command Register */
+#define RTE_PCI_COMMAND_MASTER 0x4 /* Bus Master Enable */
/* PCI Express capability registers */
#define RTE_PCI_EXP_DEVCTL 8 /* Device Control */