diff mbox series

[2/3] common/mlx5: read checksum capability from DevX

Message ID 20210421163441.17240-3-talshn@nvidia.com (mailing list archive)
State Accepted, archived
Delegated to: Raslan Darawsheh
Headers
Series mlx5 - support checksum offloads on Windows |

Checks

Context Check Description
ci/checkpatch success coding style OK

Commit Message

Tal Shnaiderman April 21, 2021, 4:34 p.m. UTC 
  mlx5 in Windows needs the hca capability csum_cap
to query the NIC for checksum offloading support

Added the capability as part of the capabilities
queried by the PMD using DevX.

Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
Acked-by: Matan Azrad <matan@nvidia.com>
---
 drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
 drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
 2 files changed, 3 insertions(+)

Comments

Odi Assli April 22, 2021, 10:17 a.m. UTC | #1 
> Subject: [PATCH 2/3] common/mlx5: read checksum capability from DevX
> 
> mlx5 in Windows needs the hca capability csum_cap to query the NIC for
> checksum offloading support
> 
> Added the capability as part of the capabilities queried by the PMD using
> DevX.
> 
> Signed-off-by: Tal Shnaiderman <talshn@nvidia.com>
> Acked-by: Matan Azrad <matan@nvidia.com>
> ---
>  drivers/common/mlx5/mlx5_devx_cmds.c | 2 ++
> drivers/common/mlx5/mlx5_devx_cmds.h | 1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c
> b/drivers/common/mlx5/mlx5_devx_cmds.c
> index 268bcd0d99..d2e4ab33a2 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.c
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.c
> @@ -837,6 +837,8 @@ mlx5_devx_cmd_query_hca_attr(void *ctx,
>  	hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
>  	attr->wqe_vlan_insert =
> MLX5_GET(per_protocol_networking_offload_caps,
>  					 hcattr, wqe_vlan_insert);
> +	attr->csum_cap =
> MLX5_GET(per_protocol_networking_offload_caps,
> +					 hcattr, csum_cap);
>  	attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps,
> hcattr,
>  				 lro_cap);
>  	attr->tunnel_lro_gre =
> MLX5_GET(per_protocol_networking_offload_caps,
> diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h
> b/drivers/common/mlx5/mlx5_devx_cmds.h
> index 67b5f771c6..1fb9130e51 100644
> --- a/drivers/common/mlx5/mlx5_devx_cmds.h
> +++ b/drivers/common/mlx5/mlx5_devx_cmds.h
> @@ -92,6 +92,7 @@ struct mlx5_hca_attr {
>  	uint32_t eth_net_offloads:1;
>  	uint32_t eth_virt:1;
>  	uint32_t wqe_vlan_insert:1;
> +	uint32_t csum_cap:1;
>  	uint32_t wqe_inline_mode:2;
>  	uint32_t vport_inline_mode:3;
>  	uint32_t tunnel_stateless_geneve_rx:1;
> --
> 2.16.1.windows.4

Tested-by: Odi Assli <odia@nvidia.com>
diff mbox series

Patch

diff --git a/drivers/common/mlx5/mlx5_devx_cmds.c b/drivers/common/mlx5/mlx5_devx_cmds.c
index 268bcd0d99..d2e4ab33a2 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.c
+++ b/drivers/common/mlx5/mlx5_devx_cmds.c
@@ -837,6 +837,8 @@  mlx5_devx_cmd_query_hca_attr(void *ctx,
 	hcattr = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
 	attr->wqe_vlan_insert = MLX5_GET(per_protocol_networking_offload_caps,
 					 hcattr, wqe_vlan_insert);
+	attr->csum_cap = MLX5_GET(per_protocol_networking_offload_caps,
+					 hcattr, csum_cap);
 	attr->lro_cap = MLX5_GET(per_protocol_networking_offload_caps, hcattr,
 				 lro_cap);
 	attr->tunnel_lro_gre = MLX5_GET(per_protocol_networking_offload_caps,
diff --git a/drivers/common/mlx5/mlx5_devx_cmds.h b/drivers/common/mlx5/mlx5_devx_cmds.h
index 67b5f771c6..1fb9130e51 100644
--- a/drivers/common/mlx5/mlx5_devx_cmds.h
+++ b/drivers/common/mlx5/mlx5_devx_cmds.h
@@ -92,6 +92,7 @@  struct mlx5_hca_attr {
 	uint32_t eth_net_offloads:1;
 	uint32_t eth_virt:1;
 	uint32_t wqe_vlan_insert:1;
+	uint32_t csum_cap:1;
 	uint32_t wqe_inline_mode:2;
 	uint32_t vport_inline_mode:3;
 	uint32_t tunnel_stateless_geneve_rx:1;