diff mbox series

[v3,26/26] event/dlb: move rte config defines to runtime devargs

Message ID 1618344896-2090-27-git-send-email-timothy.mcdaniel@intel.com (mailing list archive)
State Superseded, archived
Delegated to: Jerin Jacob
Headers
Series Add DLB V2.5 |

Checks

Context Check Description
ci/checkpatch success coding style OK
ci/Intel-compilation fail Compilation issues
ci/intel-Testing success Testing PASS
ci/iol-testing fail Testing issues

Commit Message

Timothy McDaniel April 13, 2021, 8:14 p.m. UTC 
  The new devarg names and their default values
are listed below. The defaults have not changed, and
none of these parameters are accessed in the fast path.

poll_interval=1000
sw_credit_quantai=32
default_depth_thresh=256

Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
---
 config/rte_config.h            |   3 -
 drivers/event/dlb/dlb2.c       | 109 +++++++++++++++++++++++++++++++--
 drivers/event/dlb/dlb2_priv.h  |  14 +++++
 drivers/event/dlb/pf/dlb2_pf.c |   5 +-
 4 files changed, 121 insertions(+), 10 deletions(-)

Comments

Jerin Jacob April 14, 2021, 7:11 p.m. UTC | #1 
On Wed, Apr 14, 2021 at 1:49 AM Timothy McDaniel
<timothy.mcdaniel@intel.com> wrote:
>
> The new devarg names and their default values
> are listed below. The defaults have not changed, and
> none of these parameters are accessed in the fast path.
>
> poll_interval=1000
> sw_credit_quantai=32
> default_depth_thresh=256
>
> Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>

Please check CI failures. Please make this practice to see the fate of
the patch by CI after the patch submission to avoid additional delay
in merging the patch.

http://patches.dpdk.org/project/dpdk/patch/1618344896-2090-27-git-send-email-timothy.mcdaniel@intel.com/
Timothy McDaniel April 14, 2021, 7:38 p.m. UTC | #2 
> -----Original Message-----
> From: Jerin Jacob <jerinjacobk@gmail.com>
> Sent: Wednesday, April 14, 2021 2:11 PM
> To: McDaniel, Timothy <timothy.mcdaniel@intel.com>
> Cc: dpdk-dev <dev@dpdk.org>; Carrillo, Erik G <erik.g.carrillo@intel.com>; Gage
> Eads <gage.eads@intel.com>; Van Haaren, Harry
> <harry.van.haaren@intel.com>; Jerin Jacob <jerinj@marvell.com>; Thomas
> Monjalon <thomas@monjalon.net>
> Subject: Re: [dpdk-dev] [PATCH v3 26/26] event/dlb: move rte config defines to
> runtime devargs
> 
> On Wed, Apr 14, 2021 at 1:49 AM Timothy McDaniel
> <timothy.mcdaniel@intel.com> wrote:
> >
> > The new devarg names and their default values
> > are listed below. The defaults have not changed, and
> > none of these parameters are accessed in the fast path.
> >
> > poll_interval=1000
> > sw_credit_quantai=32
> > default_depth_thresh=256
> >
> > Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
> 
> Please check CI failures. Please make this practice to see the fate of
> the patch by CI after the patch submission to avoid additional delay
> in merging the patch.
> 
> http://patches.dpdk.org/project/dpdk/patch/1618344896-2090-27-git-send-
> email-timothy.mcdaniel@intel.com/

The failures seems to be 
1) with a reference to dlb2 documentation  in the 20.11 release notes
2) an apply failure with the dqueue optimization patch. It requires the DLB 25 patches
to have been previously installed. I added a depends-on line to its cover sheet, but that
did not seem to help
3) there are many false positives reported by check patches, most spelling related. I do
not see any real issues there

As for the code cleanup, this was very minor, such as not including mbox.h, which we do not use.
Not sure it warrants its own patch, and I'm not sure I can even identify the other minor cleanups, if any.

Thanks,
Tim
Jerin Jacob April 14, 2021, 7:52 p.m. UTC | #3 
On Thu, Apr 15, 2021 at 1:09 AM McDaniel, Timothy
<timothy.mcdaniel@intel.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Jerin Jacob <jerinjacobk@gmail.com>
> > Sent: Wednesday, April 14, 2021 2:11 PM
> > To: McDaniel, Timothy <timothy.mcdaniel@intel.com>
> > Cc: dpdk-dev <dev@dpdk.org>; Carrillo, Erik G <erik.g.carrillo@intel.com>; Gage
> > Eads <gage.eads@intel.com>; Van Haaren, Harry
> > <harry.van.haaren@intel.com>; Jerin Jacob <jerinj@marvell.com>; Thomas
> > Monjalon <thomas@monjalon.net>
> > Subject: Re: [dpdk-dev] [PATCH v3 26/26] event/dlb: move rte config defines to
> > runtime devargs
> >
> > On Wed, Apr 14, 2021 at 1:49 AM Timothy McDaniel
> > <timothy.mcdaniel@intel.com> wrote:
> > >
> > > The new devarg names and their default values
> > > are listed below. The defaults have not changed, and
> > > none of these parameters are accessed in the fast path.
> > >
> > > poll_interval=1000
> > > sw_credit_quantai=32
> > > default_depth_thresh=256
> > >
> > > Signed-off-by: Timothy McDaniel <timothy.mcdaniel@intel.com>
> >
> > Please check CI failures. Please make this practice to see the fate of
> > the patch by CI after the patch submission to avoid additional delay
> > in merging the patch.
> >
> > http://patches.dpdk.org/project/dpdk/patch/1618344896-2090-27-git-send-
> > email-timothy.mcdaniel@intel.com/
>
> The failures seems to be
> 1) with a reference to dlb2 documentation  in the 20.11 release notes

Please update the 20.11 release notes to fix the issue.



> 2) an apply failure with the dqueue optimization patch. It requires the DLB 25 patches
> to have been previously installed. I added a depends-on line to its cover sheet, but that
> did not seem to help
> 3) there are many false positives reported by check patches, most spelling related. I do
> not see any real issues there
>
> As for the code cleanup, this was very minor, such as not including mbox.h, which we do not use.
> Not sure it warrants its own patch, and I'm not sure I can even identify the other minor cleanups, if any.
>
> Thanks,
> Tim
>
diff mbox series

Patch

diff --git a/config/rte_config.h b/config/rte_config.h
index 1aa852cd7..836aca3c2 100644
--- a/config/rte_config.h
+++ b/config/rte_config.h
@@ -140,9 +140,6 @@ 
 #define RTE_LIBRTE_QEDE_FW ""
 
 /* DLB defines */
-#define RTE_LIBRTE_PMD_DLB_POLL_INTERVAL 1000
 #undef RTE_LIBRTE_PMD_DLB_QUELL_STATS
-#define RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA 32
-#define RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH 256
 
 #endif /* _RTE_CONFIG_H_ */
diff --git a/drivers/event/dlb/dlb2.c b/drivers/event/dlb/dlb2.c
index e5def9357..818b1c367 100644
--- a/drivers/event/dlb/dlb2.c
+++ b/drivers/event/dlb/dlb2.c
@@ -315,6 +315,66 @@  set_cos(const char *key __rte_unused,
 	return 0;
 }
 
+static int
+set_poll_interval(const char *key __rte_unused,
+	const char *value,
+	void *opaque)
+{
+	int *poll_interval = opaque;
+	int ret;
+
+	if (value == NULL || opaque == NULL) {
+		DLB2_LOG_ERR("NULL pointer\n");
+		return -EINVAL;
+	}
+
+	ret = dlb2_string_to_int(poll_interval, value);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int
+set_sw_credit_quanta(const char *key __rte_unused,
+	const char *value,
+	void *opaque)
+{
+	int *sw_credit_quanta = opaque;
+	int ret;
+
+	if (value == NULL || opaque == NULL) {
+		DLB2_LOG_ERR("NULL pointer\n");
+		return -EINVAL;
+	}
+
+	ret = dlb2_string_to_int(sw_credit_quanta, value);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+static int
+set_default_depth_thresh(const char *key __rte_unused,
+	const char *value,
+	void *opaque)
+{
+	int *default_depth_thresh = opaque;
+	int ret;
+
+	if (value == NULL || opaque == NULL) {
+		DLB2_LOG_ERR("NULL pointer\n");
+		return -EINVAL;
+	}
+
+	ret = dlb2_string_to_int(default_depth_thresh, value);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
 static int
 set_qid_depth_thresh(const char *key __rte_unused,
 		     const char *value,
@@ -923,9 +983,9 @@  dlb2_hw_create_ldb_queue(struct dlb2_eventdev *dlb2,
 	}
 
 	if (ev_queue->depth_threshold == 0) {
-		cfg.depth_threshold = RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH;
+		cfg.depth_threshold = dlb2->default_depth_thresh;
 		ev_queue->depth_threshold =
-			RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH;
+			dlb2->default_depth_thresh;
 	} else
 		cfg.depth_threshold = ev_queue->depth_threshold;
 
@@ -1617,7 +1677,7 @@  dlb2_eventdev_port_setup(struct rte_eventdev *dev,
 		  RTE_EVENT_PORT_CFG_DISABLE_IMPL_REL);
 	ev_port->outstanding_releases = 0;
 	ev_port->inflight_credits = 0;
-	ev_port->credit_update_quanta = RTE_LIBRTE_PMD_DLB_SW_CREDIT_QUANTA;
+	ev_port->credit_update_quanta = dlb2->sw_credit_quanta;
 	ev_port->dlb2 = dlb2; /* reverse link */
 
 	/* Tear down pre-existing port->queue links */
@@ -1712,9 +1772,9 @@  dlb2_hw_create_dir_queue(struct dlb2_eventdev *dlb2,
 	cfg.port_id = qm_port_id;
 
 	if (ev_queue->depth_threshold == 0) {
-		cfg.depth_threshold = RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH;
+		cfg.depth_threshold = dlb2->default_depth_thresh;
 		ev_queue->depth_threshold =
-			RTE_LIBRTE_PMD_DLB_DEFAULT_DEPTH_THRESH;
+			dlb2->default_depth_thresh;
 	} else
 		cfg.depth_threshold = ev_queue->depth_threshold;
 
@@ -3065,7 +3125,7 @@  dlb2_dequeue_wait(struct dlb2_eventdev *dlb2,
 
 		DLB2_INC_STAT(ev_port->stats.traffic.rx_umonitor_umwait, 1);
 	} else {
-		uint64_t poll_interval = RTE_LIBRTE_PMD_DLB_POLL_INTERVAL;
+		uint64_t poll_interval = dlb2->poll_interval;
 		uint64_t curr_ticks = rte_get_timer_cycles();
 		uint64_t init_ticks = curr_ticks;
 
@@ -4020,6 +4080,9 @@  dlb2_primary_eventdev_probe(struct rte_eventdev *dev,
 	dlb2->max_num_events_override = dlb2_args->max_num_events;
 	dlb2->num_dir_credits_override = dlb2_args->num_dir_credits_override;
 	dlb2->qm_instance.cos_id = dlb2_args->cos_id;
+	dlb2->poll_interval = dlb2_args->poll_interval;
+	dlb2->sw_credit_quanta = dlb2_args->sw_credit_quanta;
+	dlb2->default_depth_thresh = dlb2_args->default_depth_thresh;
 
 	err = dlb2_iface_open(&dlb2->qm_instance, name);
 	if (err < 0) {
@@ -4120,6 +4183,9 @@  dlb2_parse_params(const char *params,
 					     DEV_ID_ARG,
 					     DLB2_QID_DEPTH_THRESH_ARG,
 					     DLB2_COS_ARG,
+					     DLB2_POLL_INTERVAL_ARG,
+					     DLB2_SW_CREDIT_QUANTA_ARG,
+					     DLB2_DEPTH_THRESH_ARG,
 					     NULL };
 
 	if (params != NULL && params[0] != '\0') {
@@ -4202,6 +4268,37 @@  dlb2_parse_params(const char *params,
 				return ret;
 			}
 
+			ret = rte_kvargs_process(kvlist, DLB2_POLL_INTERVAL_ARG,
+						 set_poll_interval,
+						 &dlb2_args->poll_interval);
+			if (ret != 0) {
+				DLB2_LOG_ERR("%s: Error parsing poll interval parameter",
+					     name);
+				rte_kvargs_free(kvlist);
+				return ret;
+			}
+
+			ret = rte_kvargs_process(kvlist,
+						 DLB2_SW_CREDIT_QUANTA_ARG,
+						 set_sw_credit_quanta,
+						 &dlb2_args->sw_credit_quanta);
+			if (ret != 0) {
+				DLB2_LOG_ERR("%s: Error parsing sw xredit quanta parameter",
+					     name);
+				rte_kvargs_free(kvlist);
+				return ret;
+			}
+
+			ret = rte_kvargs_process(kvlist, DLB2_DEPTH_THRESH_ARG,
+					set_default_depth_thresh,
+					&dlb2_args->default_depth_thresh);
+			if (ret != 0) {
+				DLB2_LOG_ERR("%s: Error parsing set depth thresh parameter",
+					     name);
+				rte_kvargs_free(kvlist);
+				return ret;
+			}
+
 			rte_kvargs_free(kvlist);
 		}
 	}
diff --git a/drivers/event/dlb/dlb2_priv.h b/drivers/event/dlb/dlb2_priv.h
index f11e08fca..3c540a264 100644
--- a/drivers/event/dlb/dlb2_priv.h
+++ b/drivers/event/dlb/dlb2_priv.h
@@ -23,6 +23,11 @@ 
 /* common name for all dlb devs (dlb v2.0, dlb v2.5 ...) */
 #define EVDEV_DLB2_NAME_PMD dlb_event
 
+/* Default values for command line devargs */
+#define DLB2_POLL_INTERVAL_DEFAULT 1000
+#define DLB2_SW_CREDIT_QUANTA_DEFAULT 32
+#define DLB2_DEPTH_THRESH_DEFAULT 256
+
 /*  command line arg strings */
 #define NUMA_NODE_ARG "numa_node"
 #define DLB2_MAX_NUM_EVENTS "max_num_events"
@@ -31,6 +36,9 @@ 
 #define DLB2_DEFER_SCHED_ARG "defer_sched"
 #define DLB2_QID_DEPTH_THRESH_ARG "qid_depth_thresh"
 #define DLB2_COS_ARG "cos"
+#define DLB2_POLL_INTERVAL_ARG "poll_interval"
+#define DLB2_SW_CREDIT_QUANTA_ARG "sw_credit_quanta"
+#define DLB2_DEPTH_THRESH_ARG "default_depth_thresh"
 
 /* Begin HW related defines and structs */
 
@@ -571,6 +579,9 @@  struct dlb2_eventdev {
 	bool global_dequeue_wait; /* Not using per dequeue wait if true */
 	bool defer_sched;
 	enum dlb2_cq_poll_modes poll_mode;
+	int poll_interval;
+	int sw_credit_quanta;
+	int default_depth_thresh;
 	uint8_t revision;
 	uint8_t version;
 	bool configured;
@@ -604,6 +615,9 @@  struct dlb2_devargs {
 	int defer_sched;
 	struct dlb2_qid_depth_thresholds qid_depth_thresholds;
 	enum dlb2_cos cos_id;
+	int poll_interval;
+	int sw_credit_quanta;
+	int default_depth_thresh;
 };
 
 /* End Eventdev related defines and structs */
diff --git a/drivers/event/dlb/pf/dlb2_pf.c b/drivers/event/dlb/pf/dlb2_pf.c
index f57dc1584..e9da89d65 100644
--- a/drivers/event/dlb/pf/dlb2_pf.c
+++ b/drivers/event/dlb/pf/dlb2_pf.c
@@ -615,7 +615,10 @@  dlb2_eventdev_pci_init(struct rte_eventdev *eventdev)
 		.max_num_events = DLB2_MAX_NUM_LDB_CREDITS,
 		.num_dir_credits_override = -1,
 		.qid_depth_thresholds = { {0} },
-		.cos_id = DLB2_COS_DEFAULT
+		.cos_id = DLB2_COS_DEFAULT,
+		.poll_interval = DLB2_POLL_INTERVAL_DEFAULT,
+		.sw_credit_quanta = DLB2_SW_CREDIT_QUANTA_DEFAULT,
+		.default_depth_thresh = DLB2_DEPTH_THRESH_DEFAULT
 	};
 	struct dlb2_eventdev *dlb2;