net/mlx5: fix modify field action order for IPv6
Checks
Commit Message
Mellanox hardware can only modify any packet field in 32-bit chunks,
which means 4 such chunks are needed to modify an IPv6 address.
The modification order of these chunks starts from the most significant
bits for the IPv6 address. That leads to confusing results when trying
to modify either source or destination address via the MODIFY_FIELD
action. Fix the order of 32-bit chunks for IPv6 addresses modification
by starting from the least significant bits.
Fixes: 641dbe4fb053 ("net/mlx5: support modify field flow action")
Cc: stable@dpdk.org
Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
---
drivers/net/mlx5/mlx5_flow_dv.c | 46 +++++++++++++++++----------------
1 file changed, 24 insertions(+), 22 deletions(-)
Comments
> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Wednesday, April 7, 2021 4:15
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>
> Subject: [PATCH] net/mlx5: fix modify field action order for IPv6
>
> Mellanox hardware can only modify any packet field in 32-bit chunks, which
> means 4 such chunks are needed to modify an IPv6 address.
> The modification order of these chunks starts from the most significant bits
> for the IPv6 address. That leads to confusing results when trying to modify
> either source or destination address via the MODIFY_FIELD action. Fix the
> order of 32-bit chunks for IPv6 addresses modification by starting from the
> least significant bits.
>
> Fixes: 641dbe4fb053 ("net/mlx5: support modify field flow action")
> Cc: stable@dpdk.org
>
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
Acked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>
Hi,
> -----Original Message-----
> From: Alexander Kozyrev <akozyrev@nvidia.com>
> Sent: Wednesday, April 7, 2021 4:15 AM
> To: dev@dpdk.org
> Cc: stable@dpdk.org; Raslan Darawsheh <rasland@nvidia.com>; Slava
> Ovsiienko <viacheslavo@nvidia.com>
> Subject: [PATCH] net/mlx5: fix modify field action order for IPv6
>
> Mellanox hardware can only modify any packet field in 32-bit chunks,
> which means 4 such chunks are needed to modify an IPv6 address.
> The modification order of these chunks starts from the most significant
> bits for the IPv6 address. That leads to confusing results when trying
> to modify either source or destination address via the MODIFY_FIELD
> action. Fix the order of 32-bit chunks for IPv6 addresses modification
> by starting from the least significant bits.
>
> Fixes: 641dbe4fb053 ("net/mlx5: support modify field flow action")
> Cc: stable@dpdk.org
>
> Signed-off-by: Alexander Kozyrev <akozyrev@nvidia.com>
>
Patch applied to next-net-mlx,
Kindest regards,
Raslan Darawsheh
@@ -1515,8 +1515,9 @@ mlx5_flow_field_id_to_modify_info
case RTE_FLOW_FIELD_IPV6_SRC:
if (mask) {
if (data->offset < 32) {
- info[idx] = (struct field_modify_info){4, 0,
- MLX5_MODI_OUT_SIPV6_127_96};
+ info[idx] = (struct field_modify_info){4,
+ 4 * idx,
+ MLX5_MODI_OUT_SIPV6_31_0};
if (width < 32) {
mask[idx] =
rte_cpu_to_be_32(0xffffffff >>
@@ -1533,7 +1534,7 @@ mlx5_flow_field_id_to_modify_info
if (data->offset < 64) {
info[idx] = (struct field_modify_info){4,
4 * idx,
- MLX5_MODI_OUT_SIPV6_95_64};
+ MLX5_MODI_OUT_SIPV6_63_32};
if (width < 32) {
mask[idx] =
rte_cpu_to_be_32(0xffffffff >>
@@ -1549,8 +1550,8 @@ mlx5_flow_field_id_to_modify_info
}
if (data->offset < 96) {
info[idx] = (struct field_modify_info){4,
- 8 * idx,
- MLX5_MODI_OUT_SIPV6_63_32};
+ 4 * idx,
+ MLX5_MODI_OUT_SIPV6_95_64};
if (width < 32) {
mask[idx] =
rte_cpu_to_be_32(0xffffffff >>
@@ -1564,30 +1565,31 @@ mlx5_flow_field_id_to_modify_info
break;
++idx;
}
- info[idx] = (struct field_modify_info){4, 12 * idx,
- MLX5_MODI_OUT_SIPV6_31_0};
+ info[idx] = (struct field_modify_info){4, 4 * idx,
+ MLX5_MODI_OUT_SIPV6_127_96};
mask[idx] = rte_cpu_to_be_32(0xffffffff >>
(32 - width));
} else {
if (data->offset < 32)
info[idx++] = (struct field_modify_info){4, 0,
- MLX5_MODI_OUT_SIPV6_127_96};
+ MLX5_MODI_OUT_SIPV6_31_0};
if (data->offset < 64)
info[idx++] = (struct field_modify_info){4, 0,
- MLX5_MODI_OUT_SIPV6_95_64};
+ MLX5_MODI_OUT_SIPV6_63_32};
if (data->offset < 96)
info[idx++] = (struct field_modify_info){4, 0,
- MLX5_MODI_OUT_SIPV6_63_32};
+ MLX5_MODI_OUT_SIPV6_95_64};
if (data->offset < 128)
info[idx++] = (struct field_modify_info){4, 0,
- MLX5_MODI_OUT_SIPV6_31_0};
+ MLX5_MODI_OUT_SIPV6_127_96};
}
break;
case RTE_FLOW_FIELD_IPV6_DST:
if (mask) {
if (data->offset < 32) {
- info[idx] = (struct field_modify_info){4, 0,
- MLX5_MODI_OUT_DIPV6_127_96};
+ info[idx] = (struct field_modify_info){4,
+ 4 * idx,
+ MLX5_MODI_OUT_DIPV6_31_0};
if (width < 32) {
mask[idx] =
rte_cpu_to_be_32(0xffffffff >>
@@ -1604,7 +1606,7 @@ mlx5_flow_field_id_to_modify_info
if (data->offset < 64) {
info[idx] = (struct field_modify_info){4,
4 * idx,
- MLX5_MODI_OUT_DIPV6_95_64};
+ MLX5_MODI_OUT_DIPV6_63_32};
if (width < 32) {
mask[idx] =
rte_cpu_to_be_32(0xffffffff >>
@@ -1620,8 +1622,8 @@ mlx5_flow_field_id_to_modify_info
}
if (data->offset < 96) {
info[idx] = (struct field_modify_info){4,
- 8 * idx,
- MLX5_MODI_OUT_DIPV6_63_32};
+ 4 * idx,
+ MLX5_MODI_OUT_DIPV6_95_64};
if (width < 32) {
mask[idx] =
rte_cpu_to_be_32(0xffffffff >>
@@ -1635,23 +1637,23 @@ mlx5_flow_field_id_to_modify_info
break;
++idx;
}
- info[idx] = (struct field_modify_info){4, 12 * idx,
- MLX5_MODI_OUT_DIPV6_31_0};
+ info[idx] = (struct field_modify_info){4, 4 * idx,
+ MLX5_MODI_OUT_DIPV6_127_96};
mask[idx] = rte_cpu_to_be_32(0xffffffff >>
(32 - width));
} else {
if (data->offset < 32)
info[idx++] = (struct field_modify_info){4, 0,
- MLX5_MODI_OUT_DIPV6_127_96};
+ MLX5_MODI_OUT_DIPV6_31_0};
if (data->offset < 64)
info[idx++] = (struct field_modify_info){4, 0,
- MLX5_MODI_OUT_DIPV6_95_64};
+ MLX5_MODI_OUT_DIPV6_63_32};
if (data->offset < 96)
info[idx++] = (struct field_modify_info){4, 0,
- MLX5_MODI_OUT_DIPV6_63_32};
+ MLX5_MODI_OUT_DIPV6_95_64};
if (data->offset < 128)
info[idx++] = (struct field_modify_info){4, 0,
- MLX5_MODI_OUT_DIPV6_31_0};
+ MLX5_MODI_OUT_DIPV6_127_96};
}
break;
case RTE_FLOW_FIELD_TCP_PORT_SRC: