diff mbox series

[V2,1/4] config/arm: add Hisilicon kunpeng920 implementer

Message ID 1615340142-19115-2-git-send-email-oulijun@huawei.com (mailing list archive)
State Superseded, archived
Delegated to: Thomas Monjalon
Headers
Series add Hisilicon kunpeng CPU support |

Checks

Context Check Description
ci/checkpatch warning coding style issues

Commit Message

Lijun Ou March 10, 2021, 1:35 a.m. UTC 
  Here addes Kunpeng920 config back which was deleted.

Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous variables")

Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
Signed-off-by: Lijun Ou <oulijun@huawei.com>
---
V1->V2:
- rewrite patch title.
- split the patch into two.
---
 config/arm/meson.build | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

Comments

humin (Q) March 20, 2021, 2:27 a.m. UTC | #1 
Hi, all,
	have any comments about this set of patches?
	thanks.

在 2021/3/10 9:35, Lijun Ou 写道:
> Here addes Kunpeng920 config back which was deleted.
> 
> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous variables")
> 
> Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
> Signed-off-by: Lijun Ou <oulijun@huawei.com>
> ---
> V1->V2:
> - rewrite patch title.
> - split the patch into two.
> ---
>   config/arm/meson.build | 20 ++++++++++++++++++++
>   1 file changed, 20 insertions(+)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 00bc461..3826900 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -133,6 +133,25 @@ implementer_cavium = {
>   	}
>   }
>   
> +implementer_hisilicon = {
> +	'description': 'Hisilicon',
> +	'flags': [
> +		['RTE_USE_C11_MEM_MODEL', true],
> +		['RTE_CACHE_LINE_SIZE', 128],
> +		['RTE_MAX_NUMA_NODES', 4]
> +	],
> +	'part_number_config': {
> +		'0xd01': {
> +			'machine_args': ['-march=armv8.2-a+crypto',
> +					 '-mtune=tsv110'],
> +			'flag': [['RTE_MACHINE', '"kunpeng920"'],
> +				 ['RTE_MAX_LCORE', 128],
> +				 ['RTE_ARM_FEATURE_ATOMICS', true]
> +			]
> +		}
> +	}
> +}
> +
>   implementer_ampere = {
>   	'description': 'Ampere Computing',
>   	'flags': [
> @@ -190,6 +209,7 @@ implementers = {
>   	'generic': implementer_generic,
>   	'0x41': implementer_arm,
>   	'0x43': implementer_cavium,
> +	'0x48': implementer_hisilicon,
>   	'0x50': implementer_ampere,
>   	'0x51': implementer_qualcomm,
>   	'0x56': implementer_marvell,
>
Ruifeng Wang March 23, 2021, 8:07 a.m. UTC | #2 
> -----Original Message-----
> From: dev <dev-bounces@dpdk.org> On Behalf Of Lijun Ou
> Sent: Wednesday, March 10, 2021 9:36 AM
> To: thomas@monjalon.net; ferruh.yigit@intel.com
> Cc: dev@dpdk.org; linuxarm@openeuler.org
> Subject: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon kunpeng920
> implementer
> 
> Here addes Kunpeng920 config back which was deleted.
> 
> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous variables")
> 
> Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
> Signed-off-by: Lijun Ou <oulijun@huawei.com>
> ---
> V1->V2:
> - rewrite patch title.
> - split the patch into two.
> ---
>  config/arm/meson.build | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
> 
> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> 00bc461..3826900 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -133,6 +133,25 @@ implementer_cavium = {
>  	}
>  }
> 
> +implementer_hisilicon = {
> +	'description': 'Hisilicon',
> +	'flags': [
> +		['RTE_USE_C11_MEM_MODEL', true],
> +		['RTE_CACHE_LINE_SIZE', 128],

Just want to double check.
One Kunpeng920 box I can access have cache line size 64B.

Thanks.
> +		['RTE_MAX_NUMA_NODES', 4]
> +	],
> +	'part_number_config': {
> +		'0xd01': {
> +			'machine_args': ['-march=armv8.2-a+crypto',
> +					 '-mtune=tsv110'],
> +			'flag': [['RTE_MACHINE', '"kunpeng920"'],
> +				 ['RTE_MAX_LCORE', 128],
> +				 ['RTE_ARM_FEATURE_ATOMICS', true]
> +			]
> +		}
> +	}
> +}
> +
>  implementer_ampere = {
>  	'description': 'Ampere Computing',
>  	'flags': [
> @@ -190,6 +209,7 @@ implementers = {
>  	'generic': implementer_generic,
>  	'0x41': implementer_arm,
>  	'0x43': implementer_cavium,
> +	'0x48': implementer_hisilicon,
>  	'0x50': implementer_ampere,
>  	'0x51': implementer_qualcomm,
>  	'0x56': implementer_marvell,
> --
> 2.7.4
Lijun Ou March 23, 2021, 1:51 p.m. UTC | #3 
在 2021/3/23 16:07, Ruifeng Wang 写道:
>> -----Original Message-----
>> From: dev <dev-bounces@dpdk.org> On Behalf Of Lijun Ou
>> Sent: Wednesday, March 10, 2021 9:36 AM
>> To: thomas@monjalon.net; ferruh.yigit@intel.com
>> Cc: dev@dpdk.org; linuxarm@openeuler.org
>> Subject: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon kunpeng920
>> implementer
>>
>> Here addes Kunpeng920 config back which was deleted.
>>
>> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous variables")
>>
>> Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
>> Signed-off-by: Lijun Ou <oulijun@huawei.com>
>> ---
>> V1->V2:
>> - rewrite patch title.
>> - split the patch into two.
>> ---
>>   config/arm/meson.build | 20 ++++++++++++++++++++
>>   1 file changed, 20 insertions(+)
>>
>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>> 00bc461..3826900 100644
>> --- a/config/arm/meson.build
>> +++ b/config/arm/meson.build
>> @@ -133,6 +133,25 @@ implementer_cavium = {
>>   	}
>>   }
>>
>> +implementer_hisilicon = {
>> +	'description': 'Hisilicon',
>> +	'flags': [
>> +		['RTE_USE_C11_MEM_MODEL', true],
>> +		['RTE_CACHE_LINE_SIZE', 128],
> 
> Just want to double check.
> One Kunpeng920 box I can access have cache line size 64B.
> 
I have a question, which level does RTE_CACHE_LINE_SIZE refer to? For 
kunpeng920, L1/L2 cache size is 64B，L3 is 128B
> Thanks.
>> +		['RTE_MAX_NUMA_NODES', 4]
>> +	],
>> +	'part_number_config': {
>> +		'0xd01': {
>> +			'machine_args': ['-march=armv8.2-a+crypto',
>> +					 '-mtune=tsv110'],
>> +			'flag': [['RTE_MACHINE', '"kunpeng920"'],
>> +				 ['RTE_MAX_LCORE', 128],
>> +				 ['RTE_ARM_FEATURE_ATOMICS', true]
>> +			]
>> +		}
>> +	}
>> +}
>> +
>>   implementer_ampere = {
>>   	'description': 'Ampere Computing',
>>   	'flags': [
>> @@ -190,6 +209,7 @@ implementers = {
>>   	'generic': implementer_generic,
>>   	'0x41': implementer_arm,
>>   	'0x43': implementer_cavium,
>> +	'0x48': implementer_hisilicon,
>>   	'0x50': implementer_ampere,
>>   	'0x51': implementer_qualcomm,
>>   	'0x56': implementer_marvell,
>> --
>> 2.7.4
> 
> .
>
Ruifeng Wang March 23, 2021, 3:40 p.m. UTC | #4 
> -----Original Message-----
> From: oulijun <oulijun@huawei.com>
> Sent: Tuesday, March 23, 2021 9:52 PM
> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
> ferruh.yigit@intel.com
> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
> kunpeng920 implementer
> 
> 
> 
>    2021/3/23 16:07, Ruifeng Wang д  :
> >> -----Original Message-----
> >> From: dev <dev-bounces@dpdk.org> On Behalf Of Lijun Ou
> >> Sent: Wednesday, March 10, 2021 9:36 AM
> >> To: thomas@monjalon.net; ferruh.yigit@intel.com
> >> Cc: dev@dpdk.org; linuxarm@openeuler.org
> >> Subject: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
> >> kunpeng920 implementer
> >>
> >> Here addes Kunpeng920 config back which was deleted.
> >>
> >> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous
> >> variables")
> >>
> >> Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
> >> Signed-off-by: Lijun Ou <oulijun@huawei.com>
> >> ---
> >> V1->V2:
> >> - rewrite patch title.
> >> - split the patch into two.
> >> ---
> >>   config/arm/meson.build | 20 ++++++++++++++++++++
> >>   1 file changed, 20 insertions(+)
> >>
> >> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> >> 00bc461..3826900 100644
> >> --- a/config/arm/meson.build
> >> +++ b/config/arm/meson.build
> >> @@ -133,6 +133,25 @@ implementer_cavium = {
> >>   	}
> >>   }
> >>
> >> +implementer_hisilicon = {
> >> +	'description': 'Hisilicon',
> >> +	'flags': [
> >> +		['RTE_USE_C11_MEM_MODEL', true],
> >> +		['RTE_CACHE_LINE_SIZE', 128],
> >
> > Just want to double check.
> > One Kunpeng920 box I can access have cache line size 64B.
> >
> I have a question, which level does RTE_CACHE_LINE_SIZE refer to? For
> kunpeng920, L1/L2 cache size is 64B  L3 is 128B

Got it. 
I think RTE_CACHE_LINE_SIZE is not defined for a certain level of cache.
Data can be prefetched into any level of cache by using different APIs.

> > Thanks.
> >> +		['RTE_MAX_NUMA_NODES', 4]
> >> +	],
> >> +	'part_number_config': {
> >> +		'0xd01': {
> >> +			'machine_args': ['-march=armv8.2-a+crypto',
> >> +					 '-mtune=tsv110'],
> >> +			'flag': [['RTE_MACHINE', '"kunpeng920"'],
> >> +				 ['RTE_MAX_LCORE', 128],
> >> +				 ['RTE_ARM_FEATURE_ATOMICS', true]
> >> +			]
> >> +		}
> >> +	}
> >> +}
> >> +
> >>   implementer_ampere = {
> >>   	'description': 'Ampere Computing',
> >>   	'flags': [
> >> @@ -190,6 +209,7 @@ implementers = {
> >>   	'generic': implementer_generic,
> >>   	'0x41': implementer_arm,
> >>   	'0x43': implementer_cavium,
> >> +	'0x48': implementer_hisilicon,
> >>   	'0x50': implementer_ampere,
> >>   	'0x51': implementer_qualcomm,
> >>   	'0x56': implementer_marvell,
> >> --
> >> 2.7.4
> >
> > .
> >
Lijun Ou March 25, 2021, 7:21 a.m. UTC | #5 
在 2021/3/23 23:40, Ruifeng Wang 写道:
>> -----Original Message-----
>> From: oulijun <oulijun@huawei.com>
>> Sent: Tuesday, March 23, 2021 9:52 PM
>> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
>> ferruh.yigit@intel.com
>> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
>> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
>> kunpeng920 implementer
>>
>>
>>
>>     2021/3/23 16:07, Ruifeng Wang д  :
>>>> -----Original Message-----
>>>> From: dev <dev-bounces@dpdk.org> On Behalf Of Lijun Ou
>>>> Sent: Wednesday, March 10, 2021 9:36 AM
>>>> To: thomas@monjalon.net; ferruh.yigit@intel.com
>>>> Cc: dev@dpdk.org; linuxarm@openeuler.org
>>>> Subject: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
>>>> kunpeng920 implementer
>>>>
>>>> Here addes Kunpeng920 config back which was deleted.
>>>>
>>>> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous
>>>> variables")
>>>>
>>>> Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
>>>> Signed-off-by: Lijun Ou <oulijun@huawei.com>
>>>> ---
>>>> V1->V2:
>>>> - rewrite patch title.
>>>> - split the patch into two.
>>>> ---
>>>>    config/arm/meson.build | 20 ++++++++++++++++++++
>>>>    1 file changed, 20 insertions(+)
>>>>
>>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>>> 00bc461..3826900 100644
>>>> --- a/config/arm/meson.build
>>>> +++ b/config/arm/meson.build
>>>> @@ -133,6 +133,25 @@ implementer_cavium = {
>>>>    	}
>>>>    }
>>>>
>>>> +implementer_hisilicon = {
>>>> +	'description': 'Hisilicon',
>>>> +	'flags': [
>>>> +		['RTE_USE_C11_MEM_MODEL', true],
>>>> +		['RTE_CACHE_LINE_SIZE', 128],
>>>
>>> Just want to double check.
>>> One Kunpeng920 box I can access have cache line size 64B.
>>>
>> I have a question, which level does RTE_CACHE_LINE_SIZE refer to? For
>> kunpeng920, L1/L2 cache size is 64B  L3 is 128B
> 
> Got it.
> I think RTE_CACHE_LINE_SIZE is not defined for a certain level of cache.
> Data can be prefetched into any level of cache by using different APIs.
> 
So our current configuration should be fine.
>>> Thanks.
>>>> +		['RTE_MAX_NUMA_NODES', 4]
>>>> +	],
>>>> +	'part_number_config': {
>>>> +		'0xd01': {
>>>> +			'machine_args': ['-march=armv8.2-a+crypto',
>>>> +					 '-mtune=tsv110'],
>>>> +			'flag': [['RTE_MACHINE', '"kunpeng920"'],
>>>> +				 ['RTE_MAX_LCORE', 128],
>>>> +				 ['RTE_ARM_FEATURE_ATOMICS', true]
>>>> +			]
>>>> +		}
>>>> +	}
>>>> +}
>>>> +
>>>>    implementer_ampere = {
>>>>    	'description': 'Ampere Computing',
>>>>    	'flags': [
>>>> @@ -190,6 +209,7 @@ implementers = {
>>>>    	'generic': implementer_generic,
>>>>    	'0x41': implementer_arm,
>>>>    	'0x43': implementer_cavium,
>>>> +	'0x48': implementer_hisilicon,
>>>>    	'0x50': implementer_ampere,
>>>>    	'0x51': implementer_qualcomm,
>>>>    	'0x56': implementer_marvell,
>>>> --
>>>> 2.7.4
>>>
>>> .
>>>
Ruifeng Wang March 25, 2021, 7:45 a.m. UTC | #6 
> -----Original Message-----
> From: oulijun <oulijun@huawei.com>
> Sent: Thursday, March 25, 2021 3:22 PM
> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
> ferruh.yigit@intel.com
> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
> kunpeng920 implementer
> 
> 
> 
> 在 2021/3/23 23:40, Ruifeng Wang 写道:
> >> -----Original Message-----
> >> From: oulijun <oulijun@huawei.com>
> >> Sent: Tuesday, March 23, 2021 9:52 PM
> >> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
> >> ferruh.yigit@intel.com
> >> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
> >> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
> >> kunpeng920 implementer
> >>
> >>
> >>
> >>     2021/3/23 16:07, Ruifeng Wang д  :
> >>>> -----Original Message-----
> >>>> From: dev <dev-bounces@dpdk.org> On Behalf Of Lijun Ou
> >>>> Sent: Wednesday, March 10, 2021 9:36 AM
> >>>> To: thomas@monjalon.net; ferruh.yigit@intel.com
> >>>> Cc: dev@dpdk.org; linuxarm@openeuler.org
> >>>> Subject: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
> >>>> kunpeng920 implementer
> >>>>
> >>>> Here addes Kunpeng920 config back which was deleted.

There was no Kunpeng920 specific config before change 91c730fd4e09.
It would fall back to generic build because the behavior was to do generic build for unknown implementor / part number.

> >>>>
> >>>> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous
> >>>> variables")
> >>>>
> >>>> Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
> >>>> Signed-off-by: Lijun Ou <oulijun@huawei.com>
> >>>> ---
> >>>> V1->V2:
> >>>> - rewrite patch title.
> >>>> - split the patch into two.
> >>>> ---
> >>>>    config/arm/meson.build | 20 ++++++++++++++++++++
> >>>>    1 file changed, 20 insertions(+)
> >>>>
> >>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
> >>>> 00bc461..3826900 100644
> >>>> --- a/config/arm/meson.build
> >>>> +++ b/config/arm/meson.build
> >>>> @@ -133,6 +133,25 @@ implementer_cavium = {
> >>>>    	}
> >>>>    }
> >>>>
> >>>> +implementer_hisilicon = {
> >>>> +	'description': 'Hisilicon',
> >>>> +	'flags': [
> >>>> +		['RTE_USE_C11_MEM_MODEL', true],
> >>>> +		['RTE_CACHE_LINE_SIZE', 128],
> >>>
> >>> Just want to double check.
> >>> One Kunpeng920 box I can access have cache line size 64B.
> >>>
> >> I have a question, which level does RTE_CACHE_LINE_SIZE refer to? For
> >> kunpeng920, L1/L2 cache size is 64B  L3 is 128B
> >
> > Got it.
> > I think RTE_CACHE_LINE_SIZE is not defined for a certain level of cache.
> > Data can be prefetched into any level of cache by using different APIs.
> >
> So our current configuration should be fine.

Agree.

> >>> Thanks.
> >>>> +		['RTE_MAX_NUMA_NODES', 4]
> >>>> +	],
> >>>> +	'part_number_config': {
> >>>> +		'0xd01': {
> >>>> +			'machine_args': ['-march=armv8.2-a+crypto',
> >>>> +					 '-mtune=tsv110'],
> >>>> +			'flag': [['RTE_MACHINE', '"kunpeng920"'],
> >>>> +				 ['RTE_MAX_LCORE', 128],
> >>>> +				 ['RTE_ARM_FEATURE_ATOMICS', true]
> >>>> +			]
> >>>> +		}
> >>>> +	}
> >>>> +}
> >>>> +
> >>>>    implementer_ampere = {
> >>>>    	'description': 'Ampere Computing',
> >>>>    	'flags': [
> >>>> @@ -190,6 +209,7 @@ implementers = {
> >>>>    	'generic': implementer_generic,
> >>>>    	'0x41': implementer_arm,
> >>>>    	'0x43': implementer_cavium,
> >>>> +	'0x48': implementer_hisilicon,
> >>>>    	'0x50': implementer_ampere,
> >>>>    	'0x51': implementer_qualcomm,
> >>>>    	'0x56': implementer_marvell,
> >>>> --
> >>>> 2.7.4
> >>>
> >>> .
> >>>
Lijun Ou March 25, 2021, 7:56 a.m. UTC | #7 
在 2021/3/25 15:45, Ruifeng Wang 写道:
>> -----Original Message-----
>> From: oulijun <oulijun@huawei.com>
>> Sent: Thursday, March 25, 2021 3:22 PM
>> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
>> ferruh.yigit@intel.com
>> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
>> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
>> kunpeng920 implementer
>>
>>
>>
>> 在 2021/3/23 23:40, Ruifeng Wang 写道:
>>>> -----Original Message-----
>>>> From: oulijun <oulijun@huawei.com>
>>>> Sent: Tuesday, March 23, 2021 9:52 PM
>>>> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
>>>> ferruh.yigit@intel.com
>>>> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
>>>> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
>>>> kunpeng920 implementer
>>>>
>>>>
>>>>
>>>>      2021/3/23 16:07, Ruifeng Wang д  :
>>>>>> -----Original Message-----
>>>>>> From: dev <dev-bounces@dpdk.org> On Behalf Of Lijun Ou
>>>>>> Sent: Wednesday, March 10, 2021 9:36 AM
>>>>>> To: thomas@monjalon.net; ferruh.yigit@intel.com
>>>>>> Cc: dev@dpdk.org; linuxarm@openeuler.org
>>>>>> Subject: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
>>>>>> kunpeng920 implementer
>>>>>>
>>>>>> Here addes Kunpeng920 config back which was deleted.
> 
> There was no Kunpeng920 specific config before change 91c730fd4e09.
> It would fall back to generic build because the behavior was to do generic build for unknown implementor / part number.
> 
What should we do with this patch? This is because we cannot compile on 
the Kunpeng 920 server without adding generic build.
>>>>>>
>>>>>> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous
>>>>>> variables")
>>>>>>
>>>>>> Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
>>>>>> Signed-off-by: Lijun Ou <oulijun@huawei.com>
>>>>>> ---
>>>>>> V1->V2:
>>>>>> - rewrite patch title.
>>>>>> - split the patch into two.
>>>>>> ---
>>>>>>     config/arm/meson.build | 20 ++++++++++++++++++++
>>>>>>     1 file changed, 20 insertions(+)
>>>>>>
>>>>>> diff --git a/config/arm/meson.build b/config/arm/meson.build index
>>>>>> 00bc461..3826900 100644
>>>>>> --- a/config/arm/meson.build
>>>>>> +++ b/config/arm/meson.build
>>>>>> @@ -133,6 +133,25 @@ implementer_cavium = {
>>>>>>     	}
>>>>>>     }
>>>>>>
>>>>>> +implementer_hisilicon = {
>>>>>> +	'description': 'Hisilicon',
>>>>>> +	'flags': [
>>>>>> +		['RTE_USE_C11_MEM_MODEL', true],
>>>>>> +		['RTE_CACHE_LINE_SIZE', 128],
>>>>>
>>>>> Just want to double check.
>>>>> One Kunpeng920 box I can access have cache line size 64B.
>>>>>
>>>> I have a question, which level does RTE_CACHE_LINE_SIZE refer to? For
>>>> kunpeng920, L1/L2 cache size is 64B  L3 is 128B
>>>
>>> Got it.
>>> I think RTE_CACHE_LINE_SIZE is not defined for a certain level of cache.
>>> Data can be prefetched into any level of cache by using different APIs.
>>>
>> So our current configuration should be fine.
> 
> Agree.
> 
>>>>> Thanks.
>>>>>> +		['RTE_MAX_NUMA_NODES', 4]
>>>>>> +	],
>>>>>> +	'part_number_config': {
>>>>>> +		'0xd01': {
>>>>>> +			'machine_args': ['-march=armv8.2-a+crypto',
>>>>>> +					 '-mtune=tsv110'],
>>>>>> +			'flag': [['RTE_MACHINE', '"kunpeng920"'],
>>>>>> +				 ['RTE_MAX_LCORE', 128],
>>>>>> +				 ['RTE_ARM_FEATURE_ATOMICS', true]
>>>>>> +			]
>>>>>> +		}
>>>>>> +	}
>>>>>> +}
>>>>>> +
>>>>>>     implementer_ampere = {
>>>>>>     	'description': 'Ampere Computing',
>>>>>>     	'flags': [
>>>>>> @@ -190,6 +209,7 @@ implementers = {
>>>>>>     	'generic': implementer_generic,
>>>>>>     	'0x41': implementer_arm,
>>>>>>     	'0x43': implementer_cavium,
>>>>>> +	'0x48': implementer_hisilicon,
>>>>>>     	'0x50': implementer_ampere,
>>>>>>     	'0x51': implementer_qualcomm,
>>>>>>     	'0x56': implementer_marvell,
>>>>>> --
>>>>>> 2.7.4
>>>>>
>>>>> .
>>>>>
Ruifeng Wang March 25, 2021, 8:10 a.m. UTC | #8 
> -----Original Message-----
> From: oulijun <oulijun@huawei.com>
> Sent: Thursday, March 25, 2021 3:56 PM
> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
> ferruh.yigit@intel.com
> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
> kunpeng920 implementer
> 
> 
> 
> 在 2021/3/25 15:45, Ruifeng Wang 写道:
> >> -----Original Message-----
> >> From: oulijun <oulijun@huawei.com>
> >> Sent: Thursday, March 25, 2021 3:22 PM
> >> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
> >> ferruh.yigit@intel.com
> >> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
> >> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
> >> kunpeng920 implementer
> >>
> >>
> >>
> >> 在 2021/3/23 23:40, Ruifeng Wang 写道:
> >>>> -----Original Message-----
> >>>> From: oulijun <oulijun@huawei.com>
> >>>> Sent: Tuesday, March 23, 2021 9:52 PM
> >>>> To: Ruifeng Wang <Ruifeng.Wang@arm.com>; thomas@monjalon.net;
> >>>> ferruh.yigit@intel.com
> >>>> Cc: dev@dpdk.org; linuxarm@openeuler.org; nd <nd@arm.com>
> >>>> Subject: Re: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
> >>>> kunpeng920 implementer
> >>>>
> >>>>
> >>>>
> >>>>      2021/3/23 16:07, Ruifeng Wang д  :
> >>>>>> -----Original Message-----
> >>>>>> From: dev <dev-bounces@dpdk.org> On Behalf Of Lijun Ou
> >>>>>> Sent: Wednesday, March 10, 2021 9:36 AM
> >>>>>> To: thomas@monjalon.net; ferruh.yigit@intel.com
> >>>>>> Cc: dev@dpdk.org; linuxarm@openeuler.org
> >>>>>> Subject: [dpdk-dev] [PATCH V2 1/4] config/arm: add Hisilicon
> >>>>>> kunpeng920 implementer
> >>>>>>
> >>>>>> Here addes Kunpeng920 config back which was deleted.
> >
> > There was no Kunpeng920 specific config before change 91c730fd4e09.
> > It would fall back to generic build because the behavior was to do generic
> build for unknown implementor / part number.
> >
> What should we do with this patch? This is because we cannot compile on
> the Kunpeng 920 server without adding generic build.

I see the need to add config for Kunpeng 920.
IMO, the commit message can be refined. 

With commit message update,
Reviewed-by: Ruifeng Wang <ruifeng.wang@arm.com>
> >>>>>>
> >>>>>> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous
> >>>>>> variables")
> >>>>>>
> >>>>>> Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
> >>>>>> Signed-off-by: Lijun Ou <oulijun@huawei.com>
> >>>>>> ---
> >>>>>> V1->V2:
> >>>>>> - rewrite patch title.
> >>>>>> - split the patch into two.
> >>>>>> ---
> >>>>>>     config/arm/meson.build | 20 ++++++++++++++++++++
> >>>>>>     1 file changed, 20 insertions(+)
> >>>>>>
> >>>>>> diff --git a/config/arm/meson.build b/config/arm/meson.build
> >>>>>> index
> >>>>>> 00bc461..3826900 100644
> >>>>>> --- a/config/arm/meson.build
> >>>>>> +++ b/config/arm/meson.build
> >>>>>> @@ -133,6 +133,25 @@ implementer_cavium = {
> >>>>>>     	}
> >>>>>>     }
> >>>>>>
> >>>>>> +implementer_hisilicon = {
> >>>>>> +	'description': 'Hisilicon',
> >>>>>> +	'flags': [
> >>>>>> +		['RTE_USE_C11_MEM_MODEL', true],
> >>>>>> +		['RTE_CACHE_LINE_SIZE', 128],
> >>>>>
> >>>>> Just want to double check.
> >>>>> One Kunpeng920 box I can access have cache line size 64B.
> >>>>>
> >>>> I have a question, which level does RTE_CACHE_LINE_SIZE refer to?
> >>>> For kunpeng920, L1/L2 cache size is 64B  L3 is 128B
> >>>
> >>> Got it.
> >>> I think RTE_CACHE_LINE_SIZE is not defined for a certain level of cache.
> >>> Data can be prefetched into any level of cache by using different APIs.
> >>>
> >> So our current configuration should be fine.
> >
> > Agree.
> >
> >>>>> Thanks.
> >>>>>> +		['RTE_MAX_NUMA_NODES', 4]
> >>>>>> +	],
> >>>>>> +	'part_number_config': {
> >>>>>> +		'0xd01': {
> >>>>>> +			'machine_args': ['-march=armv8.2-a+crypto',
> >>>>>> +					 '-mtune=tsv110'],
> >>>>>> +			'flag': [['RTE_MACHINE', '"kunpeng920"'],
> >>>>>> +				 ['RTE_MAX_LCORE', 128],
> >>>>>> +				 ['RTE_ARM_FEATURE_ATOMICS',
> true]
> >>>>>> +			]
> >>>>>> +		}
> >>>>>> +	}
> >>>>>> +}
> >>>>>> +
> >>>>>>     implementer_ampere = {
> >>>>>>     	'description': 'Ampere Computing',
> >>>>>>     	'flags': [
> >>>>>> @@ -190,6 +209,7 @@ implementers = {
> >>>>>>     	'generic': implementer_generic,
> >>>>>>     	'0x41': implementer_arm,
> >>>>>>     	'0x43': implementer_cavium,
> >>>>>> +	'0x48': implementer_hisilicon,
> >>>>>>     	'0x50': implementer_ampere,
> >>>>>>     	'0x51': implementer_qualcomm,
> >>>>>>     	'0x56': implementer_marvell,
> >>>>>> --
> >>>>>> 2.7.4
> >>>>>
> >>>>> .
> >>>>>
Jerin Jacob March 26, 2021, 12:40 p.m. UTC | #9 
On Wed, Mar 10, 2021 at 7:05 AM Lijun Ou <oulijun@huawei.com> wrote:
>
> Here addes Kunpeng920 config back which was deleted.

Please fix the commit message.

With commit message update:


Acked-by: Jerin Jacob <jerinj@marvell.com>


>
> Fixes: 91c730fd4e09 ("config/arm: remove unused or superfluous variables")
>
> Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
> Signed-off-by: Lijun Ou <oulijun@huawei.com>
> ---
> V1->V2:
> - rewrite patch title.
> - split the patch into two.
> ---
>  config/arm/meson.build | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 00bc461..3826900 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -133,6 +133,25 @@ implementer_cavium = {
>         }
>  }
>
> +implementer_hisilicon = {
> +       'description': 'Hisilicon',
> +       'flags': [
> +               ['RTE_USE_C11_MEM_MODEL', true],
> +               ['RTE_CACHE_LINE_SIZE', 128],
> +               ['RTE_MAX_NUMA_NODES', 4]
> +       ],
> +       'part_number_config': {
> +               '0xd01': {
> +                       'machine_args': ['-march=armv8.2-a+crypto',
> +                                        '-mtune=tsv110'],
> +                       'flag': [['RTE_MACHINE', '"kunpeng920"'],
> +                                ['RTE_MAX_LCORE', 128],
> +                                ['RTE_ARM_FEATURE_ATOMICS', true]
> +                       ]
> +               }
> +       }
> +}
> +
>  implementer_ampere = {
>         'description': 'Ampere Computing',
>         'flags': [
> @@ -190,6 +209,7 @@ implementers = {
>         'generic': implementer_generic,
>         '0x41': implementer_arm,
>         '0x43': implementer_cavium,
> +       '0x48': implementer_hisilicon,
>         '0x50': implementer_ampere,
>         '0x51': implementer_qualcomm,
>         '0x56': implementer_marvell,
> --
> 2.7.4
>
diff mbox series

Patch

diff --git a/config/arm/meson.build b/config/arm/meson.build
index 00bc461..3826900 100644
--- a/config/arm/meson.build
+++ b/config/arm/meson.build
@@ -133,6 +133,25 @@  implementer_cavium = {
 	}
 }
 
+implementer_hisilicon = {
+	'description': 'Hisilicon',
+	'flags': [
+		['RTE_USE_C11_MEM_MODEL', true],
+		['RTE_CACHE_LINE_SIZE', 128],
+		['RTE_MAX_NUMA_NODES', 4]
+	],
+	'part_number_config': {
+		'0xd01': {
+			'machine_args': ['-march=armv8.2-a+crypto',
+					 '-mtune=tsv110'],
+			'flag': [['RTE_MACHINE', '"kunpeng920"'],
+				 ['RTE_MAX_LCORE', 128],
+				 ['RTE_ARM_FEATURE_ATOMICS', true]
+			]
+		}
+	}
+}
+
 implementer_ampere = {
 	'description': 'Ampere Computing',
 	'flags': [
@@ -190,6 +209,7 @@  implementers = {
 	'generic': implementer_generic,
 	'0x41': implementer_arm,
 	'0x43': implementer_cavium,
+	'0x48': implementer_hisilicon,
 	'0x50': implementer_ampere,
 	'0x51': implementer_qualcomm,
 	'0x56': implementer_marvell,