[v2] net/octeontx2: add cn98xx support
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Commit Message
New cn98xx SOC comes up with two NIX blocks wrt
cn96xx, cn93xx, to achieve higher performance.
Also the no of cores increased to 36 from 24.
Adding support for cn98xx where need a logic to
detect if the LF is attached to NIX0 or NIX1 and
then accordingly use the respective NIX block.
Signed-off-by: Harman Kalra <hkalra@marvell.com>
---
*V2: updated make/meson configs with the increased no of
cores.
config/arm/meson.build | 2 +-
config/defconfig_arm64-octeontx2-linuxapp-gcc | 2 +-
doc/guides/platform/octeontx2.rst | 1 +
drivers/common/octeontx2/hw/otx2_rvu.h | 3 ++-
drivers/net/octeontx2/otx2_ethdev.c | 17 ++++++++++++++++-
5 files changed, 21 insertions(+), 4 deletions(-)
Comments
On Wed, Jun 24, 2020 at 6:17 PM Harman Kalra <hkalra@marvell.com> wrote:
>
> New cn98xx SOC comes up with two NIX blocks wrt
> cn96xx, cn93xx, to achieve higher performance.
> Also the no of cores increased to 36 from 24.
>
> Adding support for cn98xx where need a logic to
> detect if the LF is attached to NIX0 or NIX1 and
> then accordingly use the respective NIX block.
>
> Signed-off-by: Harman Kalra <hkalra@marvell.com>
Acked-by: Jerin Jacob <jerinj@marvell.com>
Applied to dpdk-next-net-mrvl/master. Thanks
> ---
> *V2: updated make/meson configs with the increased no of
> cores.
>
> config/arm/meson.build | 2 +-
> config/defconfig_arm64-octeontx2-linuxapp-gcc | 2 +-
> doc/guides/platform/octeontx2.rst | 1 +
> drivers/common/octeontx2/hw/otx2_rvu.h | 3 ++-
> drivers/net/octeontx2/otx2_ethdev.c | 17 ++++++++++++++++-
> 5 files changed, 21 insertions(+), 4 deletions(-)
>
> diff --git a/config/arm/meson.build b/config/arm/meson.build
> index 6e75e6d97..8728051d5 100644
> --- a/config/arm/meson.build
> +++ b/config/arm/meson.build
> @@ -82,7 +82,7 @@ flags_thunderx2_extra = [
> flags_octeontx2_extra = [
> ['RTE_MACHINE', '"octeontx2"'],
> ['RTE_MAX_NUMA_NODES', 1],
> - ['RTE_MAX_LCORE', 24],
> + ['RTE_MAX_LCORE', 36],
> ['RTE_ARM_FEATURE_ATOMICS', true],
> ['RTE_EAL_IGB_UIO', false],
> ['RTE_USE_C11_MEM_MODEL', true]]
> diff --git a/config/defconfig_arm64-octeontx2-linuxapp-gcc b/config/defconfig_arm64-octeontx2-linuxapp-gcc
> index 7cfb81872..0d83becf5 100644
> --- a/config/defconfig_arm64-octeontx2-linuxapp-gcc
> +++ b/config/defconfig_arm64-octeontx2-linuxapp-gcc
> @@ -7,7 +7,7 @@
> CONFIG_RTE_MACHINE="octeontx2"
>
> CONFIG_RTE_MAX_NUMA_NODES=1
> -CONFIG_RTE_MAX_LCORE=24
> +CONFIG_RTE_MAX_LCORE=36
> CONFIG_RTE_ARM_FEATURE_ATOMICS=y
>
> # Doesn't support NUMA
> diff --git a/doc/guides/platform/octeontx2.rst b/doc/guides/platform/octeontx2.rst
> index d38a4c1ed..7dd695175 100644
> --- a/doc/guides/platform/octeontx2.rst
> +++ b/doc/guides/platform/octeontx2.rst
> @@ -13,6 +13,7 @@ More information about OCTEON TX2 SoC can be found at `Marvell Official Website
> Supported OCTEON TX2 SoCs
> -------------------------
>
> +- CN98xx
> - CN96xx
> - CN93xx
>
> diff --git a/drivers/common/octeontx2/hw/otx2_rvu.h b/drivers/common/octeontx2/hw/otx2_rvu.h
> index f2037ec57..330bfb37f 100644
> --- a/drivers/common/octeontx2/hw/otx2_rvu.h
> +++ b/drivers/common/octeontx2/hw/otx2_rvu.h
> @@ -134,11 +134,12 @@
> #define RVU_BLOCK_ADDR_RVUM (0x0ull)
> #define RVU_BLOCK_ADDR_LMT (0x1ull)
> #define RVU_BLOCK_ADDR_NPA (0x3ull)
> +#define RVU_BLOCK_ADDR_NIX0 (0x4ull)
> +#define RVU_BLOCK_ADDR_NIX1 (0x5ull)
> #define RVU_BLOCK_ADDR_NPC (0x6ull)
> #define RVU_BLOCK_ADDR_SSO (0x7ull)
> #define RVU_BLOCK_ADDR_SSOW (0x8ull)
> #define RVU_BLOCK_ADDR_TIM (0x9ull)
> -#define RVU_BLOCK_ADDR_NIX0 (0x4ull)
> #define RVU_BLOCK_ADDR_CPT0 (0xaull)
> #define RVU_BLOCK_ADDR_NDC0 (0xcull)
> #define RVU_BLOCK_ADDR_NDC1 (0xdull)
> diff --git a/drivers/net/octeontx2/otx2_ethdev.c b/drivers/net/octeontx2/otx2_ethdev.c
> index 3f3f0a693..095506034 100644
> --- a/drivers/net/octeontx2/otx2_ethdev.c
> +++ b/drivers/net/octeontx2/otx2_ethdev.c
> @@ -2177,6 +2177,20 @@ otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
> return false;
> }
>
> +static inline uint64_t
> +nix_get_blkaddr(struct otx2_eth_dev *dev)
> +{
> + uint64_t reg;
> +
> + /* Reading the discovery register to know which NIX is the LF
> + * attached to.
> + */
> + reg = otx2_read64(dev->bar2 +
> + RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0));
> +
> + return reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1;
> +}
> +
> static int
> otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
> {
> @@ -2236,7 +2250,6 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
> dev->configured = 0;
> dev->drv_inited = true;
> dev->ptype_disable = 0;
> - dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
> dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
>
> /* Attach NIX LF */
> @@ -2244,6 +2257,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
> if (rc)
> goto otx2_npa_uninit;
>
> + dev->base = dev->bar2 + (nix_get_blkaddr(dev) << 20);
> +
> /* Get NIX MSIX offset */
> rc = nix_lf_get_msix_offset(dev);
> if (rc)
> --
> 2.18.0
>
On 6/24/2020 1:46 PM, Harman Kalra wrote:
> New cn98xx SOC comes up with two NIX blocks wrt
> cn96xx, cn93xx, to achieve higher performance.
> Also the no of cores increased to 36 from 24.
>
> Adding support for cn98xx where need a logic to
> detect if the LF is attached to NIX0 or NIX1 and
> then accordingly use the respective NIX block.
>
> Signed-off-by: Harman Kalra <hkalra@marvell.com>
> ---
> *V2: updated make/meson configs with the increased no of
> cores.
Since this is new SoC support I think can be good to highlight in the release
notes, what do you think?
On Fri, Jun 26, 2020 at 10:40:16AM +0100, Ferruh Yigit wrote:
> External Email
>
> ----------------------------------------------------------------------
> On 6/24/2020 1:46 PM, Harman Kalra wrote:
> > New cn98xx SOC comes up with two NIX blocks wrt
> > cn96xx, cn93xx, to achieve higher performance.
> > Also the no of cores increased to 36 from 24.
> >
> > Adding support for cn98xx where need a logic to
> > detect if the LF is attached to NIX0 or NIX1 and
> > then accordingly use the respective NIX block.
> >
> > Signed-off-by: Harman Kalra <hkalra@marvell.com>
> > ---
> > *V2: updated make/meson configs with the increased no of
> > cores.
>
> Since this is new SoC support I think can be good to highlight in the release
> notes, what do you think?
Yes, this PMD update information should be captured in release notes.
But since this patch has already been merged to dpdk-next-net-mrvl tree,
so can I send a new patch with release notes only and later you can
squash both the patches together.
Thanks
Harman
On 6/26/2020 2:34 PM, Harman Kalra wrote:
> On Fri, Jun 26, 2020 at 10:40:16AM +0100, Ferruh Yigit wrote:
>> External Email
>>
>> ----------------------------------------------------------------------
>> On 6/24/2020 1:46 PM, Harman Kalra wrote:
>>> New cn98xx SOC comes up with two NIX blocks wrt
>>> cn96xx, cn93xx, to achieve higher performance.
>>> Also the no of cores increased to 36 from 24.
>>>
>>> Adding support for cn98xx where need a logic to
>>> detect if the LF is attached to NIX0 or NIX1 and
>>> then accordingly use the respective NIX block.
>>>
>>> Signed-off-by: Harman Kalra <hkalra@marvell.com>
>>> ---
>>> *V2: updated make/meson configs with the increased no of
>>> cores.
>>
>> Since this is new SoC support I think can be good to highlight in the release
>> notes, what do you think?
>
> Yes, this PMD update information should be captured in release notes.
> But since this patch has already been merged to dpdk-next-net-mrvl tree,
> so can I send a new patch with release notes only and later you can
> squash both the patches together.
That is OK, please send the release notes update, I will squash it to this patch.
@@ -82,7 +82,7 @@ flags_thunderx2_extra = [
flags_octeontx2_extra = [
['RTE_MACHINE', '"octeontx2"'],
['RTE_MAX_NUMA_NODES', 1],
- ['RTE_MAX_LCORE', 24],
+ ['RTE_MAX_LCORE', 36],
['RTE_ARM_FEATURE_ATOMICS', true],
['RTE_EAL_IGB_UIO', false],
['RTE_USE_C11_MEM_MODEL', true]]
@@ -7,7 +7,7 @@
CONFIG_RTE_MACHINE="octeontx2"
CONFIG_RTE_MAX_NUMA_NODES=1
-CONFIG_RTE_MAX_LCORE=24
+CONFIG_RTE_MAX_LCORE=36
CONFIG_RTE_ARM_FEATURE_ATOMICS=y
# Doesn't support NUMA
@@ -13,6 +13,7 @@ More information about OCTEON TX2 SoC can be found at `Marvell Official Website
Supported OCTEON TX2 SoCs
-------------------------
+- CN98xx
- CN96xx
- CN93xx
@@ -134,11 +134,12 @@
#define RVU_BLOCK_ADDR_RVUM (0x0ull)
#define RVU_BLOCK_ADDR_LMT (0x1ull)
#define RVU_BLOCK_ADDR_NPA (0x3ull)
+#define RVU_BLOCK_ADDR_NIX0 (0x4ull)
+#define RVU_BLOCK_ADDR_NIX1 (0x5ull)
#define RVU_BLOCK_ADDR_NPC (0x6ull)
#define RVU_BLOCK_ADDR_SSO (0x7ull)
#define RVU_BLOCK_ADDR_SSOW (0x8ull)
#define RVU_BLOCK_ADDR_TIM (0x9ull)
-#define RVU_BLOCK_ADDR_NIX0 (0x4ull)
#define RVU_BLOCK_ADDR_CPT0 (0xaull)
#define RVU_BLOCK_ADDR_NDC0 (0xcull)
#define RVU_BLOCK_ADDR_NDC1 (0xdull)
@@ -2177,6 +2177,20 @@ otx2_eth_dev_is_sdp(struct rte_pci_device *pci_dev)
return false;
}
+static inline uint64_t
+nix_get_blkaddr(struct otx2_eth_dev *dev)
+{
+ uint64_t reg;
+
+ /* Reading the discovery register to know which NIX is the LF
+ * attached to.
+ */
+ reg = otx2_read64(dev->bar2 +
+ RVU_PF_BLOCK_ADDRX_DISC(RVU_BLOCK_ADDR_NIX0));
+
+ return reg & 0x1FFULL ? RVU_BLOCK_ADDR_NIX0 : RVU_BLOCK_ADDR_NIX1;
+}
+
static int
otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
{
@@ -2236,7 +2250,6 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
dev->configured = 0;
dev->drv_inited = true;
dev->ptype_disable = 0;
- dev->base = dev->bar2 + (RVU_BLOCK_ADDR_NIX0 << 20);
dev->lmt_addr = dev->bar2 + (RVU_BLOCK_ADDR_LMT << 20);
/* Attach NIX LF */
@@ -2244,6 +2257,8 @@ otx2_eth_dev_init(struct rte_eth_dev *eth_dev)
if (rc)
goto otx2_npa_uninit;
+ dev->base = dev->bar2 + (nix_get_blkaddr(dev) << 20);
+
/* Get NIX MSIX offset */
rc = nix_lf_get_msix_offset(dev);
if (rc)