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GET /api/patches/99689/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 99689,
    "url": "https://patches.dpdk.org/api/patches/99689/?format=api",
    "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210926111904.237736-8-xuemingl@nvidia.com/",
    "project": {
        "id": 1,
        "url": "https://patches.dpdk.org/api/projects/1/?format=api",
        "name": "DPDK",
        "link_name": "dpdk",
        "list_id": "dev.dpdk.org",
        "list_email": "dev@dpdk.org",
        "web_url": "http://core.dpdk.org",
        "scm_url": "git://dpdk.org/dpdk",
        "webscm_url": "http://git.dpdk.org/dpdk",
        "list_archive_url": "https://inbox.dpdk.org/dev",
        "list_archive_url_format": "https://inbox.dpdk.org/dev/{}",
        "commit_url_format": ""
    },
    "msgid": "<20210926111904.237736-8-xuemingl@nvidia.com>",
    "list_archive_url": "https://inbox.dpdk.org/dev/20210926111904.237736-8-xuemingl@nvidia.com",
    "date": "2021-09-26T11:19:00",
    "name": "[07/11] net/mlx5: move Rx queue hairpin info to private data",
    "commit_ref": null,
    "pull_url": null,
    "state": "superseded",
    "archived": true,
    "hash": "b60e4cc84468177cb4109b313f9c1a33b58dc9e8",
    "submitter": {
        "id": 1904,
        "url": "https://patches.dpdk.org/api/people/1904/?format=api",
        "name": "Xueming Li",
        "email": "xuemingl@nvidia.com"
    },
    "delegate": {
        "id": 3268,
        "url": "https://patches.dpdk.org/api/users/3268/?format=api",
        "username": "rasland",
        "first_name": "Raslan",
        "last_name": "Darawsheh",
        "email": "rasland@nvidia.com"
    },
    "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210926111904.237736-8-xuemingl@nvidia.com/mbox/",
    "series": [
        {
            "id": 19166,
            "url": "https://patches.dpdk.org/api/series/19166/?format=api",
            "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=19166",
            "date": "2021-09-26T11:18:53",
            "name": "net/mlx5: support shared Rx queue",
            "version": 1,
            "mbox": "https://patches.dpdk.org/series/19166/mbox/"
        }
    ],
    "comments": "https://patches.dpdk.org/api/patches/99689/comments/",
    "check": "success",
    "checks": "https://patches.dpdk.org/api/patches/99689/checks/",
    "tags": {},
    "related": [],
    "headers": {
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        "From": "Xueming Li <xuemingl@nvidia.com>",
        "To": "<dev@dpdk.org>",
        "CC": "<xuemingl@nvidia.com>, Lior Margalit <lmargalit@nvidia.com>, Matan Azrad\n <matan@nvidia.com>, Viacheslav Ovsiienko <viacheslavo@nvidia.com>",
        "Date": "Sun, 26 Sep 2021 19:19:00 +0800",
        "Message-ID": "<20210926111904.237736-8-xuemingl@nvidia.com>",
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        "Subject": "[dpdk-dev] [PATCH 07/11] net/mlx5: move Rx queue hairpin info to\n private data",
        "X-BeenThere": "dev@dpdk.org",
        "X-Mailman-Version": "2.1.29",
        "Precedence": "list",
        "List-Id": "DPDK patches and discussions <dev.dpdk.org>",
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        "Errors-To": "dev-bounces@dpdk.org",
        "Sender": "\"dev\" <dev-bounces@dpdk.org>"
    },
    "content": "Hairpin info of Rx queue can't be shared, moves to private queue data.\n\nSigned-off-by: Xueming Li <xuemingl@nvidia.com>\n---\n drivers/net/mlx5/mlx5_rx.h      |  4 ++--\n drivers/net/mlx5/mlx5_rxq.c     | 13 +++++--------\n drivers/net/mlx5/mlx5_trigger.c | 24 ++++++++++++------------\n 3 files changed, 19 insertions(+), 22 deletions(-)",
    "diff": "diff --git a/drivers/net/mlx5/mlx5_rx.h b/drivers/net/mlx5/mlx5_rx.h\nindex fe19414c130..2ed544556f5 100644\n--- a/drivers/net/mlx5/mlx5_rx.h\n+++ b/drivers/net/mlx5/mlx5_rx.h\n@@ -171,8 +171,6 @@ struct mlx5_rxq_ctrl {\n \tuint32_t flow_tunnels_n[MLX5_FLOW_TUNNEL]; /* Tunnels counters. */\n \tuint32_t wqn; /* WQ number. */\n \tuint16_t dump_file_n; /* Number of dump files. */\n-\tstruct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */\n-\tuint32_t hairpin_status; /* Hairpin binding status. */\n };\n \n /* RX queue private data. */\n@@ -182,6 +180,8 @@ struct mlx5_rxq_priv {\n \tstruct mlx5_rxq_ctrl *ctrl; /* Shared Rx Queue. */\n \tLIST_ENTRY(mlx5_rxq_priv) owner_entry; /* Entry in shared rxq_ctrl. */\n \tstruct mlx5_priv *priv; /* Back pointer to private data. */\n+\tstruct rte_eth_hairpin_conf hairpin_conf; /* Hairpin configuration. */\n+\tuint32_t hairpin_status; /* Hairpin binding status. */\n };\n \n /* mlx5_rxq.c */\ndiff --git a/drivers/net/mlx5/mlx5_rxq.c b/drivers/net/mlx5/mlx5_rxq.c\nindex 7f28646f55c..21cb1000899 100644\n--- a/drivers/net/mlx5/mlx5_rxq.c\n+++ b/drivers/net/mlx5/mlx5_rxq.c\n@@ -1649,8 +1649,8 @@ mlx5_rxq_hairpin_new(struct rte_eth_dev *dev, struct mlx5_rxq_priv *rxq,\n \ttmpl->rxq.elts_n = log2above(desc);\n \ttmpl->rxq.elts = NULL;\n \ttmpl->rxq.mr_ctrl.cache_bh = (struct mlx5_mr_btree) { 0 };\n-\ttmpl->hairpin_conf = *hairpin_conf;\n \ttmpl->rxq.idx = idx;\n+\trxq->hairpin_conf = *hairpin_conf;\n \tmlx5_rxq_ref(dev, idx);\n \tLIST_INSERT_HEAD(&priv->rxqsctrl, tmpl, next);\n \treturn tmpl;\n@@ -1869,14 +1869,11 @@ const struct rte_eth_hairpin_conf *\n mlx5_rxq_get_hairpin_conf(struct rte_eth_dev *dev, uint16_t idx)\n {\n \tstruct mlx5_priv *priv = dev->data->dev_private;\n-\tstruct mlx5_rxq_ctrl *rxq_ctrl = NULL;\n+\tstruct mlx5_rxq_priv *rxq = mlx5_rxq_get(dev, idx);\n \n-\tif (idx < priv->rxqs_n && (*priv->rxqs)[idx]) {\n-\t\trxq_ctrl = container_of((*priv->rxqs)[idx],\n-\t\t\t\t\tstruct mlx5_rxq_ctrl,\n-\t\t\t\t\trxq);\n-\t\tif (rxq_ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)\n-\t\t\treturn &rxq_ctrl->hairpin_conf;\n+\tif (idx < priv->rxqs_n && rxq != NULL) {\n+\t\tif (rxq->ctrl->type == MLX5_RXQ_TYPE_HAIRPIN)\n+\t\t\treturn &rxq->hairpin_conf;\n \t}\n \treturn NULL;\n }\ndiff --git a/drivers/net/mlx5/mlx5_trigger.c b/drivers/net/mlx5/mlx5_trigger.c\nindex a49254c96f6..f376f4d6fc4 100644\n--- a/drivers/net/mlx5/mlx5_trigger.c\n+++ b/drivers/net/mlx5/mlx5_trigger.c\n@@ -273,7 +273,7 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev)\n \t\t}\n \t\trxq_ctrl = rxq->ctrl;\n \t\tif (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN ||\n-\t\t    rxq_ctrl->hairpin_conf.peers[0].queue != i) {\n+\t\t    rxq->hairpin_conf.peers[0].queue != i) {\n \t\t\trte_errno = ENOMEM;\n \t\t\tDRV_LOG(ERR, \"port %u Tx queue %d can't be binded to \"\n \t\t\t\t\"Rx queue %d\", dev->data->port_id,\n@@ -303,7 +303,7 @@ mlx5_hairpin_auto_bind(struct rte_eth_dev *dev)\n \t\tif (ret)\n \t\t\tgoto error;\n \t\t/* Qs with auto-bind will be destroyed directly. */\n-\t\trxq_ctrl->hairpin_status = 1;\n+\t\trxq->hairpin_status = 1;\n \t\ttxq_ctrl->hairpin_status = 1;\n \t\tmlx5_txq_release(dev, i);\n \t}\n@@ -406,9 +406,9 @@ mlx5_hairpin_queue_peer_update(struct rte_eth_dev *dev, uint16_t peer_queue,\n \t\t}\n \t\tpeer_info->qp_id = rxq_ctrl->obj->rq->id;\n \t\tpeer_info->vhca_id = priv->config.hca_attr.vhca_id;\n-\t\tpeer_info->peer_q = rxq_ctrl->hairpin_conf.peers[0].queue;\n-\t\tpeer_info->tx_explicit = rxq_ctrl->hairpin_conf.tx_explicit;\n-\t\tpeer_info->manual_bind = rxq_ctrl->hairpin_conf.manual_bind;\n+\t\tpeer_info->peer_q = rxq->hairpin_conf.peers[0].queue;\n+\t\tpeer_info->tx_explicit = rxq->hairpin_conf.tx_explicit;\n+\t\tpeer_info->manual_bind = rxq->hairpin_conf.manual_bind;\n \t}\n \treturn 0;\n }\n@@ -530,20 +530,20 @@ mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,\n \t\t\t\tdev->data->port_id, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n-\t\tif (rxq_ctrl->hairpin_status != 0) {\n+\t\tif (rxq->hairpin_status != 0) {\n \t\t\tDRV_LOG(DEBUG, \"port %u Rx queue %d is already bound\",\n \t\t\t\tdev->data->port_id, cur_queue);\n \t\t\treturn 0;\n \t\t}\n \t\tif (peer_info->tx_explicit !=\n-\t\t    rxq_ctrl->hairpin_conf.tx_explicit) {\n+\t\t    rxq->hairpin_conf.tx_explicit) {\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"port %u Rx queue %d and peer Tx rule mode\"\n \t\t\t\t\" mismatch\", dev->data->port_id, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n \t\tif (peer_info->manual_bind !=\n-\t\t    rxq_ctrl->hairpin_conf.manual_bind) {\n+\t\t    rxq->hairpin_conf.manual_bind) {\n \t\t\trte_errno = EINVAL;\n \t\t\tDRV_LOG(ERR, \"port %u Rx queue %d and peer binding mode\"\n \t\t\t\t\" mismatch\", dev->data->port_id, cur_queue);\n@@ -555,7 +555,7 @@ mlx5_hairpin_queue_peer_bind(struct rte_eth_dev *dev, uint16_t cur_queue,\n \t\trq_attr.hairpin_peer_vhca = peer_info->vhca_id;\n \t\tret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);\n \t\tif (ret == 0)\n-\t\t\trxq_ctrl->hairpin_status = 1;\n+\t\t\trxq->hairpin_status = 1;\n \t}\n \treturn ret;\n }\n@@ -637,7 +637,7 @@ mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,\n \t\t\t\tdev->data->port_id, cur_queue);\n \t\t\treturn -rte_errno;\n \t\t}\n-\t\tif (rxq_ctrl->hairpin_status == 0) {\n+\t\tif (rxq->hairpin_status == 0) {\n \t\t\tDRV_LOG(DEBUG, \"port %u Rx queue %d is already unbound\",\n \t\t\t\tdev->data->port_id, cur_queue);\n \t\t\treturn 0;\n@@ -652,7 +652,7 @@ mlx5_hairpin_queue_peer_unbind(struct rte_eth_dev *dev, uint16_t cur_queue,\n \t\trq_attr.rq_state = MLX5_SQC_STATE_RST;\n \t\tret = mlx5_devx_cmd_modify_rq(rxq_ctrl->obj->rq, &rq_attr);\n \t\tif (ret == 0)\n-\t\t\trxq_ctrl->hairpin_status = 0;\n+\t\t\trxq->hairpin_status = 0;\n \t}\n \treturn ret;\n }\n@@ -990,7 +990,7 @@ mlx5_hairpin_get_peer_ports(struct rte_eth_dev *dev, uint16_t *peer_ports,\n \t\t\trxq_ctrl = rxq->ctrl;\n \t\t\tif (rxq_ctrl->type != MLX5_RXQ_TYPE_HAIRPIN)\n \t\t\t\tcontinue;\n-\t\t\tpp = rxq_ctrl->hairpin_conf.peers[0].port;\n+\t\t\tpp = rxq->hairpin_conf.peers[0].port;\n \t\t\tif (pp >= RTE_MAX_ETHPORTS) {\n \t\t\t\trte_errno = ERANGE;\n \t\t\t\tDRV_LOG(ERR, \"port %hu queue %u peer port \"\n",
    "prefixes": [
        "07/11"
    ]
}