Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/99018/?format=api
{ "id": 99018, "url": "https://patches.dpdk.org/api/patches/99018/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210916095304.3058210-12-qi.z.zhang@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210916095304.3058210-12-qi.z.zhang@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210916095304.3058210-12-qi.z.zhang@intel.com", "date": "2021-09-16T09:53:03", "name": "[11/12] net/ice/base: implement support for SMA controller", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "f472dcbaaa96e636eb88c6a2bafe759629f2a9dc", "submitter": { "id": 504, "url": "https://patches.dpdk.org/api/people/504/?format=api", "name": "Qi Zhang", "email": "qi.z.zhang@intel.com" }, "delegate": { "id": 1540, "url": "https://patches.dpdk.org/api/users/1540/?format=api", "username": "qzhan15", "first_name": "Qi", "last_name": "Zhang", "email": "qi.z.zhang@intel.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210916095304.3058210-12-qi.z.zhang@intel.com/mbox/", "series": [ { "id": 18975, "url": "https://patches.dpdk.org/api/series/18975/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=18975", "date": "2021-09-16T09:52:52", "name": "ice base code batch 2 for DPDK 21.11", "version": 1, "mbox": "https://patches.dpdk.org/series/18975/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/99018/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/99018/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 9BD7DA0C41;\n\tThu, 16 Sep 2021 11:50:59 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 8B8BD410EC;\n\tThu, 16 Sep 2021 11:50:26 +0200 (CEST)", "from mga14.intel.com (mga14.intel.com [192.55.52.115])\n by mails.dpdk.org (Postfix) with ESMTP id 0B21D410E8\n for <dev@dpdk.org>; Thu, 16 Sep 2021 11:50:23 +0200 (CEST)", "from fmsmga008.fm.intel.com ([10.253.24.58])\n by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 16 Sep 2021 02:50:23 -0700", "from dpdk51.sh.intel.com ([10.67.111.142])\n by fmsmga008.fm.intel.com with ESMTP; 16 Sep 2021 02:50:21 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10108\"; a=\"222185895\"", "E=Sophos;i=\"5.85,298,1624345200\"; d=\"scan'208\";a=\"222185895\"", "E=Sophos;i=\"5.85,298,1624345200\"; d=\"scan'208\";a=\"509247045\"" ], "X-ExtLoop1": "1", "From": "Qi Zhang <qi.z.zhang@intel.com>", "To": "qiming.yang@intel.com", "Cc": "junfeng.guo@intel.com, dev@dpdk.org, Qi Zhang <qi.z.zhang@intel.com>,\n Maciej Machnikowski <maciej.machnikowski@intel.com>", "Date": "Thu, 16 Sep 2021 17:53:03 +0800", "Message-Id": "<20210916095304.3058210-12-qi.z.zhang@intel.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20210916095304.3058210-1-qi.z.zhang@intel.com>", "References": "<20210916095304.3058210-1-qi.z.zhang@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH 11/12] net/ice/base: implement support for SMA\n controller", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add support for controlling SMA connectors using GPIO get/set AQs.\n\nSigned-off-by: Maciej Machnikowski <maciej.machnikowski@intel.com>\nSigned-off-by: Qi Zhang <qi.z.zhang@intel.com>\n---\n drivers/net/ice/base/ice_ptp_hw.c | 213 ++++++++++++++++++++++++++++++\n drivers/net/ice/base/ice_ptp_hw.h | 11 ++\n drivers/net/ice/base/ice_type.h | 1 +\n 3 files changed, 225 insertions(+)", "diff": "diff --git a/drivers/net/ice/base/ice_ptp_hw.c b/drivers/net/ice/base/ice_ptp_hw.c\nindex 9ed335349b..7e797c9511 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.c\n+++ b/drivers/net/ice/base/ice_ptp_hw.c\n@@ -3077,6 +3077,219 @@ ice_ptp_port_cmd_e810(struct ice_hw *hw, enum ice_ptp_tmr_cmd cmd,\n \treturn ICE_SUCCESS;\n }\n \n+/* E810T SMA functions\n+ *\n+ * The following functions operate specifically on E810T hardware and are used\n+ * to access the extended GPIOs available.\n+ */\n+\n+/**\n+ * ice_get_pca9575_handle\n+ * @hw: pointer to the hw struct\n+ * @pca9575_handle: GPIO controller's handle\n+ *\n+ * Find and return the GPIO controller's handle in the netlist.\n+ * When found - the value will be cached in the hw structure and following calls\n+ * will return cached value\n+ */\n+static enum ice_status\n+ice_get_pca9575_handle(struct ice_hw *hw, __le16 *pca9575_handle)\n+{\n+\tstruct ice_aqc_get_link_topo *cmd;\n+\tstruct ice_aq_desc desc;\n+\tenum ice_status status;\n+\tu8 idx;\n+\n+\tif (!hw || !pca9575_handle)\n+\t\treturn ICE_ERR_PARAM;\n+\n+\t/* If handle was read previously return cached value */\n+\tif (hw->io_expander_handle) {\n+\t\t*pca9575_handle = hw->io_expander_handle;\n+\t\treturn ICE_SUCCESS;\n+\t}\n+\n+\t/* If handle was not detected read it from the netlist */\n+\tcmd = &desc.params.get_link_topo;\n+\tice_fill_dflt_direct_cmd_desc(&desc, ice_aqc_opc_get_link_topo);\n+\n+\t/* Set node type to GPIO controller */\n+\tcmd->addr.topo_params.node_type_ctx =\n+\t\t(ICE_AQC_LINK_TOPO_NODE_TYPE_M &\n+\t\t ICE_AQC_LINK_TOPO_NODE_TYPE_GPIO_CTRL);\n+\n+#define SW_PCA9575_SFP_TOPO_IDX\t\t2\n+#define SW_PCA9575_QSFP_TOPO_IDX\t1\n+\n+\t/* Check if the SW IO expander controlling SMA exists in the netlist. */\n+\tif (hw->device_id == ICE_DEV_ID_E810C_SFP)\n+\t\tidx = SW_PCA9575_SFP_TOPO_IDX;\n+\telse if (hw->device_id == ICE_DEV_ID_E810C_QSFP)\n+\t\tidx = SW_PCA9575_QSFP_TOPO_IDX;\n+\telse\n+\t\treturn ICE_ERR_NOT_SUPPORTED;\n+\n+\tcmd->addr.topo_params.index = idx;\n+\n+\tstatus = ice_aq_send_cmd(hw, &desc, NULL, 0, NULL);\n+\tif (status)\n+\t\treturn ICE_ERR_NOT_SUPPORTED;\n+\n+\t/* Verify if we found the right IO expander type */\n+\tif (desc.params.get_link_topo.node_part_num !=\n+\t\tICE_ACQ_GET_LINK_TOPO_NODE_NR_PCA9575)\n+\t\treturn ICE_ERR_NOT_SUPPORTED;\n+\n+\t/* If present save the handle and return it */\n+\thw->io_expander_handle = desc.params.get_link_topo.addr.handle;\n+\t*pca9575_handle = hw->io_expander_handle;\n+\n+\treturn ICE_SUCCESS;\n+}\n+\n+/**\n+ * ice_read_e810t_pca9575_reg\n+ * @hw: pointer to the hw struct\n+ * @offset: GPIO controller register offset\n+ * @data: pointer to data to be read from the GPIO controller\n+ *\n+ * Read the register from the GPIO controller\n+ */\n+enum ice_status\n+ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data)\n+{\n+\tstruct ice_aqc_link_topo_addr link_topo;\n+\tenum ice_status status;\n+\t__le16 addr;\n+\n+\tmemset(&link_topo, 0, sizeof(link_topo));\n+\n+\tstatus = ice_get_pca9575_handle(hw, &link_topo.handle);\n+\tif (status)\n+\t\treturn status;\n+\n+\tlink_topo.topo_params.node_type_ctx =\n+\t\t(ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<\n+\t\t ICE_AQC_LINK_TOPO_NODE_CTX_S);\n+\n+\taddr = CPU_TO_LE16((u16)offset);\n+\n+\treturn ice_aq_read_i2c(hw, link_topo, 0, addr, 1, data, NULL);\n+}\n+\n+/**\n+ * ice_write_e810t_pca9575_reg\n+ * @hw: pointer to the hw struct\n+ * @offset: GPIO controller register offset\n+ * @data: data to be written to the GPIO controller\n+ *\n+ * Write the data to the GPIO controller register\n+ */\n+enum ice_status\n+ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data)\n+{\n+\tstruct ice_aqc_link_topo_addr link_topo;\n+\tenum ice_status status;\n+\t__le16 addr;\n+\n+\tmemset(&link_topo, 0, sizeof(link_topo));\n+\n+\tstatus = ice_get_pca9575_handle(hw, &link_topo.handle);\n+\tif (status)\n+\t\treturn status;\n+\n+\tlink_topo.topo_params.node_type_ctx =\n+\t\t(ICE_AQC_LINK_TOPO_NODE_CTX_PROVIDED <<\n+\t\t ICE_AQC_LINK_TOPO_NODE_CTX_S);\n+\n+\taddr = CPU_TO_LE16((u16)offset);\n+\n+\treturn ice_aq_write_i2c(hw, link_topo, 0, addr, 1, &data, NULL);\n+}\n+\n+/**\n+ * ice_read_sma_ctrl_e810t\n+ * @hw: pointer to the hw struct\n+ * @data: pointer to data to be read from the GPIO controller\n+ *\n+ * Read the SMA controller state. Only bits 3-7 in data are valid.\n+ */\n+enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data)\n+{\n+\tenum ice_status status;\n+\tu16 handle;\n+\tu8 i;\n+\n+\tstatus = ice_get_pca9575_handle(hw, &handle);\n+\tif (status)\n+\t\treturn status;\n+\n+\t*data = 0;\n+\n+\tfor (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) {\n+\t\tbool pin;\n+\n+\t\tstatus = ice_aq_get_gpio(hw, handle, i + ICE_E810T_P1_OFFSET,\n+\t\t\t\t\t &pin, NULL);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t\t*data |= (u8)(!pin) << i;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_write_sma_ctrl_e810t\n+ * @hw: pointer to the hw struct\n+ * @data: data to be written to the GPIO controller\n+ *\n+ * Write the data to the SMA controller. Only bits 3-7 in data are valid.\n+ */\n+enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data)\n+{\n+\tenum ice_status status;\n+\tu16 handle;\n+\tu8 i;\n+\n+\tstatus = ice_get_pca9575_handle(hw, &handle);\n+\tif (status)\n+\t\treturn status;\n+\n+\tfor (i = ICE_E810T_SMA_MIN_BIT; i <= ICE_E810T_SMA_MAX_BIT; i++) {\n+\t\tbool pin;\n+\n+\t\tpin = !(data & (1 << i));\n+\t\tstatus = ice_aq_set_gpio(hw, handle, i + ICE_E810T_P1_OFFSET,\n+\t\t\t\t\t pin, NULL);\n+\t\tif (status)\n+\t\t\tbreak;\n+\t}\n+\n+\treturn status;\n+}\n+\n+/**\n+ * ice_e810t_is_pca9575_present\n+ * @hw: pointer to the hw struct\n+ *\n+ * Check if the SW IO expander is present in the netlist\n+ */\n+bool ice_e810t_is_pca9575_present(struct ice_hw *hw)\n+{\n+\tenum ice_status status;\n+\t__le16 handle = 0;\n+\n+\tif (!ice_is_e810t(hw))\n+\t\treturn false;\n+\n+\tstatus = ice_get_pca9575_handle(hw, &handle);\n+\tif (!status && handle)\n+\t\treturn true;\n+\n+\treturn false;\n+}\n+\n /* Device agnostic functions\n *\n * The following functions implement shared behavior common to both E822 and\ndiff --git a/drivers/net/ice/base/ice_ptp_hw.h b/drivers/net/ice/base/ice_ptp_hw.h\nindex c804085095..ee3366e83c 100644\n--- a/drivers/net/ice/base/ice_ptp_hw.h\n+++ b/drivers/net/ice/base/ice_ptp_hw.h\n@@ -222,6 +222,13 @@ enum ice_status ice_phy_exit_bypass_e822(struct ice_hw *hw, u8 port);\n \n /* E810 family functions */\n enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);\n+enum ice_status\n+ice_read_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 *data);\n+enum ice_status\n+ice_write_e810t_pca9575_reg(struct ice_hw *hw, u8 offset, u8 data);\n+enum ice_status ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);\n+enum ice_status ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);\n+bool ice_e810t_is_pca9575_present(struct ice_hw *hw);\n \n #define PFTSYN_SEM_BYTES\t4\n \n@@ -470,4 +477,8 @@ enum ice_status ice_ptp_init_phy_e810(struct ice_hw *hw);\n #define ICE_E810T_P1_SMA2_DIR_EN\tBIT(6)\n #define ICE_E810T_P1_SMA2_TX_EN\t\tBIT(7)\n \n+#define ICE_E810T_SMA_MIN_BIT\t3\n+#define ICE_E810T_SMA_MAX_BIT\t7\n+#define ICE_E810T_P1_OFFSET\t8\n+\n #endif /* _ICE_PTP_HW_H_ */\ndiff --git a/drivers/net/ice/base/ice_type.h b/drivers/net/ice/base/ice_type.h\nindex b2b3291fb7..72cda11a4f 100644\n--- a/drivers/net/ice/base/ice_type.h\n+++ b/drivers/net/ice/base/ice_type.h\n@@ -1261,6 +1261,7 @@ struct ice_hw {\n \tstruct LIST_HEAD_TYPE rss_list_head;\n \tice_declare_bitmap(hw_ptype, ICE_FLOW_PTYPE_MAX);\n \tu8 dvm_ena;\n+\t__le16 io_expander_handle;\n };\n \n /* Statistics collected by each port, VSI, VEB, and S-channel */\n", "prefixes": [ "11/12" ] }