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GET /api/patches/97800/?format=api
{ "id": 97800, "url": "https://patches.dpdk.org/api/patches/97800/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/1630585354-1136-8-git-send-email-anoobj@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<1630585354-1136-8-git-send-email-anoobj@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/1630585354-1136-8-git-send-email-anoobj@marvell.com", "date": "2021-09-02T12:22:34", "name": "[7/7] crypto/cnxk: add dual submission in crypto_cn9k", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "37206a23fe2c50bbb07e7d054018aadcd93f760e", "submitter": { "id": 1205, "url": "https://patches.dpdk.org/api/people/1205/?format=api", "name": "Anoob Joseph", "email": "anoobj@marvell.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/1630585354-1136-8-git-send-email-anoobj@marvell.com/mbox/", "series": [ { "id": 18628, "url": "https://patches.dpdk.org/api/series/18628/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=18628", "date": "2021-09-02T12:22:27", "name": "Improvements and fixes in crypto/cnxk PMDs", "version": 1, "mbox": "https://patches.dpdk.org/series/18628/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/97800/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/97800/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 3BB70A0C47;\n\tThu, 2 Sep 2021 14:23:34 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 79802410FF;\n\tThu, 2 Sep 2021 14:23:30 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com\n [67.231.148.174])\n by mails.dpdk.org (Postfix) with ESMTP id 1EEB340686\n for <dev@dpdk.org>; Thu, 2 Sep 2021 14:23:28 +0200 (CEST)", "from pps.filterd (m0045849.ppops.net [127.0.0.1])\n by mx0a-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 1825LHeJ028342\n for <dev@dpdk.org>; Thu, 2 Sep 2021 05:23:28 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0a-0016f401.pphosted.com with ESMTP id 3atrd2hefc-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Thu, 02 Sep 2021 05:23:27 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Thu, 2 Sep 2021 05:23:26 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Thu, 2 Sep 2021 05:23:26 -0700", "from HY-LT1002.marvell.com (HY-LT1002.marvell.com [10.28.176.218])\n by maili.marvell.com (Postfix) with ESMTP id 36DC53F705E;\n Thu, 2 Sep 2021 05:23:22 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-transfer-encoding : content-type; s=pfpt0220;\n bh=JKgwjqMrQa/+2SIODoN/hTS7U6mNCsYwDixF7aI0pm4=;\n b=ZMo7f7Db6OtH3tU77uEEXwRNBLhXBNxQAUsCdZEbB4ynnaps93ulFEVkojrxcbzLwXB5\n zauDiJqeBQDrkA1NiMHSzQBBlqsf4gb0oV96GchFztChKJN4CXaKtxE7SgFQBxljpwjL\n +ANNquFjyffxmU5clWQx3eaUIDEvwoK4OIDFTRL80pWaZSwcDMyMh0Q95+j6jzzbsL9B\n J08xOyAqUXsyWCMY4S7ADgBay4BZtFrD/txBTuIfVsmtEpXiYo78Wh7bSFicl4ckRfU8\n VLVQU8E3FWVXq5RZEo6uMy31v/Ob7HMsKheupgzpCUZW3XfoeCSl0Qg+qiAZWfovpjb0 xw==", "From": "Anoob Joseph <anoobj@marvell.com>", "To": "Akhil Goyal <gakhil@marvell.com>, Jerin Jacob <jerinj@marvell.com>", "CC": "Anoob Joseph <anoobj@marvell.com>, Archana Muniganti\n <marchana@marvell.com>,\n Tejasree Kondoj <ktejasree@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 2 Sep 2021 17:52:34 +0530", "Message-ID": "<1630585354-1136-8-git-send-email-anoobj@marvell.com>", "X-Mailer": "git-send-email 2.7.4", "In-Reply-To": "<1630585354-1136-1-git-send-email-anoobj@marvell.com>", "References": "<1630585354-1136-1-git-send-email-anoobj@marvell.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Proofpoint-GUID": "4pwFH_JD-zgi-VYU32tircLnq_pHli1r", "X-Proofpoint-ORIG-GUID": "4pwFH_JD-zgi-VYU32tircLnq_pHli1r", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-02_04,2021-09-02_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 7/7] crypto/cnxk: add dual submission in\n crypto_cn9k", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Submit two instructions with one LMTST operation. Also updated dequeue\npath to have local var for constants.\n\nSigned-off-by: Anoob Joseph <anoobj@marvell.com>\n---\n drivers/crypto/cnxk/cn9k_cryptodev_ops.c | 155 +++++++++++++++++++++++++------\n 1 file changed, 127 insertions(+), 28 deletions(-)", "diff": "diff --git a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\nindex 4c0eb12..8ade197 100644\n--- a/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n+++ b/drivers/crypto/cnxk/cn9k_cryptodev_ops.c\n@@ -5,6 +5,7 @@\n #include <rte_cryptodev.h>\n #include <rte_cryptodev_pmd.h>\n #include <rte_event_crypto_adapter.h>\n+#include <rte_vect.h>\n \n #include \"cn9k_cryptodev.h\"\n #include \"cn9k_cryptodev_ops.h\"\n@@ -64,9 +65,8 @@ cn9k_cpt_sym_temp_sess_create(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op)\n }\n \n static inline int\n-cn9k_cpt_prepare_instruction(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n-\t\t\t struct cpt_inflight_req *infl_req,\n-\t\t\t struct cpt_inst_s *inst)\n+cn9k_cpt_inst_prep(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n+\t\t struct cpt_inflight_req *infl_req, struct cpt_inst_s *inst)\n {\n \tint ret;\n \n@@ -118,8 +118,8 @@ cn9k_cpt_prepare_instruction(struct cnxk_cpt_qp *qp, struct rte_crypto_op *op,\n }\n \n static inline void\n-cn9k_cpt_submit_instruction(struct cpt_inst_s *inst, uint64_t lmtline,\n-\t\t\t uint64_t io_addr)\n+cn9k_cpt_inst_submit(struct cpt_inst_s *inst, uint64_t lmtline,\n+\t\t uint64_t io_addr)\n {\n \tuint64_t lmt_status;\n \n@@ -138,46 +138,144 @@ cn9k_cpt_submit_instruction(struct cpt_inst_s *inst, uint64_t lmtline,\n \t} while (lmt_status == 0);\n }\n \n+static __plt_always_inline void\n+cn9k_cpt_inst_submit_dual(struct cpt_inst_s *inst, uint64_t lmtline,\n+\t\t\t uint64_t io_addr)\n+{\n+\tuint64_t lmt_status;\n+\n+\tdo {\n+\t\t/* Copy 2 CPT inst_s to LMTLINE */\n+#if defined(RTE_ARCH_ARM64)\n+\t\tuint64_t *s = (uint64_t *)inst;\n+\t\tuint64_t *d = (uint64_t *)lmtline;\n+\n+\t\tvst1q_u64(&d[0], vld1q_u64(&s[0]));\n+\t\tvst1q_u64(&d[2], vld1q_u64(&s[2]));\n+\t\tvst1q_u64(&d[4], vld1q_u64(&s[4]));\n+\t\tvst1q_u64(&d[6], vld1q_u64(&s[6]));\n+\t\tvst1q_u64(&d[8], vld1q_u64(&s[8]));\n+\t\tvst1q_u64(&d[10], vld1q_u64(&s[10]));\n+\t\tvst1q_u64(&d[12], vld1q_u64(&s[12]));\n+\t\tvst1q_u64(&d[14], vld1q_u64(&s[14]));\n+#else\n+\t\troc_lmt_mov_seg((void *)lmtline, inst, 8);\n+#endif\n+\n+\t\t/*\n+\t\t * Make sure compiler does not reorder memcpy and ldeor.\n+\t\t * LMTST transactions are always flushed from the write\n+\t\t * buffer immediately, a DMB is not required to push out\n+\t\t * LMTSTs.\n+\t\t */\n+\t\trte_io_wmb();\n+\t\tlmt_status = roc_lmt_submit_ldeor(io_addr);\n+\t} while (lmt_status == 0);\n+}\n+\n static uint16_t\n cn9k_cpt_enqueue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n {\n-\tstruct cpt_inflight_req *infl_req;\n+\tstruct cpt_inflight_req *infl_req_1, *infl_req_2;\n+\tstruct cpt_inst_s inst[2] __rte_cache_aligned;\n+\tstruct rte_crypto_op *op_1, *op_2;\n \tuint16_t nb_allowed, count = 0;\n \tstruct cnxk_cpt_qp *qp = qptr;\n \tstruct pending_queue *pend_q;\n-\tstruct rte_crypto_op *op;\n-\tstruct cpt_inst_s inst;\n+\tuint64_t enq_tail;\n \tint ret;\n \n+\tconst uint32_t nb_desc = qp->lf.nb_desc;\n+\tconst uint64_t lmt_base = qp->lf.lmt_base;\n+\tconst uint64_t io_addr = qp->lf.io_addr;\n+\n \tpend_q = &qp->pend_q;\n \n-\tinst.w0.u64 = 0;\n-\tinst.w2.u64 = 0;\n-\tinst.w3.u64 = 0;\n+\t/* Clear w0, w2, w3 of both inst */\n+\n+\tinst[0].w0.u64 = 0;\n+\tinst[0].w2.u64 = 0;\n+\tinst[0].w3.u64 = 0;\n+\tinst[1].w0.u64 = 0;\n+\tinst[1].w2.u64 = 0;\n+\tinst[1].w3.u64 = 0;\n \n \tnb_allowed = qp->lf.nb_desc - pend_q->pending_count;\n \tnb_ops = RTE_MIN(nb_ops, nb_allowed);\n \n-\tfor (count = 0; count < nb_ops; count++) {\n-\t\top = ops[count];\n-\t\tinfl_req = &pend_q->req_queue[pend_q->enq_tail];\n-\t\tinfl_req->op_flags = 0;\n+\tenq_tail = pend_q->enq_tail;\n+\n+\tif (unlikely(nb_ops & 1)) {\n+\t\top_1 = ops[0];\n+\t\tinfl_req_1 = &pend_q->req_queue[enq_tail];\n+\t\tinfl_req_1->op_flags = 0;\n \n-\t\tret = cn9k_cpt_prepare_instruction(qp, op, infl_req, &inst);\n+\t\tret = cn9k_cpt_inst_prep(qp, op_1, infl_req_1, &inst[0]);\n \t\tif (unlikely(ret)) {\n-\t\t\tplt_dp_err(\"Could not process op: %p\", op);\n+\t\t\tplt_dp_err(\"Could not process op: %p\", op_1);\n+\t\t\treturn 0;\n+\t\t}\n+\n+\t\tinfl_req_1->cop = op_1;\n+\t\tinfl_req_1->res.cn9k.compcode = CPT_COMP_NOT_DONE;\n+\t\tinst[0].res_addr = (uint64_t)&infl_req_1->res;\n+\n+\t\tcn9k_cpt_inst_submit(&inst[0], lmt_base, io_addr);\n+\t\tMOD_INC(enq_tail, nb_desc);\n+\t\tcount++;\n+\t}\n+\n+\twhile (count < nb_ops) {\n+\t\top_1 = ops[count];\n+\t\top_2 = ops[count + 1];\n+\n+\t\tinfl_req_1 = &pend_q->req_queue[enq_tail];\n+\t\tMOD_INC(enq_tail, nb_desc);\n+\t\tinfl_req_2 = &pend_q->req_queue[enq_tail];\n+\t\tMOD_INC(enq_tail, nb_desc);\n+\n+\t\tinfl_req_1->cop = op_1;\n+\t\tinfl_req_2->cop = op_2;\n+\t\tinfl_req_1->op_flags = 0;\n+\t\tinfl_req_2->op_flags = 0;\n+\n+\t\tinfl_req_1->res.cn9k.compcode = CPT_COMP_NOT_DONE;\n+\t\tinst[0].res_addr = (uint64_t)&infl_req_1->res;\n+\n+\t\tinfl_req_2->res.cn9k.compcode = CPT_COMP_NOT_DONE;\n+\t\tinst[1].res_addr = (uint64_t)&infl_req_2->res;\n+\n+\t\tret = cn9k_cpt_inst_prep(qp, op_1, infl_req_1, &inst[0]);\n+\t\tif (unlikely(ret)) {\n+\t\t\tplt_dp_err(\"Could not process op: %p\", op_1);\n+\t\t\tif (enq_tail == 0)\n+\t\t\t\tenq_tail = nb_desc - 2;\n+\t\t\telse if (enq_tail == 1)\n+\t\t\t\tenq_tail = nb_desc - 1;\n+\t\t\telse\n+\t\t\t\tenq_tail--;\n+\t\t\tbreak;\n+\t\t}\n+\n+\t\tret = cn9k_cpt_inst_prep(qp, op_2, infl_req_2, &inst[1]);\n+\t\tif (unlikely(ret)) {\n+\t\t\tplt_dp_err(\"Could not process op: %p\", op_2);\n+\t\t\tif (enq_tail == 0)\n+\t\t\t\tenq_tail = nb_desc - 1;\n+\t\t\telse\n+\t\t\t\tenq_tail--;\n+\n+\t\t\tcn9k_cpt_inst_submit(&inst[0], lmt_base, io_addr);\n+\t\t\tcount++;\n \t\t\tbreak;\n \t\t}\n \n-\t\tinfl_req->cop = op;\n-\t\tinfl_req->res.cn9k.compcode = CPT_COMP_NOT_DONE;\n-\t\tinst.res_addr = (uint64_t)&infl_req->res;\n+\t\tcn9k_cpt_inst_submit_dual(&inst[0], lmt_base, io_addr);\n \n-\t\tcn9k_cpt_submit_instruction(&inst, qp->lmtline.lmt_base,\n-\t\t\t\t\t qp->lmtline.io_addr);\n-\t\tMOD_INC(pend_q->enq_tail, qp->lf.nb_desc);\n+\t\tcount += 2;\n \t}\n \n+\tpend_q->enq_tail = enq_tail;\n \tpend_q->pending_count += count;\n \tpend_q->time_out = rte_get_timer_cycles() +\n \t\t\t DEFAULT_COMMAND_TIMEOUT * rte_get_timer_hz();\n@@ -219,7 +317,7 @@ cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)\n \t}\n \tinfl_req->op_flags = 0;\n \n-\tret = cn9k_cpt_prepare_instruction(qp, op, infl_req, &inst);\n+\tret = cn9k_cpt_inst_prep(qp, op, infl_req, &inst);\n \tif (unlikely(ret)) {\n \t\tplt_dp_err(\"Could not process op: %p\", op);\n \t\trte_mempool_put(qp->ca.req_mp, infl_req);\n@@ -245,8 +343,7 @@ cn9k_cpt_crypto_adapter_enqueue(uintptr_t tag_op, struct rte_crypto_op *op)\n \tif (!rsp_info->sched_type)\n \t\troc_sso_hws_head_wait(tag_op);\n \n-\tcn9k_cpt_submit_instruction(&inst, qp->lmtline.lmt_base,\n-\t\t\t\t qp->lmtline.io_addr);\n+\tcn9k_cpt_inst_submit(&inst, qp->lmtline.lmt_base, qp->lmtline.io_addr);\n \n \treturn 1;\n }\n@@ -347,14 +444,16 @@ cn9k_cpt_crypto_adapter_dequeue(uintptr_t get_work1)\n static uint16_t\n cn9k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n {\n+\tstruct cpt_inflight_req *infl_req;\n \tstruct cnxk_cpt_qp *qp = qptr;\n \tstruct pending_queue *pend_q;\n-\tstruct cpt_inflight_req *infl_req;\n \tstruct cpt_cn9k_res_s *res;\n \tstruct rte_crypto_op *cop;\n \tuint32_t pq_deq_head;\n \tint i;\n \n+\tconst uint32_t nb_desc = qp->lf.nb_desc;\n+\n \tpend_q = &qp->pend_q;\n \n \tnb_ops = RTE_MIN(nb_ops, pend_q->pending_count);\n@@ -377,7 +476,7 @@ cn9k_cpt_dequeue_burst(void *qptr, struct rte_crypto_op **ops, uint16_t nb_ops)\n \t\t\tbreak;\n \t\t}\n \n-\t\tMOD_INC(pq_deq_head, qp->lf.nb_desc);\n+\t\tMOD_INC(pq_deq_head, nb_desc);\n \n \t\tcop = infl_req->cop;\n \n", "prefixes": [ "7/7" ] }