Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/97735/?format=api
{ "id": 97735, "url": "https://patches.dpdk.org/api/patches/97735/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210902021505.17607-10-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210902021505.17607-10-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210902021505.17607-10-ndabilpuram@marvell.com", "date": "2021-09-02T02:14:47", "name": "[09/27] common/cnxk: align cpt lf enable/disable sequence", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ddb07a9f70185720a54b7577763136e6960dfa2c", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210902021505.17607-10-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 18612, "url": "https://patches.dpdk.org/api/series/18612/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=18612", "date": "2021-09-02T02:14:38", "name": "net/cnxk: support for inline ipsec", "version": 1, "mbox": "https://patches.dpdk.org/series/18612/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/97735/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/97735/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 521C2A0C4C;\n\tThu, 2 Sep 2021 04:17:50 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B4D1F4115E;\n\tThu, 2 Sep 2021 04:17:14 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id E63FF4114E\n for <dev@dpdk.org>; Thu, 2 Sep 2021 04:17:12 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 181HQSfB012709\n for <dev@dpdk.org>; Wed, 1 Sep 2021 19:17:12 -0700", "from dc5-exch02.marvell.com ([199.233.59.182])\n by mx0b-0016f401.pphosted.com with ESMTP id 3atdwq9hs2-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Sep 2021 19:17:12 -0700", "from DC5-EXCH02.marvell.com (10.69.176.39) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Wed, 1 Sep 2021 19:17:10 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com\n (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Wed, 1 Sep 2021 19:17:10 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 0933E3F7040;\n Wed, 1 Sep 2021 19:17:07 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=MlliJfOB98bbeqKpWHM5td6qAumeFPvgTlrjWE2/mMY=;\n b=V6IOxwN+PkBbrYx/n4wKEbgh0RfqoKqEU5c/EwX/oF1Ic4pmffwTz41ixtby6hE9xF/u\n cZxWxDo1cJAfQJxBBd9qML22BbBxom1+ZusFULAYndeRja5J1jKlGHGgt6eHEYDCXQ2Y\n G+h47pakNtTWlsPR+ZGuek2FbTIIv0Jn3qLYU0EF2T2Z5cAP+fuZ4DjLq+Fb+P1Sed6d\n 6xeK4jweWJJgoewDcf6GDLXm8x2DZ2pp2Zg+wgRzlymp0aVWXb4ktWFpeWl4V5PSvtou\n YvvQmG6yIHIES/95Vi20QPgP6XAIDQVssGqgtGOmtt7mpHiGxP47yPFOXLVbWh1heu30 nQ==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <schalla@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 2 Sep 2021 07:44:47 +0530", "Message-ID": "<20210902021505.17607-10-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210902021505.17607-1-ndabilpuram@marvell.com>", "References": "<20210902021505.17607-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "4BTilk5xaZ-ZGJsRfLvLH0yZwP17-zGM", "X-Proofpoint-GUID": "4BTilk5xaZ-ZGJsRfLvLH0yZwP17-zGM", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-01_05,2021-09-01_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 09/27] common/cnxk: align cpt lf enable/disable\n sequence", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "For CPT LF IQ enable, set CPT_LF_CTL[ENA] before setting\nCPT_LF_INPROG[EENA] to true.\n\nFor CPT LF IQ disable, align sequence to that of HRM.\n\nAlso this patch aligns space for instructions in CPT LF\nto ROC_ALIGN to make complete memory cache aligned and\nhas other minor fixes/additions.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/hw/cpt.h | 11 +++++++++++\n drivers/common/cnxk/roc_cpt.c | 42 ++++++++++++++++++++++++++++++++++--------\n drivers/common/cnxk/roc_cpt.h | 8 ++++++++\n 3 files changed, 53 insertions(+), 8 deletions(-)", "diff": "diff --git a/drivers/common/cnxk/hw/cpt.h b/drivers/common/cnxk/hw/cpt.h\nindex 975139f..4d9df59 100644\n--- a/drivers/common/cnxk/hw/cpt.h\n+++ b/drivers/common/cnxk/hw/cpt.h\n@@ -124,6 +124,17 @@ union cpt_lf_misc_int {\n \t} s;\n };\n \n+union cpt_lf_q_grp_ptr {\n+\tuint64_t u;\n+\tstruct {\n+\t\tuint64_t dq_ptr : 15;\n+\t\tuint64_t reserved_31_15 : 17;\n+\t\tuint64_t nq_ptr : 15;\n+\t\tuint64_t reserved_47_62 : 16;\n+\t\tuint64_t xq_xor : 1;\n+\t} s;\n+};\n+\n union cpt_inst_w4 {\n \tuint64_t u64;\n \tstruct {\ndiff --git a/drivers/common/cnxk/roc_cpt.c b/drivers/common/cnxk/roc_cpt.c\nindex f08b5d0..b30f44e 100644\n--- a/drivers/common/cnxk/roc_cpt.c\n+++ b/drivers/common/cnxk/roc_cpt.c\n@@ -437,8 +437,10 @@ cpt_lf_iq_mem_calc(uint32_t nb_desc)\n \tlen += CPT_IQ_FC_LEN;\n \n \t/* For instruction queues */\n-\tlen += CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) * CPT_IQ_NB_DESC_MULTIPLIER *\n-\t sizeof(struct cpt_inst_s);\n+\tlen += PLT_ALIGN(CPT_IQ_NB_DESC_SIZE_DIV40(nb_desc) *\n+\t\t\t\t CPT_IQ_NB_DESC_MULTIPLIER *\n+\t\t\t\t sizeof(struct cpt_inst_s),\n+\t\t\t ROC_ALIGN);\n \n \treturn len;\n }\n@@ -550,6 +552,7 @@ cpt_lf_init(struct roc_cpt_lf *lf)\n \tiq_mem = plt_zmalloc(cpt_lf_iq_mem_calc(lf->nb_desc), ROC_ALIGN);\n \tif (iq_mem == NULL)\n \t\treturn -ENOMEM;\n+\tplt_atomic_thread_fence(__ATOMIC_ACQ_REL);\n \n \tblkaddr = cpt_get_blkaddr(dev);\n \tlf->rbase = dev->bar2 + ((blkaddr << 20) | (lf->lf_id << 12));\n@@ -634,7 +637,7 @@ roc_cpt_dev_init(struct roc_cpt *roc_cpt)\n \t}\n \n \t/* Reserve 1 CPT LF for inline inbound */\n-\tnb_lf_avail = PLT_MIN(nb_lf_avail, ROC_CPT_MAX_LFS - 1);\n+\tnb_lf_avail = PLT_MIN(nb_lf_avail, (uint16_t)(ROC_CPT_MAX_LFS - 1));\n \n \troc_cpt->nb_lf_avail = nb_lf_avail;\n \n@@ -770,8 +773,10 @@ void\n roc_cpt_iq_disable(struct roc_cpt_lf *lf)\n {\n \tunion cpt_lf_ctl lf_ctl = {.u = 0x0};\n+\tunion cpt_lf_q_grp_ptr grp_ptr;\n \tunion cpt_lf_inprog lf_inprog;\n \tint timeout = 20;\n+\tint cnt;\n \n \t/* Disable instructions enqueuing */\n \tplt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);\n@@ -795,6 +800,27 @@ roc_cpt_iq_disable(struct roc_cpt_lf *lf)\n \t */\n \tlf_inprog.s.eena = 0x0;\n \tplt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);\n+\n+\t/* Wait for instruction queue to become empty */\n+\tcnt = 0;\n+\tdo {\n+\t\tlf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);\n+\t\tif (lf_inprog.s.grb_partial)\n+\t\t\tcnt = 0;\n+\t\telse\n+\t\t\tcnt++;\n+\t\tgrp_ptr.u = plt_read64(lf->rbase + CPT_LF_Q_GRP_PTR);\n+\t} while ((cnt < 10) && (grp_ptr.s.nq_ptr != grp_ptr.s.dq_ptr));\n+\n+\tcnt = 0;\n+\tdo {\n+\t\tlf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);\n+\t\tif ((lf_inprog.s.inflight == 0) && (lf_inprog.s.gwb_cnt < 40) &&\n+\t\t ((lf_inprog.s.grb_cnt == 0) || (lf_inprog.s.grb_cnt == 40)))\n+\t\t\tcnt++;\n+\t\telse\n+\t\t\tcnt = 0;\n+\t} while (cnt < 10);\n }\n \n void\n@@ -806,11 +832,6 @@ roc_cpt_iq_enable(struct roc_cpt_lf *lf)\n \t/* Disable command queue */\n \troc_cpt_iq_disable(lf);\n \n-\t/* Enable command queue execution */\n-\tlf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);\n-\tlf_inprog.s.eena = 1;\n-\tplt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);\n-\n \t/* Enable instruction queue enqueuing */\n \tlf_ctl.u = plt_read64(lf->rbase + CPT_LF_CTL);\n \tlf_ctl.s.ena = 1;\n@@ -819,6 +840,11 @@ roc_cpt_iq_enable(struct roc_cpt_lf *lf)\n \tlf_ctl.s.fc_hyst_bits = lf->fc_hyst_bits;\n \tplt_write64(lf_ctl.u, lf->rbase + CPT_LF_CTL);\n \n+\t/* Enable command queue execution */\n+\tlf_inprog.u = plt_read64(lf->rbase + CPT_LF_INPROG);\n+\tlf_inprog.s.eena = 1;\n+\tplt_write64(lf_inprog.u, lf->rbase + CPT_LF_INPROG);\n+\n \tcpt_lf_dump(lf);\n }\n \ndiff --git a/drivers/common/cnxk/roc_cpt.h b/drivers/common/cnxk/roc_cpt.h\nindex 9b55303..2ac3197 100644\n--- a/drivers/common/cnxk/roc_cpt.h\n+++ b/drivers/common/cnxk/roc_cpt.h\n@@ -75,6 +75,14 @@\n #define ROC_CPT_TUNNEL_IPV4_HDR_LEN 20\n #define ROC_CPT_TUNNEL_IPV6_HDR_LEN 40\n \n+#define ROC_CPT_CCM_AAD_DATA 1\n+#define ROC_CPT_CCM_MSG_LEN 4\n+#define ROC_CPT_CCM_ICV_LEN 16\n+#define ROC_CPT_CCM_FLAGS \\\n+\t((ROC_CPT_CCM_AAD_DATA << 6) | \\\n+\t (((ROC_CPT_CCM_ICV_LEN - 2) / 2) << 3) | (ROC_CPT_CCM_MSG_LEN - 1))\n+#define ROC_CPT_CCM_SALT_LEN 3\n+\n struct roc_cpt_lmtline {\n \tuint64_t io_addr;\n \tuint64_t *fc_addr;\n", "prefixes": [ "09/27" ] }