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GET /api/patches/97731/?format=api
{ "id": 97731, "url": "https://patches.dpdk.org/api/patches/97731/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210902021505.17607-6-ndabilpuram@marvell.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210902021505.17607-6-ndabilpuram@marvell.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210902021505.17607-6-ndabilpuram@marvell.com", "date": "2021-09-02T02:14:43", "name": "[05/27] common/cnxk: add nix inline device irq API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "429ad3f58e528a0bfabb7f01c57623fe3471cf51", "submitter": { "id": 1202, "url": "https://patches.dpdk.org/api/people/1202/?format=api", "name": "Nithin Dabilpuram", "email": "ndabilpuram@marvell.com" }, "delegate": { "id": 310, "url": "https://patches.dpdk.org/api/users/310/?format=api", "username": "jerin", "first_name": "Jerin", "last_name": "Jacob", "email": "jerinj@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210902021505.17607-6-ndabilpuram@marvell.com/mbox/", "series": [ { "id": 18612, "url": "https://patches.dpdk.org/api/series/18612/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=18612", "date": "2021-09-02T02:14:38", "name": "net/cnxk: support for inline ipsec", "version": 1, "mbox": "https://patches.dpdk.org/series/18612/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/97731/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/97731/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 2D3A3A0C4C;\n\tThu, 2 Sep 2021 04:17:19 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 086FB41135;\n\tThu, 2 Sep 2021 04:17:03 +0200 (CEST)", "from mx0b-0016f401.pphosted.com (mx0b-0016f401.pphosted.com\n [67.231.156.173])\n by mails.dpdk.org (Postfix) with ESMTP id 54E00410FF\n for <dev@dpdk.org>; Thu, 2 Sep 2021 04:17:01 +0200 (CEST)", "from pps.filterd (m0045851.ppops.net [127.0.0.1])\n by mx0b-0016f401.pphosted.com (8.16.1.2/8.16.1.2) with SMTP id 181HQSf6012709\n for <dev@dpdk.org>; Wed, 1 Sep 2021 19:17:00 -0700", "from dc5-exch01.marvell.com ([199.233.59.181])\n by mx0b-0016f401.pphosted.com with ESMTP id 3atdwq9hqx-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-SHA384 bits=256 verify=NOT)\n for <dev@dpdk.org>; Wed, 01 Sep 2021 19:17:00 -0700", "from DC5-EXCH01.marvell.com (10.69.176.38) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server (TLS) id 15.0.1497.18;\n Wed, 1 Sep 2021 19:16:58 -0700", "from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com\n (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.18 via Frontend\n Transport; Wed, 1 Sep 2021 19:16:58 -0700", "from hyd1588t430.marvell.com (unknown [10.29.52.204])\n by maili.marvell.com (Postfix) with ESMTP id 61BD93F7040;\n Wed, 1 Sep 2021 19:16:56 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com;\n h=from : to : cc :\n subject : date : message-id : in-reply-to : references : mime-version :\n content-type; s=pfpt0220; bh=XtoxIGCYV0JlXkigAP7eTr7Qcs3yKGcPhy+oiLE+LuA=;\n b=hdXuB3YbrHdg8ljrKhpWJ+9viXg8KJB2+vvBB1hFIqziP5jbYSPyiMmZXzpv4zl3F4XZ\n FnLwrWjgr2wCAvUdDAoEkUWp+3oYRf+bBUBXMJfPtZjZbIAyToDSaKL5sGLUUGoGn5Z8\n Gr2tLFI04qxzk8Yl8Vb2EnlsTHUeNC21v7Nq2oeGzKIrygRTCBsWLtGn6qYJdmLG67Js\n jN+J0/ntE5SY7x79lhxflTNKku2bQGXMniF7gGcyszwGSZqtj6vVdrPLGQqzi6F0Sl/U\n a21SFRyuBR7TWzwT9QvFWWpLqZKFRExyinzwjMa12zGqyImyfnIoxRI2b/Ea2gDPoQAs wA==", "From": "Nithin Dabilpuram <ndabilpuram@marvell.com>", "To": "Nithin Dabilpuram <ndabilpuram@marvell.com>, Kiran Kumar K\n <kirankumark@marvell.com>, Sunil Kumar Kori <skori@marvell.com>, Satha Rao\n <skoteshwar@marvell.com>", "CC": "<jerinj@marvell.com>, <schalla@marvell.com>, <dev@dpdk.org>", "Date": "Thu, 2 Sep 2021 07:44:43 +0530", "Message-ID": "<20210902021505.17607-6-ndabilpuram@marvell.com>", "X-Mailer": "git-send-email 2.8.4", "In-Reply-To": "<20210902021505.17607-1-ndabilpuram@marvell.com>", "References": "<20210902021505.17607-1-ndabilpuram@marvell.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Proofpoint-ORIG-GUID": "xnc0t7npr_XVNKl9jinkpiPzj6JvoqgA", "X-Proofpoint-GUID": "xnc0t7npr_XVNKl9jinkpiPzj6JvoqgA", "X-Proofpoint-Virus-Version": "vendor=baseguard\n engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475\n definitions=2021-09-01_05,2021-09-01_01,2020-04-07_01", "Subject": "[dpdk-dev] [PATCH 05/27] common/cnxk: add nix inline device irq API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add API to setup nix inline device IRQ's.\n\nSigned-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>\n---\n drivers/common/cnxk/meson.build | 1 +\n drivers/common/cnxk/roc_api.h | 3 +\n drivers/common/cnxk/roc_irq.c | 7 +-\n drivers/common/cnxk/roc_nix_inl.h | 10 +\n drivers/common/cnxk/roc_nix_inl_dev_irq.c | 359 ++++++++++++++++++++++++++++++\n drivers/common/cnxk/roc_nix_inl_priv.h | 57 +++++\n drivers/common/cnxk/roc_platform.h | 9 +-\n drivers/common/cnxk/roc_priv.h | 3 +\n 8 files changed, 442 insertions(+), 7 deletions(-)\n create mode 100644 drivers/common/cnxk/roc_nix_inl.h\n create mode 100644 drivers/common/cnxk/roc_nix_inl_dev_irq.c\n create mode 100644 drivers/common/cnxk/roc_nix_inl_priv.h", "diff": "diff --git a/drivers/common/cnxk/meson.build b/drivers/common/cnxk/meson.build\nindex 8a551d1..207ca00 100644\n--- a/drivers/common/cnxk/meson.build\n+++ b/drivers/common/cnxk/meson.build\n@@ -28,6 +28,7 @@ sources = files(\n 'roc_nix_debug.c',\n 'roc_nix_fc.c',\n 'roc_nix_irq.c',\n+ 'roc_nix_inl_dev_irq.c',\n 'roc_nix_mac.c',\n 'roc_nix_mcast.c',\n 'roc_nix_npc.c',\ndiff --git a/drivers/common/cnxk/roc_api.h b/drivers/common/cnxk/roc_api.h\nindex 7dec845..c1af95e 100644\n--- a/drivers/common/cnxk/roc_api.h\n+++ b/drivers/common/cnxk/roc_api.h\n@@ -129,4 +129,7 @@\n /* HASH computation */\n #include \"roc_hash.h\"\n \n+/* NIX Inline dev */\n+#include \"roc_nix_inl.h\"\n+\n #endif /* _ROC_API_H_ */\ndiff --git a/drivers/common/cnxk/roc_irq.c b/drivers/common/cnxk/roc_irq.c\nindex 4c2b4c3..28fe691 100644\n--- a/drivers/common/cnxk/roc_irq.c\n+++ b/drivers/common/cnxk/roc_irq.c\n@@ -138,9 +138,10 @@ dev_irq_register(struct plt_intr_handle *intr_handle, plt_intr_callback_fn cb,\n \t\tirq_init(intr_handle);\n \t}\n \n-\tif (vec > intr_handle->max_intr) {\n-\t\tplt_err(\"Vector=%d greater than max_intr=%d\", vec,\n-\t\t\tintr_handle->max_intr);\n+\tif (vec > intr_handle->max_intr || vec >= PLT_DIM(intr_handle->efds)) {\n+\t\tplt_err(\"Vector=%d greater than max_intr=%d or \"\n+\t\t\t\"max_efd=%\" PRIu64,\n+\t\t\tvec, intr_handle->max_intr, PLT_DIM(intr_handle->efds));\n \t\treturn -EINVAL;\n \t}\n \ndiff --git a/drivers/common/cnxk/roc_nix_inl.h b/drivers/common/cnxk/roc_nix_inl.h\nnew file mode 100644\nindex 0000000..1ec3dda\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_inl.h\n@@ -0,0 +1,10 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef _ROC_NIX_INL_H_\n+#define _ROC_NIX_INL_H_\n+\n+/* Inline device SSO Work callback */\n+typedef void (*roc_nix_inl_sso_work_cb_t)(uint64_t *gw, void *args);\n+\n+#endif /* _ROC_NIX_INL_H_ */\ndiff --git a/drivers/common/cnxk/roc_nix_inl_dev_irq.c b/drivers/common/cnxk/roc_nix_inl_dev_irq.c\nnew file mode 100644\nindex 0000000..25ed42f\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_inl_dev_irq.c\n@@ -0,0 +1,359 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+\n+#include \"roc_api.h\"\n+#include \"roc_priv.h\"\n+\n+static void\n+nix_inl_sso_work_cb(struct nix_inl_dev *inl_dev)\n+{\n+\tuintptr_t getwrk_op = inl_dev->ssow_base + SSOW_LF_GWS_OP_GET_WORK0;\n+\tuintptr_t tag_wqe_op = inl_dev->ssow_base + SSOW_LF_GWS_WQE0;\n+\tuint32_t wdata = BIT(16) | 1;\n+\tunion {\n+\t\t__uint128_t get_work;\n+\t\tuint64_t u64[2];\n+\t} gw;\n+\tuint64_t work;\n+\n+again:\n+\t/* Try to do get work */\n+\tgw.get_work = wdata;\n+\tplt_write64(gw.u64[0], getwrk_op);\n+\tdo {\n+\t\troc_load_pair(gw.u64[0], gw.u64[1], tag_wqe_op);\n+\t} while (gw.u64[0] & BIT_ULL(63));\n+\n+\twork = gw.u64[1];\n+\t/* Do we have any work? */\n+\tif (work) {\n+\t\tif (inl_dev->work_cb)\n+\t\t\tinl_dev->work_cb(gw.u64, inl_dev->cb_args);\n+\t\telse\n+\t\t\tplt_warn(\"Undelivered inl dev work gw0: %p gw1: %p\",\n+\t\t\t\t (void *)gw.u64[0], (void *)gw.u64[1]);\n+\t\tgoto again;\n+\t}\n+\n+\tplt_atomic_thread_fence(__ATOMIC_ACQ_REL);\n+}\n+\n+static int\n+nix_inl_nix_reg_dump(struct nix_inl_dev *inl_dev)\n+{\n+\tuintptr_t nix_base = inl_dev->nix_base;\n+\n+\t/* General registers */\n+\tnix_lf_gen_reg_dump(nix_base, NULL);\n+\n+\t/* Rx, Tx stat registers */\n+\tnix_lf_stat_reg_dump(nix_base, NULL, inl_dev->lf_tx_stats,\n+\t\t\t inl_dev->lf_rx_stats);\n+\n+\t/* Intr registers */\n+\tnix_lf_int_reg_dump(nix_base, NULL, inl_dev->qints, inl_dev->cints);\n+\n+\treturn 0;\n+}\n+\n+static void\n+nix_inl_sso_hwgrp_irq(void *param)\n+{\n+\tstruct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;\n+\tuintptr_t sso_base = inl_dev->sso_base;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(sso_base + SSO_LF_GGRP_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\t/* Check for work executable interrupt */\n+\tif (intr & BIT(1))\n+\t\tnix_inl_sso_work_cb(inl_dev);\n+\n+\tif (!(intr & BIT(1)))\n+\t\tplt_err(\"GGRP 0 GGRP_INT=0x%\" PRIx64 \"\", intr);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, sso_base + SSO_LF_GGRP_INT);\n+}\n+\n+static void\n+nix_inl_sso_hws_irq(void *param)\n+{\n+\tstruct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;\n+\tuintptr_t ssow_base = inl_dev->ssow_base;\n+\tuint64_t intr;\n+\n+\tintr = plt_read64(ssow_base + SSOW_LF_GWS_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"GWS 0 GWS_INT=0x%\" PRIx64 \"\", intr);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, ssow_base + SSOW_LF_GWS_INT);\n+}\n+\n+int\n+nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev)\n+{\n+\tstruct plt_intr_handle *handle = &inl_dev->pci_dev->intr_handle;\n+\tuintptr_t ssow_base = inl_dev->ssow_base;\n+\tuintptr_t sso_base = inl_dev->sso_base;\n+\tuint16_t sso_msixoff, ssow_msixoff;\n+\tint rc;\n+\n+\tssow_msixoff = inl_dev->ssow_msixoff;\n+\tsso_msixoff = inl_dev->sso_msixoff;\n+\tif (sso_msixoff == MSIX_VECTOR_INVALID ||\n+\t ssow_msixoff == MSIX_VECTOR_INVALID) {\n+\t\tplt_err(\"Invalid SSO/SSOW MSIX offsets (0x%x, 0x%x)\",\n+\t\t\tsso_msixoff, ssow_msixoff);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/*\n+\t * Setup SSOW interrupt\n+\t */\n+\n+\t/* Clear SSOW interrupt enable */\n+\tplt_write64(~0ull, ssow_base + SSOW_LF_GWS_INT_ENA_W1C);\n+\t/* Register interrupt with vfio */\n+\trc = dev_irq_register(handle, nix_inl_sso_hws_irq, inl_dev,\n+\t\t\t ssow_msixoff + SSOW_LF_INT_VEC_IOP);\n+\t/* Set SSOW interrupt enable */\n+\tplt_write64(~0ull, ssow_base + SSOW_LF_GWS_INT_ENA_W1S);\n+\n+\t/*\n+\t * Setup SSO/HWGRP interrupt\n+\t */\n+\n+\t/* Clear SSO interrupt enable */\n+\tplt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1C);\n+\t/* Register IRQ */\n+\trc |= dev_irq_register(handle, nix_inl_sso_hwgrp_irq, (void *)inl_dev,\n+\t\t\t sso_msixoff + SSO_LF_INT_VEC_GRP);\n+\t/* Enable hw interrupt */\n+\tplt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1S);\n+\n+\t/* Setup threshold for work exec interrupt to 1 wqe in IAQ */\n+\tplt_write64(0x1ull, sso_base + SSO_LF_GGRP_INT_THR);\n+\n+\treturn rc;\n+}\n+\n+void\n+nix_inl_sso_unregister_irqs(struct nix_inl_dev *inl_dev)\n+{\n+\tstruct plt_intr_handle *handle = &inl_dev->pci_dev->intr_handle;\n+\tuintptr_t ssow_base = inl_dev->ssow_base;\n+\tuintptr_t sso_base = inl_dev->sso_base;\n+\tuint16_t sso_msixoff, ssow_msixoff;\n+\n+\tssow_msixoff = inl_dev->ssow_msixoff;\n+\tsso_msixoff = inl_dev->sso_msixoff;\n+\n+\t/* Clear SSOW interrupt enable */\n+\tplt_write64(~0ull, ssow_base + SSOW_LF_GWS_INT_ENA_W1C);\n+\t/* Clear SSO/HWGRP interrupt enable */\n+\tplt_write64(~0ull, sso_base + SSO_LF_GGRP_INT_ENA_W1C);\n+\t/* Clear SSO threshold */\n+\tplt_write64(0, sso_base + SSO_LF_GGRP_INT_THR);\n+\n+\t/* Unregister IRQ */\n+\tdev_irq_unregister(handle, nix_inl_sso_hws_irq, (void *)inl_dev,\n+\t\t\t ssow_msixoff + SSOW_LF_INT_VEC_IOP);\n+\tdev_irq_unregister(handle, nix_inl_sso_hwgrp_irq, (void *)inl_dev,\n+\t\t\t sso_msixoff + SSO_LF_INT_VEC_GRP);\n+}\n+\n+static void\n+nix_inl_nix_q_irq(void *param)\n+{\n+\tstruct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;\n+\tuintptr_t nix_base = inl_dev->nix_base;\n+\tstruct dev *dev = &inl_dev->dev;\n+\tvolatile void *ctx;\n+\tuint64_t reg, intr;\n+\tuint8_t irq;\n+\tint rc;\n+\n+\tintr = plt_read64(nix_base + NIX_LF_QINTX_INT(0));\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"Queue_intr=0x%\" PRIx64 \" qintx 0 pf=%d, vf=%d\", intr, dev->pf,\n+\t\tdev->vf);\n+\n+\t/* Get and clear RQ0 interrupt */\n+\treg = roc_atomic64_add_nosync(0,\n+\t\t\t\t (int64_t *)(nix_base + NIX_LF_RQ_OP_INT));\n+\tif (reg & BIT_ULL(42) /* OP_ERR */) {\n+\t\tplt_err(\"Failed to get rq_int\");\n+\t\treturn;\n+\t}\n+\tirq = reg & 0xff;\n+\tplt_write64(0 | irq, nix_base + NIX_LF_RQ_OP_INT);\n+\n+\tif (irq & BIT_ULL(NIX_RQINT_DROP))\n+\t\tplt_err(\"RQ=0 NIX_RQINT_DROP\");\n+\n+\tif (irq & BIT_ULL(NIX_RQINT_RED))\n+\t\tplt_err(\"RQ=0 NIX_RQINT_RED\");\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, nix_base + NIX_LF_QINTX_INT(0));\n+\n+\t/* Dump registers to std out */\n+\tnix_inl_nix_reg_dump(inl_dev);\n+\n+\t/* Dump RQ 0 */\n+\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, 0, &ctx);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to get rq context\");\n+\t\treturn;\n+\t}\n+\tnix_lf_rq_dump(ctx);\n+}\n+\n+static void\n+nix_inl_nix_ras_irq(void *param)\n+{\n+\tstruct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;\n+\tuintptr_t nix_base = inl_dev->nix_base;\n+\tstruct dev *dev = &inl_dev->dev;\n+\tvolatile void *ctx;\n+\tuint64_t intr;\n+\tint rc;\n+\n+\tintr = plt_read64(nix_base + NIX_LF_RAS);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"Ras_intr=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n+\t/* Clear interrupt */\n+\tplt_write64(intr, nix_base + NIX_LF_RAS);\n+\n+\t/* Dump registers to std out */\n+\tnix_inl_nix_reg_dump(inl_dev);\n+\n+\t/* Dump RQ 0 */\n+\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, 0, &ctx);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to get rq context\");\n+\t\treturn;\n+\t}\n+\tnix_lf_rq_dump(ctx);\n+}\n+\n+static void\n+nix_inl_nix_err_irq(void *param)\n+{\n+\tstruct nix_inl_dev *inl_dev = (struct nix_inl_dev *)param;\n+\tuintptr_t nix_base = inl_dev->nix_base;\n+\tstruct dev *dev = &inl_dev->dev;\n+\tvolatile void *ctx;\n+\tuint64_t intr;\n+\tint rc;\n+\n+\tintr = plt_read64(nix_base + NIX_LF_ERR_INT);\n+\tif (intr == 0)\n+\t\treturn;\n+\n+\tplt_err(\"Err_irq=0x%\" PRIx64 \" pf=%d, vf=%d\", intr, dev->pf, dev->vf);\n+\n+\t/* Clear interrupt */\n+\tplt_write64(intr, nix_base + NIX_LF_ERR_INT);\n+\n+\t/* Dump registers to std out */\n+\tnix_inl_nix_reg_dump(inl_dev);\n+\n+\t/* Dump RQ 0 */\n+\trc = nix_q_ctx_get(dev, NIX_AQ_CTYPE_RQ, 0, &ctx);\n+\tif (rc) {\n+\t\tplt_err(\"Failed to get rq context\");\n+\t\treturn;\n+\t}\n+\tnix_lf_rq_dump(ctx);\n+}\n+\n+int\n+nix_inl_nix_register_irqs(struct nix_inl_dev *inl_dev)\n+{\n+\tstruct plt_intr_handle *handle = &inl_dev->pci_dev->intr_handle;\n+\tuintptr_t nix_base = inl_dev->nix_base;\n+\tuint16_t msixoff;\n+\tint rc;\n+\n+\tmsixoff = inl_dev->nix_msixoff;\n+\tif (msixoff == MSIX_VECTOR_INVALID) {\n+\t\tplt_err(\"Invalid NIXLF MSIX vector offset: 0x%x\", msixoff);\n+\t\treturn -EINVAL;\n+\t}\n+\n+\t/* Disable err interrupts */\n+\tplt_write64(~0ull, nix_base + NIX_LF_ERR_INT_ENA_W1C);\n+\t/* DIsable RAS interrupts */\n+\tplt_write64(~0ull, nix_base + NIX_LF_RAS_ENA_W1C);\n+\n+\t/* Register err irq */\n+\trc = dev_irq_register(handle, nix_inl_nix_err_irq, inl_dev,\n+\t\t\t msixoff + NIX_LF_INT_VEC_ERR_INT);\n+\trc |= dev_irq_register(handle, nix_inl_nix_ras_irq, inl_dev,\n+\t\t\t msixoff + NIX_LF_INT_VEC_POISON);\n+\n+\t/* Enable all nix lf error irqs except RQ_DISABLED and CQ_DISABLED */\n+\tplt_write64(~(BIT_ULL(11) | BIT_ULL(24)),\n+\t\t nix_base + NIX_LF_ERR_INT_ENA_W1S);\n+\t/* Enable RAS interrupts */\n+\tplt_write64(~0ull, nix_base + NIX_LF_RAS_ENA_W1S);\n+\n+\t/* Setup queue irq for RQ 0 */\n+\n+\t/* Clear QINT CNT, interrupt */\n+\tplt_write64(0, nix_base + NIX_LF_QINTX_CNT(0));\n+\tplt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1C(0));\n+\n+\t/* Register queue irq vector */\n+\trc |= dev_irq_register(handle, nix_inl_nix_q_irq, inl_dev,\n+\t\t\t msixoff + NIX_LF_INT_VEC_QINT_START);\n+\n+\tplt_write64(0, nix_base + NIX_LF_QINTX_CNT(0));\n+\tplt_write64(0, nix_base + NIX_LF_QINTX_INT(0));\n+\t/* Enable QINT interrupt */\n+\tplt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1S(0));\n+\n+\treturn rc;\n+}\n+\n+void\n+nix_inl_nix_unregister_irqs(struct nix_inl_dev *inl_dev)\n+{\n+\tstruct plt_intr_handle *handle = &inl_dev->pci_dev->intr_handle;\n+\tuintptr_t nix_base = inl_dev->nix_base;\n+\tuint16_t msixoff;\n+\n+\tmsixoff = inl_dev->nix_msixoff;\n+\t/* Disable err interrupts */\n+\tplt_write64(~0ull, nix_base + NIX_LF_ERR_INT_ENA_W1C);\n+\t/* DIsable RAS interrupts */\n+\tplt_write64(~0ull, nix_base + NIX_LF_RAS_ENA_W1C);\n+\n+\tdev_irq_unregister(handle, nix_inl_nix_err_irq, inl_dev,\n+\t\t\t msixoff + NIX_LF_INT_VEC_ERR_INT);\n+\tdev_irq_unregister(handle, nix_inl_nix_ras_irq, inl_dev,\n+\t\t\t msixoff + NIX_LF_INT_VEC_POISON);\n+\n+\t/* Clear QINT CNT */\n+\tplt_write64(0, nix_base + NIX_LF_QINTX_CNT(0));\n+\tplt_write64(0, nix_base + NIX_LF_QINTX_INT(0));\n+\n+\t/* Disable QINT interrupt */\n+\tplt_write64(~0ull, nix_base + NIX_LF_QINTX_ENA_W1C(0));\n+\n+\t/* Unregister queue irq vector */\n+\tdev_irq_unregister(handle, nix_inl_nix_q_irq, inl_dev,\n+\t\t\t msixoff + NIX_LF_INT_VEC_QINT_START);\n+}\ndiff --git a/drivers/common/cnxk/roc_nix_inl_priv.h b/drivers/common/cnxk/roc_nix_inl_priv.h\nnew file mode 100644\nindex 0000000..f424009\n--- /dev/null\n+++ b/drivers/common/cnxk/roc_nix_inl_priv.h\n@@ -0,0 +1,57 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright(C) 2021 Marvell.\n+ */\n+#ifndef _ROC_NIX_INL_PRIV_H_\n+#define _ROC_NIX_INL_PRIV_H_\n+\n+struct nix_inl_dev {\n+\t/* Base device object */\n+\tstruct dev dev;\n+\n+\t/* PCI device */\n+\tstruct plt_pci_device *pci_dev;\n+\n+\t/* LF specific BAR2 regions */\n+\tuintptr_t nix_base;\n+\tuintptr_t ssow_base;\n+\tuintptr_t sso_base;\n+\n+\t/* MSIX vector offsets */\n+\tuint16_t nix_msixoff;\n+\tuint16_t ssow_msixoff;\n+\tuint16_t sso_msixoff;\n+\n+\t/* SSO data */\n+\tuint32_t xaq_buf_size;\n+\tuint32_t xae_waes;\n+\tuint32_t iue;\n+\tuint64_t xaq_aura;\n+\tvoid *xaq_mem;\n+\troc_nix_inl_sso_work_cb_t work_cb;\n+\tvoid *cb_args;\n+\n+\t/* NIX data */\n+\tuint8_t lf_tx_stats;\n+\tuint8_t lf_rx_stats;\n+\tuint16_t cints;\n+\tuint16_t qints;\n+\tstruct roc_nix_rq rq;\n+\tuint16_t rq_refs;\n+\tbool is_nix1;\n+\n+\t/* NIX/CPT data */\n+\tvoid *inb_sa_base;\n+\tuint16_t inb_sa_sz;\n+\n+\t/* Device arguments */\n+\tuint8_t selftest;\n+\tuint16_t ipsec_in_max_spi;\n+};\n+\n+int nix_inl_sso_register_irqs(struct nix_inl_dev *inl_dev);\n+void nix_inl_sso_unregister_irqs(struct nix_inl_dev *inl_dev);\n+\n+int nix_inl_nix_register_irqs(struct nix_inl_dev *inl_dev);\n+void nix_inl_nix_unregister_irqs(struct nix_inl_dev *inl_dev);\n+\n+#endif /* _ROC_NIX_INL_PRIV_H_ */\ndiff --git a/drivers/common/cnxk/roc_platform.h b/drivers/common/cnxk/roc_platform.h\nindex 285b24b..177db3d 100644\n--- a/drivers/common/cnxk/roc_platform.h\n+++ b/drivers/common/cnxk/roc_platform.h\n@@ -113,10 +113,11 @@\n #define plt_write64(val, addr) \\\n \trte_write64_relaxed((val), (volatile void *)(addr))\n \n-#define plt_wmb() rte_wmb()\n-#define plt_rmb() rte_rmb()\n-#define plt_io_wmb() rte_io_wmb()\n-#define plt_io_rmb() rte_io_rmb()\n+#define plt_wmb()\t\trte_wmb()\n+#define plt_rmb()\t\trte_rmb()\n+#define plt_io_wmb()\t\trte_io_wmb()\n+#define plt_io_rmb()\t\trte_io_rmb()\n+#define plt_atomic_thread_fence rte_atomic_thread_fence\n \n #define plt_mmap mmap\n #define PLT_PROT_READ PROT_READ\ndiff --git a/drivers/common/cnxk/roc_priv.h b/drivers/common/cnxk/roc_priv.h\nindex 7494b8d..f72bbd5 100644\n--- a/drivers/common/cnxk/roc_priv.h\n+++ b/drivers/common/cnxk/roc_priv.h\n@@ -38,4 +38,7 @@\n /* CPT */\n #include \"roc_cpt_priv.h\"\n \n+/* NIX Inline dev */\n+#include \"roc_nix_inl_priv.h\"\n+\n #endif /* _ROC_PRIV_H_ */\n", "prefixes": [ "05/27" ] }