Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/97710/?format=api
{ "id": 97710, "url": "https://patches.dpdk.org/api/patches/97710/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210901163216.120087-6-bruce.richardson@intel.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210901163216.120087-6-bruce.richardson@intel.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210901163216.120087-6-bruce.richardson@intel.com", "date": "2021-09-01T16:32:15", "name": "[v2,5/6] app/test: test dmadev instance failure handling", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "043912241106cc5b6eefef65d65359f89398530c", "submitter": { "id": 20, "url": "https://patches.dpdk.org/api/people/20/?format=api", "name": "Bruce Richardson", "email": "bruce.richardson@intel.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210901163216.120087-6-bruce.richardson@intel.com/mbox/", "series": [ { "id": 18607, "url": "https://patches.dpdk.org/api/series/18607/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=18607", "date": "2021-09-01T16:32:10", "name": "add test suite for DMA drivers", "version": 2, "mbox": "https://patches.dpdk.org/series/18607/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/97710/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/97710/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 148F4A0C47;\n\tWed, 1 Sep 2021 18:32:55 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 513E241178;\n\tWed, 1 Sep 2021 18:32:45 +0200 (CEST)", "from mga12.intel.com (mga12.intel.com [192.55.52.136])\n by mails.dpdk.org (Postfix) with ESMTP id 3D825410E9\n for <dev@dpdk.org>; Wed, 1 Sep 2021 18:32:43 +0200 (CEST)", "from orsmga005.jf.intel.com ([10.7.209.41])\n by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384;\n 01 Sep 2021 09:32:42 -0700", "from silpixa00399126.ir.intel.com ([10.237.223.29])\n by orsmga005.jf.intel.com with ESMTP; 01 Sep 2021 09:32:41 -0700" ], "X-IronPort-AV": [ "E=McAfee;i=\"6200,9189,10094\"; a=\"198359913\"", "E=Sophos;i=\"5.84,369,1620716400\"; d=\"scan'208\";a=\"198359913\"", "E=Sophos;i=\"5.84,369,1620716400\"; d=\"scan'208\";a=\"645812885\"" ], "X-ExtLoop1": "1", "From": "Bruce Richardson <bruce.richardson@intel.com>", "To": "dev@dpdk.org", "Cc": "conor.walsh@intel.com, kevin.laatz@intel.com, fengchengwen@huawei.com,\n jerinj@marvell.com, Bruce Richardson <bruce.richardson@intel.com>", "Date": "Wed, 1 Sep 2021 17:32:15 +0100", "Message-Id": "<20210901163216.120087-6-bruce.richardson@intel.com>", "X-Mailer": "git-send-email 2.30.2", "In-Reply-To": "<20210901163216.120087-1-bruce.richardson@intel.com>", "References": "<20210826183301.333442-1-bruce.richardson@intel.com>\n <20210901163216.120087-1-bruce.richardson@intel.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Subject": "[dpdk-dev] [PATCH v2 5/6] app/test: test dmadev instance failure\n handling", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Add a series of tests to inject bad copy operations into a dmadev to\ntest the error handling and reporting capabilities. Various combinations\nof errors in various positions in a burst are tested, as are errors in\nbursts with fence flag set, and multiple errors in a single burst.\n\nSigned-off-by: Bruce Richardson <bruce.richardson@intel.com>\n---\n app/test/test_dmadev.c | 427 +++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 427 insertions(+)", "diff": "diff --git a/app/test/test_dmadev.c b/app/test/test_dmadev.c\nindex 7a808a9cba..5d7b6ddd87 100644\n--- a/app/test/test_dmadev.c\n+++ b/app/test/test_dmadev.c\n@@ -302,6 +302,414 @@ test_enqueue_copies(int dev_id, uint16_t vchan)\n \t\t\t|| do_multi_copies(dev_id, vchan, 0, 0, 1);\n }\n \n+/* Failure handling test cases - global macros and variables for those tests*/\n+#define COMP_BURST_SZ\t16\n+#define OPT_FENCE(idx) ((fence && idx == 8) ? RTE_DMA_OP_FLAG_FENCE : 0)\n+\n+static int\n+test_failure_in_full_burst(int dev_id, uint16_t vchan, bool fence,\n+\t\tstruct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx)\n+{\n+\t/* Test single full batch statuses with failures */\n+\tenum rte_dma_status_code status[COMP_BURST_SZ];\n+\tstruct rte_dmadev_stats baseline, stats;\n+\tuint16_t invalid_addr_id = 0;\n+\tuint16_t idx;\n+\tuint16_t count, status_count;\n+\tunsigned int i;\n+\tbool error = 0;\n+\tint err_count = 0;\n+\n+\trte_dmadev_stats_get(dev_id, vchan, &baseline); /* get a baseline set of stats */\n+\tfor (i = 0; i < COMP_BURST_SZ; i++) {\n+\t\tint id = rte_dmadev_copy(dev_id, vchan,\n+\t\t\t\t(i == fail_idx ? 0 : (srcs[i]->buf_iova + srcs[i]->data_off)),\n+\t\t\t\tdsts[i]->buf_iova + dsts[i]->data_off,\n+\t\t\t\tCOPY_LEN, OPT_FENCE(i));\n+\t\tif (id < 0) {\n+\t\t\tPRINT_ERR(\"Error with rte_dmadev_copy for buffer %u\\n\", i);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif (i == fail_idx)\n+\t\t\tinvalid_addr_id = id;\n+\t}\n+\trte_dmadev_submit(dev_id, vchan);\n+\trte_dmadev_stats_get(dev_id, vchan, &stats);\n+\tif (stats.submitted != baseline.submitted + COMP_BURST_SZ) {\n+\t\tPRINT_ERR(\"Submitted stats value not as expected, %\"PRIu64\" not %\"PRIu64\"\\n\",\n+\t\t\t\tstats.submitted, baseline.submitted + COMP_BURST_SZ);\n+\t\treturn -1;\n+\t}\n+\n+\tawait_hw(dev_id, vchan);\n+\n+\tcount = rte_dmadev_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error);\n+\tif (count != fail_idx) {\n+\t\tPRINT_ERR(\"Error with rte_dmadev_completed for failure test. Got returned %u not %u.\\n\",\n+\t\t\t\tcount, fail_idx);\n+\t\trte_dmadev_dump(dev_id, stdout);\n+\t\treturn -1;\n+\t}\n+\tif (error == false) {\n+\t\tPRINT_ERR(\"Error, missing expected failed copy, %u. has_error is not set\\n\",\n+\t\t\t\tfail_idx);\n+\t\treturn -1;\n+\t}\n+\tif (idx != invalid_addr_id - 1) {\n+\t\tPRINT_ERR(\"Error, missing expected failed copy, %u. Got last idx %u, not %u\\n\",\n+\t\t\t\tfail_idx, idx, invalid_addr_id - 1);\n+\t\treturn -1;\n+\t}\n+\n+\t/* all checks ok, now verify calling completed() again always returns 0 */\n+\tfor (i = 0; i < 10; i++) {\n+\t\tif (rte_dmadev_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error) != 0\n+\t\t\t\t|| error == false || idx != (invalid_addr_id - 1)) {\n+\t\t\tPRINT_ERR(\"Error with follow-up completed calls for fail idx %u\\n\",\n+\t\t\t\t\tfail_idx);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\tstatus_count = rte_dmadev_completed_status(dev_id, vchan, COMP_BURST_SZ,\n+\t\t\t&idx, status);\n+\t/* some HW may stop on error and be restarted after getting error status for single value\n+\t * To handle this case, if we get just one error back, wait for more completions and get\n+\t * status for rest of the burst\n+\t */\n+\tif (status_count == 1) {\n+\t\tawait_hw(dev_id, vchan);\n+\t\tstatus_count += rte_dmadev_completed_status(dev_id, vchan, COMP_BURST_SZ - 1,\n+\t\t\t\t\t&idx, &status[1]);\n+\t}\n+\t/* check that at this point we have all status values */\n+\tif (status_count != COMP_BURST_SZ - count) {\n+\t\tPRINT_ERR(\"Error with completed_status calls for fail idx %u. Got %u not %u\\n\",\n+\t\t\t\tfail_idx, status_count, COMP_BURST_SZ - count);\n+\t\treturn -1;\n+\t}\n+\t/* now verify just one failure followed by multiple successful or skipped entries */\n+\tif (status[0] == RTE_DMA_STATUS_SUCCESSFUL) {\n+\t\tPRINT_ERR(\"Error with status returned for fail idx %u. First status was not failure\\n\",\n+\t\t\t\tfail_idx);\n+\t\treturn -1;\n+\t}\n+\tfor (i = 1; i < status_count; i++) {\n+\t\t/* after a failure in a burst, depending on ordering/fencing,\n+\t\t * operations may be successful or skipped because of previous error.\n+\t\t */\n+\t\tif (status[i] != RTE_DMA_STATUS_SUCCESSFUL\n+\t\t\t\t&& status[i] != RTE_DMA_STATUS_NOT_ATTEMPTED) {\n+\t\t\tPRINT_ERR(\"Error with status calls for fail idx %u. Status for job %u (of %u) is not successful\\n\",\n+\t\t\t\t\tfail_idx, count + i, COMP_BURST_SZ);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\t/* check the completed + errors stats are as expected */\n+\trte_dmadev_stats_get(dev_id, vchan, &stats);\n+\tif (stats.completed != baseline.completed + COMP_BURST_SZ) {\n+\t\tPRINT_ERR(\"Completed stats value not as expected, %\"PRIu64\" not %\"PRIu64\"\\n\",\n+\t\t\t\tstats.completed, baseline.completed + COMP_BURST_SZ);\n+\t\treturn -1;\n+\t}\n+\tfor (i = 0; i < status_count; i++)\n+\t\terr_count += (status[i] != RTE_DMA_STATUS_SUCCESSFUL);\n+\tif (stats.errors != baseline.errors + err_count) {\n+\t\tPRINT_ERR(\"'Errors' stats value not as expected, %\"PRIu64\" not %\"PRIu64\"\\n\",\n+\t\t\t\tstats.errors, baseline.errors + err_count);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+test_individual_status_query_with_failure(int dev_id, uint16_t vchan, bool fence,\n+\t\tstruct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx)\n+{\n+\t/* Test gathering batch statuses one at a time */\n+\tenum rte_dma_status_code status[COMP_BURST_SZ];\n+\tuint16_t invalid_addr_id = 0;\n+\tuint16_t idx;\n+\tuint16_t count = 0, status_count = 0;\n+\tunsigned int j;\n+\tbool error = false;\n+\n+\tfor (j = 0; j < COMP_BURST_SZ; j++) {\n+\t\tint id = rte_dmadev_copy(dev_id, vchan,\n+\t\t\t\t(j == fail_idx ? 0 : (srcs[j]->buf_iova + srcs[j]->data_off)),\n+\t\t\t\tdsts[j]->buf_iova + dsts[j]->data_off,\n+\t\t\t\tCOPY_LEN, OPT_FENCE(j));\n+\t\tif (id < 0) {\n+\t\t\tPRINT_ERR(\"Error with rte_dmadev_copy for buffer %u\\n\", j);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif (j == fail_idx)\n+\t\t\tinvalid_addr_id = id;\n+\t}\n+\trte_dmadev_submit(dev_id, vchan);\n+\tawait_hw(dev_id, vchan);\n+\n+\t/* use regular \"completed\" until we hit error */\n+\twhile (!error) {\n+\t\tuint16_t n = rte_dmadev_completed(dev_id, vchan, 1, &idx, &error);\n+\t\tcount += n;\n+\t\tif (n > 1 || count >= COMP_BURST_SZ) {\n+\t\t\tPRINT_ERR(\"Error - too many completions got\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif (n == 0 && !error) {\n+\t\t\tPRINT_ERR(\"Error, unexpectedly got zero completions after %u completed\\n\",\n+\t\t\t\t\tcount);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\tif (idx != invalid_addr_id - 1) {\n+\t\tPRINT_ERR(\"Error, last successful index not as expected, got %u, expected %u\\n\",\n+\t\t\t\tidx, invalid_addr_id - 1);\n+\t\treturn -1;\n+\t}\n+\n+\t/* use completed_status until we hit end of burst */\n+\twhile (count + status_count < COMP_BURST_SZ) {\n+\t\tuint16_t n = rte_dmadev_completed_status(dev_id, vchan, 1, &idx,\n+\t\t\t\t&status[status_count]);\n+\t\tawait_hw(dev_id, vchan); /* allow delay to ensure jobs are completed */\n+\t\tstatus_count += n;\n+\t\tif (n != 1) {\n+\t\t\tPRINT_ERR(\"Error: unexpected number of completions received, %u, not 1\\n\",\n+\t\t\t\t\tn);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\t/* check for single failure */\n+\tif (status[0] == RTE_DMA_STATUS_SUCCESSFUL) {\n+\t\tPRINT_ERR(\"Error, unexpected successful DMA transaction\\n\");\n+\t\treturn -1;\n+\t}\n+\tfor (j = 1; j < status_count; j++) {\n+\t\tif (status[j] != RTE_DMA_STATUS_SUCCESSFUL\n+\t\t\t\t&& status[j] != RTE_DMA_STATUS_NOT_ATTEMPTED) {\n+\t\t\tPRINT_ERR(\"Error, unexpected DMA error reported\\n\");\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+test_single_item_status_query_with_failure(int dev_id, uint16_t vchan,\n+\t\tstruct rte_mbuf **srcs, struct rte_mbuf **dsts, unsigned int fail_idx)\n+{\n+\t/* When error occurs just collect a single error using \"completed_status()\"\n+\t * before going to back to completed() calls\n+\t */\n+\tenum rte_dma_status_code status;\n+\tuint16_t invalid_addr_id = 0;\n+\tuint16_t idx;\n+\tuint16_t count, status_count, count2;\n+\tunsigned int j;\n+\tbool error = 0;\n+\n+\tfor (j = 0; j < COMP_BURST_SZ; j++) {\n+\t\tint id = rte_dmadev_copy(dev_id, vchan,\n+\t\t\t\t(j == fail_idx ? 0 : (srcs[j]->buf_iova + srcs[j]->data_off)),\n+\t\t\t\tdsts[j]->buf_iova + dsts[j]->data_off,\n+\t\t\t\tCOPY_LEN, 0);\n+\t\tif (id < 0) {\n+\t\t\tPRINT_ERR(\"Error with rte_dmadev_copy for buffer %u\\n\", j);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tif (j == fail_idx)\n+\t\t\tinvalid_addr_id = id;\n+\t}\n+\trte_dmadev_submit(dev_id, vchan);\n+\tawait_hw(dev_id, vchan);\n+\n+\t/* get up to the error point */\n+\tcount = rte_dmadev_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error);\n+\tif (count != fail_idx) {\n+\t\tPRINT_ERR(\"Error with rte_dmadev_completed for failure test. Got returned %u not %u.\\n\",\n+\t\t\t\tcount, fail_idx);\n+\t\trte_dmadev_dump(dev_id, stdout);\n+\t\treturn -1;\n+\t}\n+\tif (error == false) {\n+\t\tPRINT_ERR(\"Error, missing expected failed copy, %u. has_error is not set\\n\",\n+\t\t\t\tfail_idx);\n+\t\treturn -1;\n+\t}\n+\tif (idx != invalid_addr_id - 1) {\n+\t\tPRINT_ERR(\"Error, missing expected failed copy, %u. Got last idx %u, not %u\\n\",\n+\t\t\t\tfail_idx, idx, invalid_addr_id - 1);\n+\t\treturn -1;\n+\t}\n+\n+\t/* get the error code */\n+\tstatus_count = rte_dmadev_completed_status(dev_id, vchan, 1, &idx, &status);\n+\tif (status_count != 1) {\n+\t\tPRINT_ERR(\"Error with completed_status calls for fail idx %u. Got %u not %u\\n\",\n+\t\t\t\tfail_idx, status_count, COMP_BURST_SZ - count);\n+\t\treturn -1;\n+\t}\n+\tif (status == RTE_DMA_STATUS_SUCCESSFUL) {\n+\t\tPRINT_ERR(\"Error with status returned for fail idx %u. First status was not failure\\n\",\n+\t\t\t\tfail_idx);\n+\t\treturn -1;\n+\t}\n+\t/* delay in case time needed after err handled to complete other jobs */\n+\tawait_hw(dev_id, vchan);\n+\n+\t/* get the rest of the completions without status */\n+\tcount2 = rte_dmadev_completed(dev_id, vchan, COMP_BURST_SZ, &idx, &error);\n+\tif (error == true) {\n+\t\tPRINT_ERR(\"Error, got further errors post completed_status() call, for failure case %u.\\n\",\n+\t\t\t\tfail_idx);\n+\t\treturn -1;\n+\t}\n+\tif (count + status_count + count2 != COMP_BURST_SZ) {\n+\t\tPRINT_ERR(\"Error, incorrect number of completions received, got %u not %u\\n\",\n+\t\t\t\tcount + status_count + count2, COMP_BURST_SZ);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+test_multi_failure(int dev_id, uint16_t vchan, struct rte_mbuf **srcs, struct rte_mbuf **dsts,\n+\t\tconst unsigned int *fail, size_t num_fail)\n+{\n+\t/* test having multiple errors in one go */\n+\tenum rte_dma_status_code status[COMP_BURST_SZ];\n+\tunsigned int i, j;\n+\tuint16_t count, err_count = 0;\n+\tbool error = 0;\n+\n+\t/* enqueue and gather completions in one go */\n+\tfor (j = 0; j < COMP_BURST_SZ; j++) {\n+\t\tuintptr_t src = srcs[j]->buf_iova + srcs[j]->data_off;\n+\t\t/* set up for failure if the current index is anywhere is the fails array */\n+\t\tfor (i = 0; i < num_fail; i++)\n+\t\t\tif (j == fail[i])\n+\t\t\t\tsrc = 0;\n+\n+\t\tint id = rte_dmadev_copy(dev_id, vchan,\n+\t\t\t\tsrc, dsts[j]->buf_iova + dsts[j]->data_off,\n+\t\t\t\tCOPY_LEN, 0);\n+\t\tif (id < 0) {\n+\t\t\tPRINT_ERR(\"Error with rte_dmadev_copy for buffer %u\\n\", j);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\trte_dmadev_submit(dev_id, vchan);\n+\tawait_hw(dev_id, vchan);\n+\n+\tcount = rte_dmadev_completed_status(dev_id, vchan, COMP_BURST_SZ, NULL, status);\n+\twhile (count < COMP_BURST_SZ) {\n+\t\tawait_hw(dev_id, vchan);\n+\n+\t\tuint16_t ret = rte_dmadev_completed_status(dev_id, vchan, COMP_BURST_SZ - count,\n+\t\t\t\tNULL, &status[count]);\n+\t\tif (ret == 0) {\n+\t\t\tPRINT_ERR(\"Error getting all completions for jobs. Got %u of %u\\n\",\n+\t\t\t\t\tcount, COMP_BURST_SZ);\n+\t\t\treturn -1;\n+\t\t}\n+\t\tcount += ret;\n+\t}\n+\tfor (i = 0; i < count; i++) {\n+\t\tif (status[i] != RTE_DMA_STATUS_SUCCESSFUL)\n+\t\t\terr_count++;\n+\t}\n+\tif (err_count != num_fail) {\n+\t\tPRINT_ERR(\"Error: Invalid number of failed completions returned, %u; expected %zu\\n\",\n+\t\t\terr_count, num_fail);\n+\t\treturn -1;\n+\t}\n+\n+\t/* enqueue and gather completions in bursts, but getting errors one at a time */\n+\tfor (j = 0; j < COMP_BURST_SZ; j++) {\n+\t\tuintptr_t src = srcs[j]->buf_iova + srcs[j]->data_off;\n+\t\t/* set up for failure if the current index is anywhere is the fails array */\n+\t\tfor (i = 0; i < num_fail; i++)\n+\t\t\tif (j == fail[i])\n+\t\t\t\tsrc = 0;\n+\n+\t\tint id = rte_dmadev_copy(dev_id, vchan,\n+\t\t\t\tsrc, dsts[j]->buf_iova + dsts[j]->data_off,\n+\t\t\t\tCOPY_LEN, 0);\n+\t\tif (id < 0) {\n+\t\t\tPRINT_ERR(\"Error with rte_dmadev_copy for buffer %u\\n\", j);\n+\t\t\treturn -1;\n+\t\t}\n+\t}\n+\trte_dmadev_submit(dev_id, vchan);\n+\tawait_hw(dev_id, vchan);\n+\n+\tcount = 0;\n+\terr_count = 0;\n+\twhile (count + err_count < COMP_BURST_SZ) {\n+\t\tcount += rte_dmadev_completed(dev_id, vchan, COMP_BURST_SZ, NULL, &error);\n+\t\tif (error) {\n+\t\t\tuint16_t ret = rte_dmadev_completed_status(dev_id, vchan, 1,\n+\t\t\t\t\tNULL, status);\n+\t\t\tif (ret != 1) {\n+\t\t\t\tPRINT_ERR(\"Error getting error-status for completions\\n\");\n+\t\t\t\treturn -1;\n+\t\t\t}\n+\t\t\terr_count += ret;\n+\t\t\tawait_hw(dev_id, vchan);\n+\t\t}\n+\t}\n+\tif (err_count != num_fail) {\n+\t\tPRINT_ERR(\"Error: Incorrect number of failed completions received, got %u not %zu\\n\",\n+\t\t\t\terr_count, num_fail);\n+\t\treturn -1;\n+\t}\n+\n+\treturn 0;\n+}\n+\n+static int\n+test_completion_status(int dev_id, uint16_t vchan, bool fence)\n+{\n+\tconst unsigned int fail[] = {0, 7, 14, 15};\n+\tstruct rte_mbuf *srcs[COMP_BURST_SZ], *dsts[COMP_BURST_SZ];\n+\tunsigned int i;\n+\n+\tfor (i = 0; i < COMP_BURST_SZ; i++) {\n+\t\tsrcs[i] = rte_pktmbuf_alloc(pool);\n+\t\tdsts[i] = rte_pktmbuf_alloc(pool);\n+\t}\n+\n+\tfor (i = 0; i < RTE_DIM(fail); i++) {\n+\t\tif (test_failure_in_full_burst(dev_id, vchan, fence, srcs, dsts, fail[i]) < 0)\n+\t\t\treturn -1;\n+\n+\t\tif (test_individual_status_query_with_failure(dev_id, vchan, fence,\n+\t\t\t\tsrcs, dsts, fail[i]) < 0)\n+\t\t\treturn -1;\n+\n+\t\t/* test is run the same fenced, or unfenced, but no harm in running it twice */\n+\t\tif (test_single_item_status_query_with_failure(dev_id, vchan,\n+\t\t\t\tsrcs, dsts, fail[i]) < 0)\n+\t\t\treturn -1;\n+\t}\n+\n+\tif (test_multi_failure(dev_id, vchan, srcs, dsts, fail, RTE_DIM(fail)) < 0)\n+\t\treturn -1;\n+\n+\tfor (i = 0; i < COMP_BURST_SZ; i++) {\n+\t\trte_pktmbuf_free(srcs[i]);\n+\t\trte_pktmbuf_free(dsts[i]);\n+\t}\n+\treturn 0;\n+}\n+\n static int\n test_dmadev_instance(uint16_t dev_id)\n {\n@@ -386,6 +794,25 @@ test_dmadev_instance(uint16_t dev_id)\n \tif (check_stats(&stats, true) < 0)\n \t\tgoto err;\n \n+\t/* to test error handling we can provide null pointers for source or dest in copies. This\n+\t * requires VA mode in DPDK, since NULL(0) is a valid physical address.\n+\t */\n+\tif (rte_eal_iova_mode() == RTE_IOVA_VA) {\n+\t\trte_dmadev_stats_reset(dev_id, vchan);\n+\t\tprintf(\"DMA Dev: %u, Running Completion Handling Tests (errors expected)\\n\",\n+\t\t\t\tdev_id);\n+\t\tif (test_completion_status(dev_id, vchan, false) != 0) /* without fences */\n+\t\t\tgoto err;\n+\t\tif (test_completion_status(dev_id, vchan, true) != 0) /* with fences */\n+\t\t\tgoto err;\n+\t\trte_dmadev_stats_get(dev_id, 0, &stats);\n+\t\tprintf(\"Ops submitted: %\"PRIu64\"\\t\", stats.submitted);\n+\t\tprintf(\"Ops completed: %\"PRIu64\"\\t\", stats.completed);\n+\t\tprintf(\"Errors: %\"PRIu64\"\\n\", stats.errors);\n+\t\tif (check_stats(&stats, false) < 0) /* don't check stats.errors this time */\n+\t\t\tgoto err;\n+\t}\n+\n \trte_mempool_free(pool);\n \trte_dmadev_stop(dev_id);\n \trte_dmadev_stats_reset(dev_id, vchan);\n", "prefixes": [ "v2", "5/6" ] }