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GET /api/patches/97302/?format=api
{ "id": 97302, "url": "https://patches.dpdk.org/api/patches/97302/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210825071510.7913-10-hemant.agrawal@nxp.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210825071510.7913-10-hemant.agrawal@nxp.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210825071510.7913-10-hemant.agrawal@nxp.com", "date": "2021-08-25T07:15:04", "name": "[09/15] crypto/dpaa2_sec: support OOP with raw buffer API", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "ccba3f00de6ea4a4f10250133c9ea5c487744578", "submitter": { "id": 477, "url": "https://patches.dpdk.org/api/people/477/?format=api", "name": "Hemant Agrawal", "email": "hemant.agrawal@nxp.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210825071510.7913-10-hemant.agrawal@nxp.com/mbox/", "series": [ { "id": 18444, "url": "https://patches.dpdk.org/api/series/18444/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=18444", "date": "2021-08-25T07:14:55", "name": "crypto: add raw vector support in DPAAx", "version": 1, "mbox": "https://patches.dpdk.org/series/18444/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/97302/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/97302/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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b=Hed8d8DiTF4dIwe4B8oPK+2ilE4PxynnwRYLRUGAdMVHB1Sx8S4k/Iit6u/nxbYc3lmc110hpoCw5aO29F25qEzk9Llp+yVxIPd7wkQT3hFLApD7SErFVOMhs7A5nb+TAcaO51Jl6Sq8PUB1ve9cQU/irwDtgcpiSIa3iI6hErc=", "Authentication-Results": "dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=none action=none header.from=nxp.com;", "From": "Hemant Agrawal <hemant.agrawal@nxp.com>", "To": "dev@dpdk.org,\n\tgakhil@marvell.com", "Cc": "konstantin.ananyev@intel.com, roy.fan.zhang@intel.com,\n Gagandeep Singh <g.singh@nxp.com>", "Date": "Wed, 25 Aug 2021 12:45:04 +0530", "Message-Id": "<20210825071510.7913-10-hemant.agrawal@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20210825071510.7913-1-hemant.agrawal@nxp.com>", "References": "<20210812071244.28799-1-hemant.agrawal@nxp.com>\n <20210825071510.7913-1-hemant.agrawal@nxp.com>", "Content-Type": "text/plain", "X-ClientProxiedBy": "SG2PR01CA0126.apcprd01.prod.exchangelabs.com\n (2603:1096:4:40::30) To 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fdbqBQh6dtJ28j5tD8Q9LslzHHH+HtIb6BxDWky5yXuaBsbfZSSK3EfhpkkPVSikbWAXhJfYC4LWRulo8oVo5Tk7K5HndAtdvwFC6AcWdwSOCBA6x8EKd5PL/rQiXVURrzrftwy5o9b4Jp+zSuN7NDqJYRPwWHxxKUUA/PwnkRq/lucVDx/6992YDcCpN0BPMurr0ZgSX55IQ1z5wcGnJct5lecIQj5UwWVBD18syAJKC4V0UaiM6XDKFyyOJxY8r64acT29akSJL0ge3kt/4TCcO0ovl5p4St5oSej5cq9DUEyFiYeN2i0XKO9e7I99u/xQ/FUPQrMqHXvCRnNMqmquSnaY682ONBycLVxl5iNBKOJIMeImDVcbNoOiO6ZBTtNDwZ67GWd3aqcLrDw3Y4pykO2gDMrNnOvCtY8qNyVvY+KTSZyUrhy4I2ry3uHqmJES9PwEFtjtnYpKo36lMlsy6F0zogIOP1fYw5Nb1J9GXu/1XUpGECM+JOGSp6ApgS4hhZUevtAdVWKO0BQ315Jc8jljxCftV8p22i8lnXt4ystgBvZxHOGJpGrsv3/IlIBCxLK+BvobPq6rQ+C7hMQlWhjNvCLajpzbBaFIfWeMNLqdbYvLGmpfadgCvVT8VW1uKUdlaTHsQLWg9axuZhy1+nI9AuDKMCbsVBCfC/rgowCG9PY6ySy6b8cDZNNdzUf/L7Dyow/3SYM2XLUG33LpPF0aHfzmYmNTOT4bxmjPqkRx1e1n1ExhK+TonLwIVuuKn3omKqBwhD1ZnlS/uwlTyRFbFWBIPCRBVo666Vgk8lgjUYi3fyytOqJEyH64u0cy5XB1TFl5/xmjlG5aVzLa1LWEg8GP26e23ZQ5cRo/+1verPBt2QMXAiD0qdaBaMDHcLLO1w6T5uCRvgIrz8OvGNl1l/cVhTVYbXyKum9AdZbiJent3SxMfxAkOhneoVcRzJogT49OCPZpjBLqwUOpByToerzbqeefEXXjRHjNiSbgVtgOi80FgEYWK0eApAo4/Bcb966sUG/+aqoc15ijA3U8W+Ml0htT+9Iz0Yy/ZjtdNzhmHTvk7dPy3TlUkMeFAFFFY9xkH1zrejdiJqAlRjr+mWBAgBfr5iGUA+XtBfadHEe0UOdFZA5jaGnS1DDAE/Mvd1XldZwV//7dxksszXZV4cwXxSloymkbCJeN0lOtFeuGN5omEgg/5ZJJ1VZPPyVLF1WpXgwoyNaL/TguSQped7XrBfzN2/7+qpdm6v/M6YHcbWgI3GpRu9CD+511NaElW4InbpKIKwZtjcuBjRlHv/7bXXWEmpoGIWW6s79YuvjCWgNj5SwbqAOc", "X-OriginatorOrg": "nxp.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 21822a69-a9c4-4f07-e4b0-08d967989f2e", "X-MS-Exchange-CrossTenant-AuthSource": "DU2PR04MB8630.eurprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "25 Aug 2021 07:19:05.4942 (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "686ea1d3-bc2b-4c6f-a92c-d99c5c301635", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n uJeqajb8h6qWEiC6p3X8kpCjZ0Ar7WJKKmvSgitMWPlTyUv33omenXbFPLxHxTJoWgVXOYlBKm0LDiVOpUh5IQ==", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DU2PR04MB8614", "Subject": "[dpdk-dev] [PATCH 09/15] crypto/dpaa2_sec: support OOP with raw\n buffer API", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Gagandeep Singh <g.singh@nxp.com>\n\nadd support for out of order processing with raw vector APIs.\n\nSigned-off-by: Gagandeep Singh <g.singh@nxp.com>\n---\n drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h | 1 +\n drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c | 156 +++++++++++++++-----\n 2 files changed, 116 insertions(+), 41 deletions(-)", "diff": "diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\nindex f6507855e3..db72c11a5f 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_priv.h\n@@ -179,6 +179,7 @@ typedef int (*dpaa2_sec_build_fd_t)(\n \n typedef int (*dpaa2_sec_build_raw_dp_fd_t)(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\ndiff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\nindex 5191e5381c..51e316cc00 100644\n--- a/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\n+++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_raw_dp.c\n@@ -24,6 +24,7 @@ struct dpaa2_sec_raw_dp_ctx {\n static int\n build_raw_dp_chain_fd(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -89,17 +90,33 @@ build_raw_dp_chain_fd(uint8_t *drv_ctx,\n \t\t\t(cipher_len + icv_len) :\n \t\t\tcipher_len;\n \n-\t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.auth.head);\n-\tsge->length = sgl->vec[0].len - ofs.ofs.auth.head;\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = dest_sgl->vec[0].len - ofs.ofs.cipher.head;\n \n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n+\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t}\n \t}\n \n \tif (sess->dir == DIR_ENC) {\n@@ -160,6 +177,7 @@ build_raw_dp_chain_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_aead_fd(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -219,17 +237,33 @@ build_raw_dp_aead_fd(uint8_t *drv_ctx,\n \t\t\t(aead_len + icv_len) :\n \t\t\taead_len;\n \n-\t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n-\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = dest_sgl->vec[0].len - ofs.ofs.cipher.head;\n \n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, ofs.ofs.cipher.head);\n+\t\tsge->length = sgl->vec[0].len - ofs.ofs.cipher.head;\n+\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t}\n \t}\n \n \tif (sess->dir == DIR_ENC) {\n@@ -294,6 +328,7 @@ build_raw_dp_aead_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_auth_fd(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -303,6 +338,7 @@ build_raw_dp_auth_fd(uint8_t *drv_ctx,\n {\n \tRTE_SET_USED(iv);\n \tRTE_SET_USED(auth_iv);\n+\tRTE_SET_USED(dest_sgl);\n \n \tdpaa2_sec_session *sess =\n \t\t((struct dpaa2_sec_raw_dp_ctx *)drv_ctx)->session;\n@@ -416,6 +452,7 @@ build_raw_dp_auth_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_proto_fd(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -466,20 +503,39 @@ build_raw_dp_proto_fd(uint8_t *drv_ctx,\n \tDPAA2_SET_FLE_SG_EXT(op_fle);\n \tDPAA2_SET_FLE_ADDR(op_fle, DPAA2_VADDR_TO_IOVA(sge));\n \n-\t/* Configure Output SGE for Encap/Decap */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\tsge->length = sgl->vec[0].len;\n-\tout_len += sge->length;\n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n \t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\tsge->length = dest_sgl->vec[0].len;\n+\t\tout_len += sge->length;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t\tout_len += sge->length;\n+\t\t}\n+\t\tsge->length = dest_sgl->vec[i - 1].tot_len;\n+\n+\t} else {\n+\t\t/* Configure Output SGE for Encap/Decap */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\tsge->length = sgl->vec[0].len;\n \t\tout_len += sge->length;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t\tout_len += sge->length;\n+\t\t}\n+\t\tsge->length = sgl->vec[i - 1].tot_len;\n \t}\n-\tsge->length = sgl->vec[i - 1].tot_len;\n \tout_len += sge->length;\n \n \tDPAA2_SET_FLE_FIN(sge);\n@@ -528,6 +584,7 @@ build_raw_dp_proto_fd(uint8_t *drv_ctx,\n static int\n build_raw_dp_cipher_fd(uint8_t *drv_ctx,\n \t\t struct rte_crypto_sgl *sgl,\n+\t\t struct rte_crypto_sgl *dest_sgl,\n \t\t struct rte_crypto_va_iova_ptr *iv,\n \t\t struct rte_crypto_va_iova_ptr *digest,\n \t\t struct rte_crypto_va_iova_ptr *auth_iv,\n@@ -593,17 +650,33 @@ build_raw_dp_cipher_fd(uint8_t *drv_ctx,\n \top_fle->length = data_len;\n \tDPAA2_SET_FLE_SG_EXT(op_fle);\n \n-\t/* o/p 1st seg */\n-\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n-\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n-\tsge->length = sgl->vec[0].len - data_offset;\n+\t/* OOP */\n+\tif (dest_sgl) {\n+\t\t/* o/p 1st seg */\n+\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\t\tsge->length = dest_sgl->vec[0].len - data_offset;\n \n-\t/* o/p segs */\n-\tfor (i = 1; i < sgl->num; i++) {\n-\t\tsge++;\n-\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n-\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n-\t\tsge->length = sgl->vec[i].len;\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < dest_sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, dest_sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = dest_sgl->vec[i].len;\n+\t\t}\n+\t} else {\n+\t\t/* o/p 1st seg */\n+\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[0].iova);\n+\t\tDPAA2_SET_FLE_OFFSET(sge, data_offset);\n+\t\tsge->length = sgl->vec[0].len - data_offset;\n+\n+\t\t/* o/p segs */\n+\t\tfor (i = 1; i < sgl->num; i++) {\n+\t\t\tsge++;\n+\t\t\tDPAA2_SET_FLE_ADDR(sge, sgl->vec[i].iova);\n+\t\t\tDPAA2_SET_FLE_OFFSET(sge, 0);\n+\t\t\tsge->length = sgl->vec[i].len;\n+\t\t}\n \t}\n \tDPAA2_SET_FLE_FIN(sge);\n \n@@ -706,6 +779,7 @@ dpaa2_sec_raw_enqueue_burst(void *qp_data, uint8_t *drv_ctx,\n \t\t\tmemset(&fd_arr[loop], 0, sizeof(struct qbman_fd));\n \t\t\tret = sess->build_raw_dp_fd(drv_ctx,\n \t\t\t\t\t\t &vec->src_sgl[loop],\n+\t\t\t\t\t\t &vec->dest_sgl[loop],\n \t\t\t\t\t\t &vec->iv[loop],\n \t\t\t\t\t\t &vec->digest[loop],\n \t\t\t\t\t\t &vec->auth_iv[loop],\n", "prefixes": [ "09/15" ] }