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GET /api/patches/96169/?format=api
{ "id": 96169, "url": "https://patches.dpdk.org/api/patches/96169/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210721143743.24626-14-xuemingl@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210721143743.24626-14-xuemingl@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210721143743.24626-14-xuemingl@nvidia.com", "date": "2021-07-21T14:37:40", "name": "[v4,13/16] vdpa/mlx5: support SubFunction", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "171c663ed76bdb08eb90a5f5f9a81aa1d0ba97ae", "submitter": { "id": 1904, "url": "https://patches.dpdk.org/api/people/1904/?format=api", "name": "Xueming Li", "email": "xuemingl@nvidia.com" }, "delegate": { "id": 1, "url": "https://patches.dpdk.org/api/users/1/?format=api", "username": "tmonjalo", "first_name": "Thomas", "last_name": "Monjalon", "email": "thomas@monjalon.net" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210721143743.24626-14-xuemingl@nvidia.com/mbox/", "series": [ { "id": 17938, "url": "https://patches.dpdk.org/api/series/17938/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17938", "date": "2021-07-21T14:37:27", "name": "net/mlx5: support Sub-Function", "version": 4, "mbox": "https://patches.dpdk.org/series/17938/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/96169/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/96169/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 4BA92A0C52;\n\tWed, 21 Jul 2021 16:40:02 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 81E0E41153;\n\tWed, 21 Jul 2021 16:39:36 +0200 (CEST)", "from NAM04-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam08on2077.outbound.protection.outlook.com [40.107.100.77])\n by mails.dpdk.org (Postfix) with ESMTP id 26A5F41120\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Xueming Li <xuemingl@nvidia.com>", "To": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "CC": "Thomas Monjalon <thomas@monjalon.net>, <dev@dpdk.org>,\n <xuemingl@nvidia.com>, Matan Azrad <matan@nvidia.com>", "Date": "Wed, 21 Jul 2021 22:37:40 +0800", "Message-ID": "<20210721143743.24626-14-xuemingl@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210721143743.24626-1-xuemingl@nvidia.com>", "References": "<20210616040935.311733-1-xuemingl@nvidia.com>\n <20210721143743.24626-1-xuemingl@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "40960335-de23-4202-78ed-08d94c555b65", "X-MS-TrafficTypeDiagnostic": "DM5PR1201MB0090:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <DM5PR1201MB00905D510EF3E677DBD0D2F3A1E39@DM5PR1201MB0090.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:565;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n Z1IgaKrYRdGn2ZhHlh2ie+NUUyzdmzc0HJ43DRADVoUIXu2PrwpuHJW9ut4rDPiwx/uqxMUQ2ywTg004PA/hN2Rym+twi1HSwqNQ2xkfysTkIGwowDpDdQbL1iPeGqdTbcAF4E5bCbcICIUUH+IImFdO7kIkABqnD4RhjWy5noWyJ6HJ4rAwewAX+j1Br/Z2YCiRtMb6JZJMAE8eXfp4gojSApAtASWjKr5C0rUQ7TiejpRfrqsxAGggMGDvIiRI3Uan1Ze2CB8qBs9HL4PsM7X4KwbFHbkFaQBEJObVHeHw/lR1DcAijMmeq3xFHlYStHlMZN1uH7papCYgOIEBtckj52M7qiZlAI3bMb8ZAQMsXL9yG6+iYf9B5ZuPbU+nFpzK0inVV6yRHlCBnxB+jO8kqDgY121DdTwonCoZYZ7FLL491AUm/6CKaGtpj7A0JsJQNdkUA7bIuiQ3q+58EmGTMxqS3t1x3+u1YZW+gENoulwNrz19OUVjLydjnfB74wNlDJktbdz6wW3dPXiDSrNkIsFu3Hxop1JmvrOfYDbo+gEqGJ3QKrG/llwBPRJe7OlVAJP/C3scyPy7EEWaRwdvcIXaNLfzXQJa7dX5ak+rEWVH/iQs5/3q7fXEdrkoJegdz2ZvJqgnZS/w89+yFhM+Qzr9NHsem69Np0FGTgM4LSoTV2UBI+/58DZ4SEeAMOu1NrCZs2EFMDWj/R+Bog==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(46966006)(36840700001)(2616005)(6666004)(86362001)(16526019)(336012)(426003)(70206006)(186003)(54906003)(70586007)(508600001)(8936002)(8676002)(7636003)(356005)(36756003)(6286002)(36860700001)(36906005)(55016002)(26005)(83380400001)(2906002)(316002)(7696005)(47076005)(107886003)(6862004)(4326008)(5660300002)(6636002)(1076003)(82310400003)(37006003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "21 Jul 2021 14:39:33.7424 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 40960335-de23-4202-78ed-08d94c555b65", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT060.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DM5PR1201MB0090", "Subject": "[dpdk-dev] [PATCH v4 13/16] vdpa/mlx5: support SubFunction", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "From: Thomas Monjalon <thomas@monjalon.net>\n\nSupports SubFunction on auxiliary bus. SF probe devargs:\n auxiliary:mlx5_core.sf.<id>,class=vdpa\n\nSigned-off-by: Thomas Monjalon <thomas@monjalon.net>\nAcked-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\n---\n doc/guides/vdpadevs/mlx5.rst | 10 ++++++++++\n drivers/vdpa/mlx5/mlx5_vdpa.c | 8 ++++++--\n 2 files changed, 16 insertions(+), 2 deletions(-)", "diff": "diff --git a/doc/guides/vdpadevs/mlx5.rst b/doc/guides/vdpadevs/mlx5.rst\nindex 9b2f9f12c7..e81dbd0004 100644\n--- a/doc/guides/vdpadevs/mlx5.rst\n+++ b/doc/guides/vdpadevs/mlx5.rst\n@@ -162,6 +162,16 @@ Driver options\n \n - 0, HW default.\n \n+Devargs example\n+^^^^^^^^^^^^^^^\n+\n+- PCI devargs:\n+\n+ -a 0000:03:00.2,class=vdpa\n+\n+- Auxiliary devargs:\n+\n+ -a auxiliary:mlx5_core.sf.2,class=vdpa\n \n Error handling\n ^^^^^^^^^^^^^^\ndiff --git a/drivers/vdpa/mlx5/mlx5_vdpa.c b/drivers/vdpa/mlx5/mlx5_vdpa.c\nindex 9c9a552ba0..6d17d7a6f3 100644\n--- a/drivers/vdpa/mlx5/mlx5_vdpa.c\n+++ b/drivers/vdpa/mlx5/mlx5_vdpa.c\n@@ -553,9 +553,13 @@ mlx5_vdpa_sys_roce_disable(const char *addr)\n static int\n mlx5_vdpa_roce_disable(struct rte_device *dev)\n {\n+\tchar pci_addr[PCI_PRI_STR_SIZE] = { 0 };\n+\n+\tif (mlx5_dev_to_pci_str(dev, pci_addr, sizeof(pci_addr)) < 0)\n+\t\treturn -rte_errno;\n \t/* Firstly try to disable ROCE by Netlink and fallback to sysfs. */\n-\tif (mlx5_vdpa_nl_roce_disable(dev->name) != 0 &&\n-\t mlx5_vdpa_sys_roce_disable(dev->name) != 0)\n+\tif (mlx5_vdpa_nl_roce_disable(pci_addr) != 0 &&\n+\t mlx5_vdpa_sys_roce_disable(pci_addr) != 0)\n \t\treturn -rte_errno;\n \treturn 0;\n }\n", "prefixes": [ "v4", "13/16" ] }