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GET /api/patches/95913/?format=api
{ "id": 95913, "url": "https://patches.dpdk.org/api/patches/95913/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210715164126.54073-8-shirik@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210715164126.54073-8-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210715164126.54073-8-shirik@nvidia.com", "date": "2021-07-15T16:41:17", "name": "[v8,07/16] crypto/mlx5: add memory region management", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "64b833f4de574f78e3a77352e40a56643c61d019", "submitter": { "id": 1894, "url": "https://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210715164126.54073-8-shirik@nvidia.com/mbox/", "series": [ { "id": 17843, "url": "https://patches.dpdk.org/api/series/17843/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17843", "date": "2021-07-15T16:41:10", "name": "drivers: introduce mlx5 crypto PMD", "version": 8, "mbox": "https://patches.dpdk.org/series/17843/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95913/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/95913/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 17633A0C41;\n\tThu, 15 Jul 2021 18:42:54 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 850224130B;\n\tThu, 15 Jul 2021 18:42:18 +0200 (CEST)", "from NAM11-CO1-obe.outbound.protection.outlook.com\n (mail-co1nam11on2069.outbound.protection.outlook.com [40.107.220.69])\n by mails.dpdk.org (Postfix) with ESMTP id 15064412DF\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>,\n <david.marchand@redhat.com>, Michael Baum <michaelba@nvidia.com>", "Date": "Thu, 15 Jul 2021 19:41:17 +0300", "Message-ID": "<20210715164126.54073-8-shirik@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210715164126.54073-1-shirik@nvidia.com>", "References": "<20210715150817.51485-1-shirik@nvidia.com>\n <20210715164126.54073-1-shirik@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL105.nvidia.com (172.20.187.12) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "773cea12-8a70-4f01-acf2-08d947af7f84", "X-MS-TrafficTypeDiagnostic": "MW2PR12MB2393:", "X-Microsoft-Antispam-PRVS": "\n <MW2PR12MB2393A2A615FE2DCC34360D52AA129@MW2PR12MB2393.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:785;", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n zduzfTNuxIHoq8m3pAKti2cJlrl5fpipwULge698RlZuN/S8SJgPzRXdM0VFrnjd06ZA7d4uE806QlGhGW2avxkwgy/g4mYgZ9cTwKhTFuJ+1/fcFs4UGPApvx9E3bjcnfSQgnOzIDeAiLUvv4n475ZWttyuxBTBIKOEARMkxfKbtdkUqlFbQ2QXCHwAdsa2t1MzRZ4mJWwiGlwhW8W4TIdc6yogThfOceD9fcQG7Zna59HuuJ66jqgvCkqem2GjPqRY+5nYxZ4KunEvc/OhY50fvDy2o6lqHG9e3CmDEMR5tPBpxaEzRdMTNK0OILEeD6eFK7T17cGzbgrXosnre7PtX1hAcx0uwOQhttFDfyp3PD0Lq4y9Vde8TC4I6DG6Q+SYcvuje6+SImXkC2rPFQl/fV2e3BZfQYAhHWGKbAba+Sn3sH9lMNU5FFj1Ioa8r3nt8EzuH56Mgn0ykk2mHJWVEvimXy3/AsDwpBqwlih425Qit7bHocSvMBQtGP4EWEgBOZ1qYEpr0fGk5N7kGXK3nUUiogoj0S7/6O1dsnaBRw21UaXD/lDNIsZpf++LQGCStjRpf+ISfHDfJ4tuR3YdXbGvnxbgUBgbd1wO6JV0w98tVeLRU1Wozow030EkInwd2DfHbdbBJ5dh9s0bBvxemvdtLJjGLPIekACpCkjoZpk3x57sD6j6QFHgmriCvaGsE8vTzVEIvPRaPGsEHdlBHjHB+c9mc2rrZOKZCvM=", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(396003)(39860400002)(376002)(136003)(36840700001)(46966006)(86362001)(426003)(2906002)(107886003)(26005)(36906005)(8936002)(34020700004)(36756003)(316002)(82310400003)(36860700001)(55016002)(7696005)(4326008)(54906003)(1076003)(478600001)(6286002)(82740400003)(336012)(8676002)(16526019)(70206006)(5660300002)(47076005)(2616005)(186003)(7636003)(70586007)(356005)(6916009)(83380400001);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "15 Jul 2021 16:42:13.2766 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 773cea12-8a70-4f01-acf2-08d947af7f84", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT010.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW2PR12MB2393", "Subject": "[dpdk-dev] [PATCH v8 07/16] crypto/mlx5: add memory region\n management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Mellanox user space drivers don't deal with physical addresses as part\nof a memory protection mechanism.\nThe device translates the given virtual address to a physical address\nusing the given memory key as an address space identifier.\nThat's why any mbuf virtual address is moved directly to the HW\ndescriptor(WQE).\n\nThe mapping between the virtual address to the physical address is saved\nin MR configured by the kernel to the HW.\n\nEach MR has a key that should also be moved to the WQE by the SW.\n\nWhen the SW sees an unmapped address, it extends the address range and\ncreates a MR using a system call.\n\nAdd memory region cache management:\n\t- 2 level cache per queue-pair - no locks.\n\t- 1 shared cache between all the queues using a lock.\n\nUsing this way, the MR key search per data-path address is optimized.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n doc/guides/cryptodevs/mlx5.rst | 6 +++\n drivers/crypto/mlx5/mlx5_crypto.c | 63 +++++++++++++++++++++++++++++++\n drivers/crypto/mlx5/mlx5_crypto.h | 3 ++\n 3 files changed, 72 insertions(+)", "diff": "diff --git a/doc/guides/cryptodevs/mlx5.rst b/doc/guides/cryptodevs/mlx5.rst\nindex dd1d1a615d..ece881220e 100644\n--- a/doc/guides/cryptodevs/mlx5.rst\n+++ b/doc/guides/cryptodevs/mlx5.rst\n@@ -26,6 +26,12 @@ the MKEY is configured to perform crypto operations.\n \n The encryption does not require text to be aligned to the AES block size (128b).\n \n+For security reasons and to increase robustness, this driver only deals with virtual\n+memory addresses. The way resources allocations are handled by the kernel,\n+combined with hardware specifications that allow handling virtual memory\n+addresses directly, ensure that DPDK applications cannot access random\n+physical memory (or memory that does not belong to the current process).\n+\n The PMD uses libibverbs and libmlx5 to access the device firmware or to\n access the hardware components directly.\n There are different levels of objects and bypassing abilities.\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex 37e66cf57b..38008dcb28 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -261,6 +261,7 @@ mlx5_crypto_queue_pair_release(struct rte_cryptodev *dev, uint16_t qp_id)\n \t\tclaim_zero(mlx5_glue->devx_umem_dereg(qp->umem_obj));\n \tif (qp->umem_buf != NULL)\n \t\trte_free(qp->umem_buf);\n+\tmlx5_mr_btree_free(&qp->mr_ctrl.cache_bh);\n \tmlx5_devx_cq_destroy(&qp->cq_obj);\n \trte_free(qp);\n \tdev->data->queue_pairs[qp_id] = NULL;\n@@ -342,6 +343,14 @@ mlx5_crypto_queue_pair_setup(struct rte_cryptodev *dev, uint16_t qp_id,\n \t\tDRV_LOG(ERR, \"Failed to register QP umem.\");\n \t\tgoto error;\n \t}\n+\tif (mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,\n+\t\t\t priv->dev_config.socket_id) != 0) {\n+\t\tDRV_LOG(ERR, \"Cannot allocate MR Btree for qp %u.\",\n+\t\t\t(uint32_t)qp_id);\n+\t\trte_errno = ENOMEM;\n+\t\tgoto error;\n+\t}\n+\tqp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;\n \tattr.pd = priv->pdn;\n \tattr.uar_index = mlx5_os_get_devx_uar_page_id(priv->uar);\n \tattr.cqn = qp->cq_obj.cq->id;\n@@ -448,6 +457,40 @@ mlx5_crypto_hw_global_prepare(struct mlx5_crypto_priv *priv)\n \treturn 0;\n }\n \n+/**\n+ * Callback for memory event.\n+ *\n+ * @param event_type\n+ * Memory event type.\n+ * @param addr\n+ * Address of memory.\n+ * @param len\n+ * Size of memory.\n+ */\n+static void\n+mlx5_crypto_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n+\t\t\t size_t len, void *arg __rte_unused)\n+{\n+\tstruct mlx5_crypto_priv *priv;\n+\n+\t/* Must be called from the primary process. */\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tswitch (event_type) {\n+\tcase RTE_MEM_EVENT_FREE:\n+\t\tpthread_mutex_lock(&priv_list_lock);\n+\t\t/* Iterate all the existing mlx5 devices. */\n+\t\tTAILQ_FOREACH(priv, &mlx5_crypto_priv_list, next)\n+\t\t\tmlx5_free_mr_by_addr(&priv->mr_scache,\n+\t\t\t\t\t priv->ctx->device->name,\n+\t\t\t\t\t addr, len);\n+\t\tpthread_mutex_unlock(&priv_list_lock);\n+\t\tbreak;\n+\tcase RTE_MEM_EVENT_ALLOC:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n /**\n * DPDK callback to register a PCI device.\n *\n@@ -530,6 +573,22 @@ mlx5_crypto_pci_probe(struct rte_pci_driver *pci_drv,\n \t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n \t\treturn -1;\n \t}\n+\tif (mlx5_mr_btree_init(&priv->mr_scache.cache,\n+\t\t\t MLX5_MR_BTREE_CACHE_N * 2, rte_socket_id()) != 0) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate shared cache MR memory.\");\n+\t\tmlx5_crypto_hw_global_release(priv);\n+\t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n+\t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\n+\t\trte_errno = ENOMEM;\n+\t\treturn -rte_errno;\n+\t}\n+\tpriv->mr_scache.reg_mr_cb = mlx5_common_verbs_reg_mr;\n+\tpriv->mr_scache.dereg_mr_cb = mlx5_common_verbs_dereg_mr;\n+\t/* Register callback function for global shared MR cache management. */\n+\tif (TAILQ_EMPTY(&mlx5_crypto_priv_list))\n+\t\trte_mem_event_callback_register(\"MLX5_MEM_EVENT_CB\",\n+\t\t\t\t\t\tmlx5_crypto_mr_mem_event_cb,\n+\t\t\t\t\t\tNULL);\n \tpthread_mutex_lock(&priv_list_lock);\n \tTAILQ_INSERT_TAIL(&mlx5_crypto_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\n@@ -549,6 +608,10 @@ mlx5_crypto_pci_remove(struct rte_pci_device *pdev)\n \t\tTAILQ_REMOVE(&mlx5_crypto_priv_list, priv, next);\n \tpthread_mutex_unlock(&priv_list_lock);\n \tif (priv) {\n+\t\tif (TAILQ_EMPTY(&mlx5_crypto_priv_list))\n+\t\t\trte_mem_event_callback_unregister(\"MLX5_MEM_EVENT_CB\",\n+\t\t\t\t\t\t\t NULL);\n+\t\tmlx5_mr_release_cache(&priv->mr_scache);\n \t\tmlx5_crypto_hw_global_release(priv);\n \t\trte_cryptodev_pmd_destroy(priv->crypto_dev);\n \t\tclaim_zero(mlx5_glue->close_device(priv->ctx));\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nindex 1c3c4855ec..a9fbc0aa82 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.h\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -12,6 +12,7 @@\n \n #include <mlx5_common_utils.h>\n #include <mlx5_common_devx.h>\n+#include <mlx5_common_mr.h>\n \n #define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)\n #define MLX5_CRYPTO_KEY_LENGTH 80\n@@ -27,6 +28,7 @@ struct mlx5_crypto_priv {\n \tstruct ibv_pd *pd;\n \tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n \tstruct rte_cryptodev_config dev_config;\n+\tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n };\n \n struct mlx5_crypto_qp {\n@@ -36,6 +38,7 @@ struct mlx5_crypto_qp {\n \tvoid *umem_buf;\n \tvolatile uint32_t *db_rec;\n \tstruct rte_crypto_op **ops;\n+\tstruct mlx5_mr_ctrl mr_ctrl;\n };\n \n struct mlx5_crypto_dek {\n", "prefixes": [ "v8", "07/16" ] }