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GET /api/patches/95511/?format=api
{ "id": 95511, "url": "https://patches.dpdk.org/api/patches/95511/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210707155428.13178-1-viacheslavo@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210707155428.13178-1-viacheslavo@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210707155428.13178-1-viacheslavo@nvidia.com", "date": "2021-07-07T15:54:27", "name": "[v4,1/2] common/mlx5: add provider query port support to glue library", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": true, "hash": "56a3bf56f08c1b0daf6335de827f456c85968a85", "submitter": { "id": 1926, "url": "https://patches.dpdk.org/api/people/1926/?format=api", "name": "Slava Ovsiienko", "email": "viacheslavo@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210707155428.13178-1-viacheslavo@nvidia.com/mbox/", "series": [ { "id": 17703, "url": "https://patches.dpdk.org/api/series/17703/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17703", "date": "2021-07-07T15:54:27", "name": "[v4,1/2] common/mlx5: add provider query port support to glue library", "version": 4, "mbox": "https://patches.dpdk.org/series/17703/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95511/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/95511/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 18A5CA0C4B;\n\tWed, 7 Jul 2021 17:54:51 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id F31B541564;\n\tWed, 7 Jul 2021 17:54:50 +0200 (CEST)", "from NAM04-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam08on2062.outbound.protection.outlook.com [40.107.102.62])\n by mails.dpdk.org (Postfix) with ESMTP id 7F9CB41563;\n Wed, 7 Jul 2021 17:54:49 +0200 (CEST)", "from MW4P221CA0006.NAMP221.PROD.OUTLOOK.COM (2603:10b6:303:8b::11)\n by BL1PR12MB5240.namprd12.prod.outlook.com (2603:10b6:208:319::21) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4287.27; 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redhat.com; dkim=none (message not signed)\n header.d=none;redhat.com; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Viacheslav Ovsiienko <viacheslavo@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<rasland@nvidia.com>, <matan@nvidia.com>, <thomas@monjalon.net>,\n <david.marchand@redhat.com>, <stable@dpdk.org>", "Date": "Wed, 7 Jul 2021 18:54:27 +0300", "Message-ID": "<20210707155428.13178-1-viacheslavo@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "\n <CAJFAV8yYp1W0WAWawHVnpwP3trvgfCcbazoKZzLD3L+g4yLhcg@mail.gmail.com>", "References": "\n <CAJFAV8yYp1W0WAWawHVnpwP3trvgfCcbazoKZzLD3L+g4yLhcg@mail.gmail.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "82e8df21-284a-4db8-c298-08d9415f8be6", "X-MS-TrafficTypeDiagnostic": "BL1PR12MB5240:", "X-LD-Processed": "43083d15-7273-40c1-b7db-39efd9ccc17a,ExtAddr", "X-Microsoft-Antispam-PRVS": "\n <BL1PR12MB5240EB3F74C3EB87E3B17CDEDF1A9@BL1PR12MB5240.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:7219;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n KjBJR/nX55LihHGbPCbpX9iP4urWexNpHPdVyAOW1COr0/b2BuNiuxaZsc1M+9eq+Hlsmf14JcJ0XgT6wV8TGnj8jOZfP+3AAmCl9s8LqQ+j54cc5orqpdsef58puUtSdfoEv3AKBH/0zDuR4YaTmABRTKytGZWZvQ5RKTtY1aPpuPO7BminUe2vu4GUVzQQRSMSzq0Jd5EC9wOL1S7jf8927hO+yLeTUT83a/GND8fJaxeJVsxldsAwAzDfUNAAkiOQNbNYKety8StFM5njmaWmBzuDlrk2zRo4oEhC8PUXgc23AcaF+nG7zcL54C9yPXFoV50A2W0233abarW4jCTntakznIW+tpbkqVq/j0aN1tYODMGi+/tt5e/G4GpJI46zEmiUrC+8v00Q/ze5bbqVmJso4XuESd+rNQ3fub4o6RiiJ0Q5KTmV+0EjoOiszeOm1V7PfmY5Qjga74ZMaajeLNYSbtS2L7OByao3PoDGVef+vSzLSqwIKdm48uC4tnOMsLTC5Y4qMtYTZ53QEiIqlKl3R+DrtMz7n8o5kU33hEzpDtpFEuLqKM8MK1HBDEU57bXZUk9qxc5JhC3GrhgDK9xwyrsGu4CLYcCfUALLLlkOuwOzqaBt62pAoiFLbxQskALM1bRIaBA1dR9ZGUVVa76aKvbBcPTTWY+yTIlHwbSxSflWQtAvyVG9+w2S0MCnwEJiQNWkUwcb88C5MA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(346002)(136003)(396003)(376002)(39860400002)(36840700001)(46966006)(26005)(70586007)(2906002)(8936002)(1076003)(36756003)(316002)(186003)(86362001)(16526019)(356005)(55016002)(82310400003)(83380400001)(2616005)(36906005)(8676002)(47076005)(36860700001)(478600001)(5660300002)(70206006)(7636003)(336012)(82740400003)(4326008)(6666004)(6286002)(6916009)(7696005)(54906003)(426003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Jul 2021 15:54:47.3361 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 82e8df21-284a-4db8-c298-08d9415f8be6", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n CO1NAM11FT048.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BL1PR12MB5240", "Subject": "[dpdk-dev] [PATCH v4 1/2] common/mlx5: add provider query port\n support to glue library", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In order to get E-Switch vport identifiers the mlx5 PMD relies\non two approaches:\n [a] use port query API if it is provided by rdma-core library\n [b] otherwise, deduce vport ids from the related VF index\nThe latter is not reliable and may not work with newer kernel\ndrivers and in some configurations (LAG), causing E-Switch\nmalfunction. Hence, engaging the port query API is highly\ndesirable.\n\nDepending on rdma-core version the port query API is:\n - very old OFED versions have no query API (approach [b])\n - rdma-core OFED < 5.5 provides mlx5dv_query_devx_port,\n HAVE_MLX5DV_DR_DEVX_PORT flag is defined (approach [a])\n - rdma-core OFED >= 5.5 has mlx5dv_query_port, flag\n HAVE_MLX5DV_DR_DEVX_PORT_V35 is defined (approach [a])\n - future OFED versions might remove mlx5dv_query_devx_port\n and HAVE_MLX5DV_DR_DEVX_PORT will not be defined\n - Upstream rdma-core < v35 has no port query API (approach [b])\n - Upstream rdma-core >= v35 has mlx5dv_query_port, flag\n HAVE_MLX5DV_DR_DEVX_PORT_V35 is defined (approach [a])\n\nIn order to support the new mlx5dv_query_port routine, the\nconditional compilation flag HAVE_MLX5DV_DR_DEVX_PORT_V35\nis introduced by the this patch. The flag HAVE_MLX5DV_DR_DEVX_PORT\nis kept for compatibility with previous rdma-core versions.\n\nDespite this patch is not a bugfix (it follows the introduced API\nvariation in underlying library), it resolves the compatibility\nissue and is highly desired to be ported to DPDK LTS.\n\nCc: stable@dpdk.org\n\nSigned-off-by: Viacheslav Ovsiienko <viacheslavo@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/common/mlx5/linux/meson.build | 2 +\n drivers/common/mlx5/linux/mlx5_glue.c | 55 ++++++++++++++++++++----\n drivers/common/mlx5/linux/mlx5_glue.h | 16 ++++++-\n drivers/net/mlx5/linux/mlx5_os.c | 60 ++++++++++++---------------\n 4 files changed, 89 insertions(+), 44 deletions(-)", "diff": "diff --git a/drivers/common/mlx5/linux/meson.build b/drivers/common/mlx5/linux/meson.build\nindex 007834a49b..7168edc62c 100644\n--- a/drivers/common/mlx5/linux/meson.build\n+++ b/drivers/common/mlx5/linux/meson.build\n@@ -93,6 +93,8 @@ has_sym_args = [\n 'IBV_WQ_FLAG_RX_END_PADDING' ],\n [ 'HAVE_MLX5DV_DR_DEVX_PORT', 'infiniband/mlx5dv.h',\n 'mlx5dv_query_devx_port' ],\n+ [ 'HAVE_MLX5DV_DR_DEVX_PORT_V35', 'infiniband/mlx5dv.h',\n+ 'mlx5dv_query_port' ],\n [ 'HAVE_IBV_DEVX_OBJ', 'infiniband/mlx5dv.h',\n 'mlx5dv_devx_obj_create' ],\n [ 'HAVE_IBV_FLOW_DEVX_COUNTERS', 'infiniband/mlx5dv.h',\ndiff --git a/drivers/common/mlx5/linux/mlx5_glue.c b/drivers/common/mlx5/linux/mlx5_glue.c\nindex d3bd645a5b..38b174aa31 100644\n--- a/drivers/common/mlx5/linux/mlx5_glue.c\n+++ b/drivers/common/mlx5/linux/mlx5_glue.c\n@@ -1087,17 +1087,54 @@ mlx5_glue_devx_wq_query(struct ibv_wq *wq, const void *in, size_t inlen,\n static int\n mlx5_glue_devx_port_query(struct ibv_context *ctx,\n \t\t\t uint32_t port_num,\n-\t\t\t struct mlx5dv_devx_port *mlx5_devx_port)\n-{\n+\t\t\t struct mlx5_port_info *info)\n+{\n+\tint err = 0;\n+\n+\tinfo->query_flags = 0;\n+#ifdef HAVE_MLX5DV_DR_DEVX_PORT_V35\n+\t/* The DevX port query API is implemented (rdma-core v35 and above). */\n+\tstruct mlx5_ib_uapi_query_port devx_port;\n+\n+\tmemset(&devx_port, 0, sizeof(devx_port));\n+\terr = mlx5dv_query_port(ctx, port_num, &devx_port);\n+\tif (err)\n+\t\treturn err;\n+\tif (devx_port.flags & MLX5DV_QUERY_PORT_VPORT_REG_C0) {\n+\t\tinfo->vport_meta_tag = devx_port.reg_c0.value;\n+\t\tinfo->vport_meta_mask = devx_port.reg_c0.mask;\n+\t\tinfo->query_flags |= MLX5_PORT_QUERY_REG_C0;\n+\t}\n+\tif (devx_port.flags & MLX5DV_QUERY_PORT_VPORT) {\n+\t\tinfo->vport_id = devx_port.vport;\n+\t\tinfo->query_flags |= MLX5_PORT_QUERY_VPORT;\n+\t}\n+#else\n #ifdef HAVE_MLX5DV_DR_DEVX_PORT\n-\treturn mlx5dv_query_devx_port(ctx, port_num, mlx5_devx_port);\n+\t/* The legacy DevX port query API is implemented (prior v35). */\n+\tstruct mlx5dv_devx_port devx_port = {\n+\t\t.comp_mask = MLX5DV_DEVX_PORT_VPORT |\n+\t\t\t MLX5DV_DEVX_PORT_MATCH_REG_C_0\n+\t};\n+\n+\terr = mlx5dv_query_devx_port(ctx, port_num, &devx_port);\n+\tif (err)\n+\t\treturn err;\n+\tif (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {\n+\t\tinfo->vport_meta_tag = devx_port.reg_c_0.value;\n+\t\tinfo->vport_meta_mask = devx_port.reg_c_0.mask;\n+\t\tinfo->query_flags |= MLX5_PORT_QUERY_REG_C0;\n+\t}\n+\tif (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {\n+\t\tinfo->vport_id = devx_port.vport_num;\n+\t\tinfo->query_flags |= MLX5_PORT_QUERY_VPORT;\n+\t}\n #else\n-\t(void)ctx;\n-\t(void)port_num;\n-\t(void)mlx5_devx_port;\n-\terrno = ENOTSUP;\n-\treturn errno;\n-#endif\n+\tRTE_SET_USED(ctx);\n+\tRTE_SET_USED(port_num);\n+#endif /* HAVE_MLX5DV_DR_DEVX_PORT */\n+#endif /* HAVE_MLX5DV_DR_DEVX_PORT_V35 */\n+\treturn err;\n }\n \n static int\ndiff --git a/drivers/common/mlx5/linux/mlx5_glue.h b/drivers/common/mlx5/linux/mlx5_glue.h\nindex 97462e9ab8..840d8cf57f 100644\n--- a/drivers/common/mlx5/linux/mlx5_glue.h\n+++ b/drivers/common/mlx5/linux/mlx5_glue.h\n@@ -84,6 +84,20 @@ struct mlx5dv_dr_action;\n struct mlx5dv_devx_port;\n #endif\n \n+#ifndef HAVE_MLX5DV_DR_DEVX_PORT_V35\n+struct mlx5dv_port;\n+#endif\n+\n+#define MLX5_PORT_QUERY_VPORT (1u << 0)\n+#define MLX5_PORT_QUERY_REG_C0 (1u << 1)\n+\n+struct mlx5_port_info {\n+\tuint16_t query_flags;\n+\tuint16_t vport_id; /* Associated VF vport index (if any). */\n+\tuint32_t vport_meta_tag; /* Used for vport index match ove VF LAG. */\n+\tuint32_t vport_meta_mask; /* Used for vport index field match mask. */\n+};\n+\n #ifndef HAVE_MLX5_DR_CREATE_ACTION_FLOW_METER\n struct mlx5dv_dr_flow_meter_attr;\n #endif\n@@ -311,7 +325,7 @@ struct mlx5_glue {\n \t\t\t void *out, size_t outlen);\n \tint (*devx_port_query)(struct ibv_context *ctx,\n \t\t\t uint32_t port_num,\n-\t\t\t struct mlx5dv_devx_port *mlx5_devx_port);\n+\t\t\t struct mlx5_port_info *info);\n \tint (*dr_dump_domain)(FILE *file, void *domain);\n \tint (*dr_dump_rule)(FILE *file, void *rule);\n \tint (*devx_query_eqn)(struct ibv_context *context, uint32_t cpus,\ndiff --git a/drivers/net/mlx5/linux/mlx5_os.c b/drivers/net/mlx5/linux/mlx5_os.c\nindex 302a881310..92b3009786 100644\n--- a/drivers/net/mlx5/linux/mlx5_os.c\n+++ b/drivers/net/mlx5/linux/mlx5_os.c\n@@ -822,9 +822,7 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tchar name[RTE_ETH_NAME_MAX_LEN];\n \tint own_domain_id = 0;\n \tuint16_t port_id;\n-#ifdef HAVE_MLX5DV_DR_DEVX_PORT\n-\tstruct mlx5dv_devx_port devx_port = { .comp_mask = 0 };\n-#endif\n+\tstruct mlx5_port_info vport_info = { .query_flags = 0 };\n \n \t/* Determine if this port representor is supposed to be spawned. */\n \tif (switch_info->representor && dpdk_dev->devargs &&\n@@ -1055,29 +1053,27 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \tpriv->vport_meta_tag = 0;\n \tpriv->vport_meta_mask = 0;\n \tpriv->pf_bond = spawn->pf_bond;\n-#ifdef HAVE_MLX5DV_DR_DEVX_PORT\n \t/*\n-\t * The DevX port query API is implemented. E-Switch may use\n-\t * either vport or reg_c[0] metadata register to match on\n-\t * vport index. The engaged part of metadata register is\n-\t * defined by mask.\n+\t * If we have E-Switch we should determine the vport attributes.\n+\t * E-Switch may use either source vport field or reg_c[0] metadata\n+\t * register to match on vport index. The engaged part of metadata\n+\t * register is defined by mask.\n \t */\n \tif (switch_info->representor || switch_info->master) {\n-\t\tdevx_port.comp_mask = MLX5DV_DEVX_PORT_VPORT |\n-\t\t\t\t MLX5DV_DEVX_PORT_MATCH_REG_C_0;\n-\t\terr = mlx5_glue->devx_port_query(sh->ctx, spawn->phys_port,\n-\t\t\t\t\t\t &devx_port);\n+\t\terr = mlx5_glue->devx_port_query(sh->ctx,\n+\t\t\t\t\t\t spawn->phys_port,\n+\t\t\t\t\t\t &vport_info);\n \t\tif (err) {\n \t\t\tDRV_LOG(WARNING,\n \t\t\t\t\"can't query devx port %d on device %s\",\n \t\t\t\tspawn->phys_port,\n \t\t\t\tmlx5_os_get_dev_device_name(spawn->phys_dev));\n-\t\t\tdevx_port.comp_mask = 0;\n+\t\t\tvport_info.query_flags = 0;\n \t\t}\n \t}\n-\tif (devx_port.comp_mask & MLX5DV_DEVX_PORT_MATCH_REG_C_0) {\n-\t\tpriv->vport_meta_tag = devx_port.reg_c_0.value;\n-\t\tpriv->vport_meta_mask = devx_port.reg_c_0.mask;\n+\tif (vport_info.query_flags & MLX5_PORT_QUERY_REG_C0) {\n+\t\tpriv->vport_meta_tag = vport_info.vport_meta_tag;\n+\t\tpriv->vport_meta_mask = vport_info.vport_meta_mask;\n \t\tif (!priv->vport_meta_mask) {\n \t\t\tDRV_LOG(ERR, \"vport zero mask for port %d\"\n \t\t\t\t \" on bonding device %s\",\n@@ -1097,8 +1093,8 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\t\tgoto error;\n \t\t}\n \t}\n-\tif (devx_port.comp_mask & MLX5DV_DEVX_PORT_VPORT) {\n-\t\tpriv->vport_id = devx_port.vport_num;\n+\tif (vport_info.query_flags & MLX5_PORT_QUERY_VPORT) {\n+\t\tpriv->vport_id = vport_info.vport_id;\n \t} else if (spawn->pf_bond >= 0 &&\n \t\t (switch_info->representor || switch_info->master)) {\n \t\tDRV_LOG(ERR, \"can't deduce vport index for port %d\"\n@@ -1108,25 +1104,21 @@ mlx5_dev_spawn(struct rte_device *dpdk_dev,\n \t\terr = ENOTSUP;\n \t\tgoto error;\n \t} else {\n-\t\t/* Suppose vport index in compatible way. */\n+\t\t/*\n+\t\t * Suppose vport index in compatible way. Kernel/rdma_core\n+\t\t * support single E-Switch per PF configurations only and\n+\t\t * vport_id field contains the vport index for associated VF,\n+\t\t * which is deduced from representor port name.\n+\t\t * For example, let's have the IB device port 10, it has\n+\t\t * attached network device eth0, which has port name attribute\n+\t\t * pf0vf2, we can deduce the VF number as 2, and set vport index\n+\t\t * as 3 (2+1). This assigning schema should be changed if the\n+\t\t * multiple E-Switch instances per PF configurations or/and PCI\n+\t\t * subfunctions are added.\n+\t\t */\n \t\tpriv->vport_id = switch_info->representor ?\n \t\t\t\t switch_info->port_name + 1 : -1;\n \t}\n-#else\n-\t/*\n-\t * Kernel/rdma_core support single E-Switch per PF configurations\n-\t * only and vport_id field contains the vport index for\n-\t * associated VF, which is deduced from representor port name.\n-\t * For example, let's have the IB device port 10, it has\n-\t * attached network device eth0, which has port name attribute\n-\t * pf0vf2, we can deduce the VF number as 2, and set vport index\n-\t * as 3 (2+1). This assigning schema should be changed if the\n-\t * multiple E-Switch instances per PF configurations or/and PCI\n-\t * subfunctions are added.\n-\t */\n-\tpriv->vport_id = switch_info->representor ?\n-\t\t\t switch_info->port_name + 1 : -1;\n-#endif\n \tpriv->representor_id = mlx5_representor_id_encode(switch_info,\n \t\t\t\t\t\t\t eth_da->type);\n \t/*\n", "prefixes": [ "v4", "1/2" ] }