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GET /api/patches/95495/?format=api
{ "id": 95495, "url": "https://patches.dpdk.org/api/patches/95495/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210707120303.2490006-2-michaelba@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210707120303.2490006-2-michaelba@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210707120303.2490006-2-michaelba@nvidia.com", "date": "2021-07-07T12:03:01", "name": "[PATCH_v3,1/3] regex/mlx5: fix memory region unregistration", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "7c7f6d24d82a6d36c473eee85687cffd75ed6326", "submitter": { "id": 1949, "url": "https://patches.dpdk.org/api/people/1949/?format=api", "name": "Michael Baum", "email": "michaelba@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210707120303.2490006-2-michaelba@nvidia.com/mbox/", "series": [ { "id": 17699, "url": "https://patches.dpdk.org/api/series/17699/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17699", "date": "2021-07-07T12:03:00", "name": "regex/mlx5: some independent fixes", "version": 1, "mbox": "https://patches.dpdk.org/series/17699/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95495/comments/", "check": "fail", "checks": "https://patches.dpdk.org/api/patches/95495/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", 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header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Michael Baum <michaelba@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "Matan Azrad <matan@nvidia.com>, Raslan Darawsheh <rasland@nvidia.com>,\n Viacheslav Ovsiienko <viacheslavo@nvidia.com>, <stable@dpdk.org>", "Date": "Wed, 7 Jul 2021 15:03:01 +0300", "Message-ID": "<20210707120303.2490006-2-michaelba@nvidia.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": "<20210707120303.2490006-1-michaelba@nvidia.com>", "References": "<20210705052730.2283962-1-michaelba@nvidia.com>\n <20210707120303.2490006-1-michaelba@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com 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JRZCFHXOdj1aMeSiOEjybE0qtWu/O7QzE0PhIRjPGU+Y8RUYHESltvNN72ku9tQJC1996jXTUdmJphQ7FwUOziG/NjQDjXO7JngOMu/DJEZNLTlS99f1NUD7r5fzNEhNuMsIJEtWYGXcHlxF0Vsm9tc5q9QSVxAPG9yYP7M4l8hfnZ6sRuopHvMKxSRDFndCoWxA8biPKgkXjZQXEDVyo99XH52fq33JZl2Cg+rZTIwZsW20rZWWPDsCCC+S2Gj57oegIxUPYTwpjGg8Mg0eTHSi8GoSwdRcUxzkpVVl5AGbpwfMn2Z5iyB75YBJ5lA0wRuzgRD2etbbBsZg17sPAOEoyXSV7+Sd1FkIQgALcqzmRY9wh5Xt+Gyt0hwigoXhVV+XtsQ1rlMGKtdNH6wcMefip2m8jCKj/Lj0cb4SFfBaozVKbS2HIcCeefBOcQCKTbEmHd3J/CUQTXNYKQHvnfIa0rL2D1sxRiK+MT6ppIDVAilA6pZCOHCIDW4SPfD11nZRJmH0JEJadXQMqK96Y6PYSVubiakDuGM2u+OuuN4AHOUwSI3gd8j24Vu0M6D6ANBQ0QRXxAoS5XrcxodKcdidBNzymcJ54KbIXGvTBnjH3nqahXuQxEvBVC/3joAaguEkipdmGgB1pp5yfJcGhB5zJwWTPFAbDi2ElgqpgdAyRFnCcsWHPLPhG+Lt1Jx3KWWAZVlGnTXV52OZAFXH/A==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(39860400002)(396003)(136003)(376002)(346002)(46966006)(36840700001)(7636003)(316002)(36906005)(450100002)(6666004)(5660300002)(26005)(70206006)(186003)(82740400003)(54906003)(55016002)(8936002)(6286002)(6916009)(16526019)(7696005)(8676002)(4326008)(47076005)(2906002)(1076003)(2616005)(36756003)(83380400001)(82310400003)(86362001)(426003)(36860700001)(478600001)(336012)(70586007)(356005);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "07 Jul 2021 12:03:36.5663 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 9f2feced-ad64-4271-b10c-08d9413f4052", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT015.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN9PR12MB5381", "Subject": "[dpdk-dev] [PATCH_v3 1/3] regex/mlx5: fix memory region\n unregistration", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "The issue can cause illegal physical address access while a huge-page A\nis released and huge-page B is allocated on the same virtual address.\nThe old MR can be matched using the virtual address of huge-page B but\nthe HW will access the physical address of huge-page A which is no more\npart of the DPDK process.\n\nRegister a driver callback for memory event in order to free out all the\nMRs of memory that is going to be freed from the dpdk process.\n\nFixes: cda883bbb655 (\"regex/mlx5: add dynamic memory registration to datapath\")\nCc: stable@dpdk.org\n\nSigned-off-by: Michael Baum <michaelba@nvidia.com>\n---\n drivers/regex/mlx5/mlx5_regex.c | 55 ++++++++++++++++++++++++\n drivers/regex/mlx5/mlx5_regex.h | 2 +\n drivers/regex/mlx5/mlx5_regex_control.c | 2 +\n drivers/regex/mlx5/mlx5_regex_fastpath.c | 50 +++++++++++++++------\n 4 files changed, 97 insertions(+), 12 deletions(-)", "diff": "diff --git a/drivers/regex/mlx5/mlx5_regex.c b/drivers/regex/mlx5/mlx5_regex.c\nindex dcb2ced88e..0f12d94d7e 100644\n--- a/drivers/regex/mlx5/mlx5_regex.c\n+++ b/drivers/regex/mlx5/mlx5_regex.c\n@@ -11,6 +11,7 @@\n #include <rte_regexdev_driver.h>\n \n #include <mlx5_common_pci.h>\n+#include <mlx5_common_mr.h>\n #include <mlx5_common.h>\n #include <mlx5_glue.h>\n #include <mlx5_devx_cmds.h>\n@@ -24,6 +25,10 @@\n \n int mlx5_regex_logtype;\n \n+TAILQ_HEAD(regex_mem_event, mlx5_regex_priv) mlx5_mem_event_list =\n+\t\t\t\tTAILQ_HEAD_INITIALIZER(mlx5_mem_event_list);\n+static pthread_mutex_t mem_event_list_lock = PTHREAD_MUTEX_INITIALIZER;\n+\n const struct rte_regexdev_ops mlx5_regexdev_ops = {\n \t.dev_info_get = mlx5_regex_info_get,\n \t.dev_configure = mlx5_regex_configure,\n@@ -82,6 +87,40 @@ mlx5_regex_get_name(char *name, struct rte_pci_device *pci_dev __rte_unused)\n \t\tpci_dev->addr.devid, pci_dev->addr.function);\n }\n \n+/**\n+ * Callback for memory event.\n+ *\n+ * @param event_type\n+ * Memory event type.\n+ * @param addr\n+ * Address of memory.\n+ * @param len\n+ * Size of memory.\n+ */\n+static void\n+mlx5_regex_mr_mem_event_cb(enum rte_mem_event event_type, const void *addr,\n+\t\t\t size_t len, void *arg __rte_unused)\n+{\n+\tstruct mlx5_regex_priv *priv;\n+\n+\t/* Must be called from the primary process. */\n+\tMLX5_ASSERT(rte_eal_process_type() == RTE_PROC_PRIMARY);\n+\tswitch (event_type) {\n+\tcase RTE_MEM_EVENT_FREE:\n+\t\tpthread_mutex_lock(&mem_event_list_lock);\n+\t\t/* Iterate all the existing mlx5 devices. */\n+\t\tTAILQ_FOREACH(priv, &mlx5_mem_event_list, mem_event_cb)\n+\t\t\tmlx5_free_mr_by_addr(&priv->mr_scache,\n+\t\t\t\t\t priv->ctx->device->name,\n+\t\t\t\t\t addr, len);\n+\t\tpthread_mutex_unlock(&mem_event_list_lock);\n+\t\tbreak;\n+\tcase RTE_MEM_EVENT_ALLOC:\n+\tdefault:\n+\t\tbreak;\n+\t}\n+}\n+\n static int\n mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t\t struct rte_pci_device *pci_dev)\n@@ -193,6 +232,15 @@ mlx5_regex_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,\n \t rte_errno = ENOMEM;\n \t\tgoto error;\n \t}\n+\t/* Register callback function for global shared MR cache management. */\n+\tif (TAILQ_EMPTY(&mlx5_mem_event_list))\n+\t\trte_mem_event_callback_register(\"MLX5_MEM_EVENT_CB\",\n+\t\t\t\t\t\tmlx5_regex_mr_mem_event_cb,\n+\t\t\t\t\t\tNULL);\n+\t/* Add device to memory callback list. */\n+\tpthread_mutex_lock(&mem_event_list_lock);\n+\tTAILQ_INSERT_TAIL(&mlx5_mem_event_list, priv, mem_event_cb);\n+\tpthread_mutex_unlock(&mem_event_list_lock);\n \tDRV_LOG(INFO, \"RegEx GGA is %s.\",\n \t\tpriv->has_umr ? \"supported\" : \"unsupported\");\n \treturn 0;\n@@ -225,6 +273,13 @@ mlx5_regex_pci_remove(struct rte_pci_device *pci_dev)\n \t\treturn 0;\n \tpriv = dev->data->dev_private;\n \tif (priv) {\n+\t\t/* Remove from memory callback device list. */\n+\t\tpthread_mutex_lock(&mem_event_list_lock);\n+\t\tTAILQ_REMOVE(&mlx5_mem_event_list, priv, mem_event_cb);\n+\t\tpthread_mutex_unlock(&mem_event_list_lock);\n+\t\tif (TAILQ_EMPTY(&mlx5_mem_event_list))\n+\t\t\trte_mem_event_callback_unregister(\"MLX5_MEM_EVENT_CB\",\n+\t\t\t\t\t\t\t NULL);\n \t\tif (priv->pd)\n \t\t\tmlx5_glue->dealloc_pd(priv->pd);\n \t\tif (priv->uar)\ndiff --git a/drivers/regex/mlx5/mlx5_regex.h b/drivers/regex/mlx5/mlx5_regex.h\nindex 51a2101e53..61f59ba873 100644\n--- a/drivers/regex/mlx5/mlx5_regex.h\n+++ b/drivers/regex/mlx5/mlx5_regex.h\n@@ -70,6 +70,8 @@ struct mlx5_regex_priv {\n \tuint32_t nb_engines; /* Number of RegEx engines. */\n \tstruct mlx5dv_devx_uar *uar; /* UAR object. */\n \tstruct ibv_pd *pd;\n+\tTAILQ_ENTRY(mlx5_regex_priv) mem_event_cb;\n+\t/**< Called by memory event callback. */\n \tstruct mlx5_mr_share_cache mr_scache; /* Global shared MR cache. */\n \tuint8_t is_bf2; /* The device is BF2 device. */\n \tuint8_t sq_ts_format; /* Whether SQ supports timestamp formats. */\ndiff --git a/drivers/regex/mlx5/mlx5_regex_control.c b/drivers/regex/mlx5/mlx5_regex_control.c\nindex eef0fe579d..8ce2dabb55 100644\n--- a/drivers/regex/mlx5/mlx5_regex_control.c\n+++ b/drivers/regex/mlx5/mlx5_regex_control.c\n@@ -246,6 +246,8 @@ mlx5_regex_qp_setup(struct rte_regexdev *dev, uint16_t qp_ind,\n \t\tnb_sq_config++;\n \t}\n \n+\t/* Save pointer of global generation number to check memory event. */\n+\tqp->mr_ctrl.dev_gen_ptr = &priv->mr_scache.dev_gen;\n \tret = mlx5_mr_btree_init(&qp->mr_ctrl.cache_bh, MLX5_MR_BTREE_CACHE_N,\n \t\t\t\t rte_socket_id());\n \tif (ret) {\ndiff --git a/drivers/regex/mlx5/mlx5_regex_fastpath.c b/drivers/regex/mlx5/mlx5_regex_fastpath.c\nindex b57e7d7794..6d5096701f 100644\n--- a/drivers/regex/mlx5/mlx5_regex_fastpath.c\n+++ b/drivers/regex/mlx5/mlx5_regex_fastpath.c\n@@ -109,6 +109,40 @@ set_wqe_ctrl_seg(struct mlx5_wqe_ctrl_seg *seg, uint16_t pi, uint8_t opcode,\n \tseg->imm = imm;\n }\n \n+/**\n+ * Query LKey from a packet buffer for QP. If not found, add the mempool.\n+ *\n+ * @param priv\n+ * Pointer to the priv object.\n+ * @param mr_ctrl\n+ * Pointer to per-queue MR control structure.\n+ * @param mbuf\n+ * Pointer to source mbuf, to search in.\n+ *\n+ * @return\n+ * Searched LKey on success, UINT32_MAX on no match.\n+ */\n+static inline uint32_t\n+mlx5_regex_addr2mr(struct mlx5_regex_priv *priv, struct mlx5_mr_ctrl *mr_ctrl,\n+\t\t struct rte_mbuf *mbuf)\n+{\n+\tuintptr_t addr = rte_pktmbuf_mtod(mbuf, uintptr_t);\n+\tuint32_t lkey;\n+\n+\t/* Check generation bit to see if there's any change on existing MRs. */\n+\tif (unlikely(*mr_ctrl->dev_gen_ptr != mr_ctrl->cur_gen))\n+\t\tmlx5_mr_flush_local_cache(mr_ctrl);\n+\t/* Linear search on MR cache array. */\n+\tlkey = mlx5_mr_lookup_lkey(mr_ctrl->cache, &mr_ctrl->mru,\n+\t\t\t\t MLX5_MR_CACHE_N, addr);\n+\tif (likely(lkey != UINT32_MAX))\n+\t\treturn lkey;\n+\t/* Take slower bottom-half on miss. */\n+\treturn mlx5_mr_addr2mr_bh(priv->pd, 0, &priv->mr_scache, mr_ctrl, addr,\n+\t\t\t\t !!(mbuf->ol_flags & EXT_ATTACHED_MBUF));\n+}\n+\n+\n static inline void\n __prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_sq *sq,\n \t struct rte_regex_ops *op, struct mlx5_regex_job *job,\n@@ -160,10 +194,7 @@ prep_one(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n \tstruct mlx5_klm klm;\n \n \tklm.byte_count = rte_pktmbuf_data_len(op->mbuf);\n-\tklm.mkey = mlx5_mr_addr2mr_bh(priv->pd, 0,\n-\t\t\t\t &priv->mr_scache, &qp->mr_ctrl,\n-\t\t\t\t rte_pktmbuf_mtod(op->mbuf, uintptr_t),\n-\t\t\t\t !!(op->mbuf->ol_flags & EXT_ATTACHED_MBUF));\n+\tklm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, op->mbuf);\n \tklm.address = rte_pktmbuf_mtod(op->mbuf, uintptr_t);\n \t__prep_one(priv, sq, op, job, sq->pi, &klm);\n \tsq->db_pi = sq->pi;\n@@ -329,10 +360,8 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n \t\t\t\t\t(qp->jobs[mkey_job_id].imkey->id);\n \t\t\twhile (mbuf) {\n \t\t\t\t/* Build indirect mkey seg's KLM. */\n-\t\t\t\tmkey_klm->mkey = mlx5_mr_addr2mr_bh(priv->pd,\n-\t\t\t\t\tNULL, &priv->mr_scache, &qp->mr_ctrl,\n-\t\t\t\t\trte_pktmbuf_mtod(mbuf, uintptr_t),\n-\t\t\t\t\t!!(mbuf->ol_flags & EXT_ATTACHED_MBUF));\n+\t\t\t\tmkey_klm->mkey = mlx5_regex_addr2mr\n+\t\t\t\t\t\t(priv, &qp->mr_ctrl, mbuf);\n \t\t\t\tmkey_klm->address = rte_cpu_to_be_64\n \t\t\t\t\t(rte_pktmbuf_mtod(mbuf, uintptr_t));\n \t\t\t\tmkey_klm->byte_count = rte_cpu_to_be_32\n@@ -350,10 +379,7 @@ prep_regex_umr_wqe_set(struct mlx5_regex_priv *priv, struct mlx5_regex_qp *qp,\n \t\t\tklm.byte_count = scatter_size;\n \t\t} else {\n \t\t\t/* The single mubf case. Build the KLM directly. */\n-\t\t\tklm.mkey = mlx5_mr_addr2mr_bh(priv->pd, NULL,\n-\t\t\t\t\t&priv->mr_scache, &qp->mr_ctrl,\n-\t\t\t\t\trte_pktmbuf_mtod(mbuf, uintptr_t),\n-\t\t\t\t\t!!(mbuf->ol_flags & EXT_ATTACHED_MBUF));\n+\t\t\tklm.mkey = mlx5_regex_addr2mr(priv, &qp->mr_ctrl, mbuf);\n \t\t\tklm.address = rte_pktmbuf_mtod(mbuf, uintptr_t);\n \t\t\tklm.byte_count = rte_pktmbuf_data_len(mbuf);\n \t\t}\n", "prefixes": [ "PATCH_v3", "1/3" ] }