Patch Detail
get:
Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/patches/95390/?format=api
{ "id": 95390, "url": "https://patches.dpdk.org/api/patches/95390/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210706133257.3353-4-suanmingm@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210706133257.3353-4-suanmingm@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210706133257.3353-4-suanmingm@nvidia.com", "date": "2021-07-06T13:32:34", "name": "[v4,03/26] net/mlx5: add index pool foreach define", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": true, "hash": "2238ae9343bf153c0545b862cb4045faa5761be4", "submitter": { "id": 1887, "url": "https://patches.dpdk.org/api/people/1887/?format=api", "name": "Suanming Mou", "email": "suanmingm@nvidia.com" }, "delegate": { "id": 3268, "url": "https://patches.dpdk.org/api/users/3268/?format=api", "username": "rasland", "first_name": "Raslan", "last_name": "Darawsheh", "email": "rasland@nvidia.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210706133257.3353-4-suanmingm@nvidia.com/mbox/", "series": [ { "id": 17668, "url": "https://patches.dpdk.org/api/series/17668/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17668", "date": "2021-07-06T13:32:31", "name": "net/mlx5: insertion rate optimization", "version": 4, "mbox": "https://patches.dpdk.org/series/17668/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95390/comments/", "check": "warning", "checks": "https://patches.dpdk.org/api/patches/95390/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id BBCD1A0C47;\n\tTue, 6 Jul 2021 15:33:44 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id B32234138B;\n\tTue, 6 Jul 2021 15:33:29 +0200 (CEST)", "from NAM11-BN8-obe.outbound.protection.outlook.com\n (mail-bn8nam11on2083.outbound.protection.outlook.com [40.107.236.83])\n by mails.dpdk.org (Postfix) with ESMTP id AEC7941367\n for <dev@dpdk.org>; Tue, 6 Jul 2021 15:33:28 +0200 (CEST)", "from BN0PR02CA0059.namprd02.prod.outlook.com (2603:10b6:408:e5::34)\n by MW2PR12MB2378.namprd12.prod.outlook.com (2603:10b6:907:f::15) with\n Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4287.27; Tue, 6 Jul\n 2021 13:33:25 +0000", "from BN8NAM11FT047.eop-nam11.prod.protection.outlook.com\n (2603:10b6:408:e5:cafe::5f) by BN0PR02CA0059.outlook.office365.com\n (2603:10b6:408:e5::34) with Microsoft SMTP Server (version=TLS1_2,\n cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4308.20 via Frontend\n Transport; Tue, 6 Jul 2021 13:33:24 +0000", "from mail.nvidia.com (216.228.112.34) by\n BN8NAM11FT047.mail.protection.outlook.com (10.13.177.220) with Microsoft SMTP\n Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id\n 15.20.4287.22 via Frontend Transport; Tue, 6 Jul 2021 13:33:24 +0000", "from nvidia.com (172.20.187.6) by HQMAIL107.nvidia.com\n (172.20.187.13) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 6 Jul\n 2021 13:33:22 +0000" ], "ARC-Seal": "i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none;\n b=byfU0KWDc/+YtRFwagRxbXIhds4dqP1dfeVvSw4bGTxkEaFXK5HJBIVQZNDsq9CmIwfiEOAcT+YwtHOqYExdoxde6GbrM29E5UVAmrXnFtngzysLbehKo6kXud7JXkrJU0TIhlN4P8+u7pl0s7LpBBWtRnBu68F9h1qi7/R2jB145rzsR3HlHbOVq74l/LmqJXwNLVW8+taZ6nwblpyiZT2dqA6yMU/WNcTTmDVhq/cDk8iEYpJRoG7/mIswoAjKCU4ic0W/w88s6rvvhptO7R+NWeO7FCiviREvde9YTekAiI9HIaR57saEhdaf/4sUCljM/R0qo8MPbOpapgmXCQ==", "ARC-Message-Signature": "i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com;\n s=arcselector9901;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=whPPfUGImCWDw9H8NLoASnEJAELcHjAacM0mL6bfyow=;\n b=EgIPcmgs0SfeQ9pxKApsZM4jMFNnxklbxQoc+w1zLxN73bcJW0hWRF90RrsiDS5rH579Q0M/dZ4nsChvpcPcA5RqJ7G6VBJhdZgW/zTwq4SIXL6bTusHDcWYwFQXS1NSvpwIVbv5CUr5ZI+kHTDTp8cTz6RGE/u+41CFnRo18Babgn09Oa4reqLOZmjNJ39UyzAJp/HZTILy/smzsVl+F3C/Hpy/ljOFfMhs7wA7AaPe9JjgPcl+rPmT/UPVROG9Ua51AbK4NwqPtqrAuMBMIZt97QGacy6H159YfhNpZb9spmkdHN4HgtZbw+wqYLb/oLhx/R+LNG0g+M8uLIYawg==", "ARC-Authentication-Results": "i=1; mx.microsoft.com 1; spf=pass (sender ip is\n 216.228.112.34) smtp.rcpttodomain=dpdk.org smtp.mailfrom=nvidia.com;\n dmarc=pass (p=none sp=none pct=100) action=none header.from=nvidia.com;\n dkim=none (message not signed); arc=none", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=Nvidia.com;\n s=selector2;\n h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck;\n bh=whPPfUGImCWDw9H8NLoASnEJAELcHjAacM0mL6bfyow=;\n b=Nx3IAZMSGBPUkeQozSZl8w0U1XlIgkTOJ5Ifo+a5oWos2I7cL6MrTclbF8V+E1kq2WlrYix/FrguVU+jATkyqXPKi7Z6OMPvTjfkd+7wlEB1t5cK3TPFAfeePSLsYMza9YhSB+PxwWDo/uRvwf94Bx2b52Er4FslZIbAkgRRWbLwzDx+qfrCEx5kM1nwtt1jd+krYsz569MBAaMsfHUDQaqih9+Fdd38jLKBVXwKEQpESBI35zg22ZNk8+UHRF8DxVIjYiSf5TVbToLEuikfXVSUVxb0Ja5GWBodT5MIg1W/WUT5AmETrjFdZn0KNMGMIjN14bhpTHYsHY5hi1A1Xg==", "X-MS-Exchange-Authentication-Results": "spf=pass (sender IP is 216.228.112.34)\n smtp.mailfrom=nvidia.com; dpdk.org; dkim=none (message not signed)\n header.d=none;dpdk.org; dmarc=pass action=none header.from=nvidia.com;", "Received-SPF": "Pass (protection.outlook.com: domain of nvidia.com designates\n 216.228.112.34 as permitted sender) receiver=protection.outlook.com;\n client-ip=216.228.112.34; helo=mail.nvidia.com;", "From": "Suanming Mou <suanmingm@nvidia.com>", "To": "<viacheslavo@nvidia.com>, <matan@nvidia.com>", "CC": "<rasland@nvidia.com>, <orika@nvidia.com>, <dev@dpdk.org>", "Date": "Tue, 6 Jul 2021 16:32:34 +0300", "Message-ID": "<20210706133257.3353-4-suanmingm@nvidia.com>", "X-Mailer": "git-send-email 2.18.1", "In-Reply-To": "<20210706133257.3353-1-suanmingm@nvidia.com>", "References": "<20210527093403.1153127-1-suanmingm@nvidia.com>\n <20210706133257.3353-1-suanmingm@nvidia.com>", "MIME-Version": "1.0", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL101.nvidia.com (172.20.187.10) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "1798d11a-fc79-4117-170d-08d94082a15d", "X-MS-TrafficTypeDiagnostic": "MW2PR12MB2378:", "X-Microsoft-Antispam-PRVS": "\n <MW2PR12MB2378DFD2813E2FEA3917CF51C11B9@MW2PR12MB2378.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:156;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n pZeIUYuEPj4KJ/a7NmxrpjDaqNFK6GisaRneMjjy7eeMf+jTPuiX7JurwsFVjz9RJRV9iiCtUfSOA2as1g9gq/PntpaRNo0EKVsIJbOjeGw4dDzd1WQtH3Sbm93CKnfXTfAgyCHOatuRr4DV5xf3Zf7jMTeYDa2uJuZdDDIV3HrRHD4Qz1PxX0eevKXMX6pAsSQLvxbxGbYGgU8apf/J6+Y1lxIPgDWJOnVLdjZ5D5jqaVs2dWtRXIK5v+AOMfOb3/rrbEwfb+LrmJM3ocDOwYXxblVxdRB553L4z0NnvZ1Z0rQcYFH9wN5mghLFdBppl0YXWcqrrzqZXi4IqbDKCxv0Xo5TRN4AQHBn770h73m+pWPddbG1zI2st3f7K2XXTRSEpBl8sTWutv27EeHx/3s+JTVKTzdZVN+S8YhEzzE9+4bUUGCcu5P/60XYS8PW+MG+5ixywt6XOr9cEBjaTWg8w4iPKNNlLEGl10xHmTEpSmnr058SiabeZSNq2bwOCUKWH36YsJKyLHy2C4m8uqCd8wQdbHwNx/Mrlw1U4NBrHIVbk5LZEevdP/WbQtfp6BBV1yLKyNOAs/9chYnzpKQy1QLlq4PU12KOJ0uoO4JgXDu7Wl8lKKiVXsk8UrqAlX5ZuIrKJAlWSF0rzE6FNi8FdsWaf/bktrPHBpUWVHSDY3eCjOIN+8D4chbyRYVckYVz1H6mZAXzpNLxnbW60Q==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(376002)(396003)(136003)(346002)(39860400002)(36840700001)(46966006)(55016002)(36860700001)(6666004)(82310400003)(8676002)(47076005)(7696005)(54906003)(478600001)(86362001)(316002)(36906005)(5660300002)(336012)(16526019)(7636003)(426003)(36756003)(70586007)(70206006)(2906002)(26005)(356005)(110136005)(6636002)(6286002)(8936002)(186003)(4326008)(2616005)(1076003)(83380400001)(82740400003);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "06 Jul 2021 13:33:24.5065 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 1798d11a-fc79-4117-170d-08d94082a15d", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT047.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MW2PR12MB2378", "Subject": "[dpdk-dev] [PATCH v4 03/26] net/mlx5: add index pool foreach define", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "In some cases, application may want to know all the allocated\nindex in order to apply some operations to the allocated index.\n\nThis commit adds the indexed pool functions to support foreach\noperation.\n\nSigned-off-by: Suanming Mou <suanmingm@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/net/mlx5/mlx5_utils.c | 96 +++++++++++++++++++++++++++++++++++\n drivers/net/mlx5/mlx5_utils.h | 8 +++\n 2 files changed, 104 insertions(+)", "diff": "diff --git a/drivers/net/mlx5/mlx5_utils.c b/drivers/net/mlx5/mlx5_utils.c\nindex 215024632d..32f8d65073 100644\n--- a/drivers/net/mlx5/mlx5_utils.c\n+++ b/drivers/net/mlx5/mlx5_utils.c\n@@ -529,6 +529,16 @@ mlx5_ipool_get_cache(struct mlx5_indexed_pool *pool, uint32_t idx)\n \t\trte_errno = ENOTSUP;\n \t\treturn NULL;\n \t}\n+\tif (unlikely(!pool->cache[cidx])) {\n+\t\tpool->cache[cidx] = pool->cfg.malloc(MLX5_MEM_ZERO,\n+\t\t\tsizeof(struct mlx5_ipool_per_lcore) +\n+\t\t\t(pool->cfg.per_core_cache * sizeof(uint32_t)),\n+\t\t\tRTE_CACHE_LINE_SIZE, SOCKET_ID_ANY);\n+\t\tif (!pool->cache[cidx]) {\n+\t\t\tDRV_LOG(ERR, \"Ipool cache%d allocate failed\\n\", cidx);\n+\t\t\treturn NULL;\n+\t\t}\n+\t}\n \tlc = mlx5_ipool_update_global_cache(pool, cidx);\n \tidx -= 1;\n \ttrunk_idx = mlx5_trunk_idx_get(pool, idx);\n@@ -839,6 +849,92 @@ mlx5_ipool_destroy(struct mlx5_indexed_pool *pool)\n \treturn 0;\n }\n \n+void\n+mlx5_ipool_flush_cache(struct mlx5_indexed_pool *pool)\n+{\n+\tuint32_t i, j;\n+\tstruct mlx5_indexed_cache *gc;\n+\tstruct rte_bitmap *ibmp;\n+\tuint32_t bmp_num, mem_size;\n+\n+\tif (!pool->cfg.per_core_cache)\n+\t\treturn;\n+\tgc = pool->gc;\n+\tif (!gc)\n+\t\treturn;\n+\t/* Reset bmp. */\n+\tbmp_num = mlx5_trunk_idx_offset_get(pool, gc->n_trunk_valid);\n+\tmem_size = rte_bitmap_get_memory_footprint(bmp_num);\n+\tpool->bmp_mem = pool->cfg.malloc(MLX5_MEM_ZERO, mem_size,\n+\t\t\t\t\t RTE_CACHE_LINE_SIZE, rte_socket_id());\n+\tif (!pool->bmp_mem) {\n+\t\tDRV_LOG(ERR, \"Ipool bitmap mem allocate failed.\\n\");\n+\t\treturn;\n+\t}\n+\tibmp = rte_bitmap_init_with_all_set(bmp_num, pool->bmp_mem, mem_size);\n+\tif (!ibmp) {\n+\t\tpool->cfg.free(pool->bmp_mem);\n+\t\tpool->bmp_mem = NULL;\n+\t\tDRV_LOG(ERR, \"Ipool bitmap create failed.\\n\");\n+\t\treturn;\n+\t}\n+\tpool->ibmp = ibmp;\n+\t/* Clear global cache. */\n+\tfor (i = 0; i < gc->len; i++)\n+\t\trte_bitmap_clear(ibmp, gc->idx[i] - 1);\n+\t/* Clear core cache. */\n+\tfor (i = 0; i < RTE_MAX_LCORE; i++) {\n+\t\tstruct mlx5_ipool_per_lcore *ilc = pool->cache[i];\n+\n+\t\tif (!ilc)\n+\t\t\tcontinue;\n+\t\tfor (j = 0; j < ilc->len; j++)\n+\t\t\trte_bitmap_clear(ibmp, ilc->idx[j] - 1);\n+\t}\n+}\n+\n+static void *\n+mlx5_ipool_get_next_cache(struct mlx5_indexed_pool *pool, uint32_t *pos)\n+{\n+\tstruct rte_bitmap *ibmp;\n+\tuint64_t slab = 0;\n+\tuint32_t iidx = *pos;\n+\n+\tibmp = pool->ibmp;\n+\tif (!ibmp || !rte_bitmap_scan(ibmp, &iidx, &slab)) {\n+\t\tif (pool->bmp_mem) {\n+\t\t\tpool->cfg.free(pool->bmp_mem);\n+\t\t\tpool->bmp_mem = NULL;\n+\t\t\tpool->ibmp = NULL;\n+\t\t}\n+\t\treturn NULL;\n+\t}\n+\tiidx += __builtin_ctzll(slab);\n+\trte_bitmap_clear(ibmp, iidx);\n+\tiidx++;\n+\t*pos = iidx;\n+\treturn mlx5_ipool_get_cache(pool, iidx);\n+}\n+\n+void *\n+mlx5_ipool_get_next(struct mlx5_indexed_pool *pool, uint32_t *pos)\n+{\n+\tuint32_t idx = *pos;\n+\tvoid *entry;\n+\n+\tif (pool->cfg.per_core_cache)\n+\t\treturn mlx5_ipool_get_next_cache(pool, pos);\n+\twhile (idx <= mlx5_trunk_idx_offset_get(pool, pool->n_trunk)) {\n+\t\tentry = mlx5_ipool_get(pool, idx);\n+\t\tif (entry) {\n+\t\t\t*pos = idx;\n+\t\t\treturn entry;\n+\t\t}\n+\t\tidx++;\n+\t}\n+\treturn NULL;\n+}\n+\n void\n mlx5_ipool_dump(struct mlx5_indexed_pool *pool)\n {\ndiff --git a/drivers/net/mlx5/mlx5_utils.h b/drivers/net/mlx5/mlx5_utils.h\nindex 0469062695..737dd7052d 100644\n--- a/drivers/net/mlx5/mlx5_utils.h\n+++ b/drivers/net/mlx5/mlx5_utils.h\n@@ -261,6 +261,9 @@ struct mlx5_indexed_pool {\n \t\t\t/* Global cache. */\n \t\t\tstruct mlx5_ipool_per_lcore *cache[RTE_MAX_LCORE];\n \t\t\t/* Local cache. */\n+\t\t\tstruct rte_bitmap *ibmp;\n+\t\t\tvoid *bmp_mem;\n+\t\t\t/* Allocate objects bitmap. Use during flush. */\n \t\t};\n \t};\n #ifdef POOL_DEBUG\n@@ -862,4 +865,9 @@ struct {\t\t\t\t\t\t\t\t\\\n \t (entry);\t\t\t\t\t\t\t\\\n \t idx++, (entry) = mlx5_l3t_get_next((tbl), &idx))\n \n+#define MLX5_IPOOL_FOREACH(ipool, idx, entry)\t\t\t\t\\\n+\tfor ((idx) = 0, mlx5_ipool_flush_cache((ipool)),\t\t\\\n+\t (entry) = mlx5_ipool_get_next((ipool), &idx);\t\t\\\n+\t (entry); idx++, (entry) = mlx5_ipool_get_next((ipool), &idx))\n+\n #endif /* RTE_PMD_MLX5_UTILS_H_ */\n", "prefixes": [ "v4", "03/26" ] }