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GET /api/patches/95134/?format=api
{ "id": 95134, "url": "https://patches.dpdk.org/api/patches/95134/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210701132609.53727-4-shirik@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210701132609.53727-4-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210701132609.53727-4-shirik@nvidia.com", "date": "2021-07-01T13:25:57", "name": "[v5,03/15] crypto/mlx5: add session operations", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "af5d756dad5555d5da10502a7d728c06b65e1df6", "submitter": { "id": 1894, "url": "https://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210701132609.53727-4-shirik@nvidia.com/mbox/", "series": [ { "id": 17580, "url": "https://patches.dpdk.org/api/series/17580/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17580", "date": "2021-07-01T13:25:54", "name": "drivers: introduce mlx5 crypto PMD", "version": 5, "mbox": "https://patches.dpdk.org/series/17580/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95134/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/95134/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id A6693A0A0C;\n\tThu, 1 Jul 2021 15:27:18 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 77E6E412F4;\n\tThu, 1 Jul 2021 15:27:14 +0200 (CEST)", "from NAM12-MW2-obe.outbound.protection.outlook.com\n (mail-mw2nam12on2088.outbound.protection.outlook.com [40.107.244.88])\n by mails.dpdk.org (Postfix) with ESMTP id 8A172412DE\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>", "Date": "Thu, 1 Jul 2021 16:25:57 +0300", "Message-ID": "<20210701132609.53727-4-shirik@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210701132609.53727-1-shirik@nvidia.com>", "References": "<20210509160507.224644-1-matan@nvidia.com>\n <20210701132609.53727-1-shirik@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "a37b9ebf-74dc-46df-32b5-08d93c93edfb", "X-MS-TrafficTypeDiagnostic": "MN2PR12MB4567:", "X-Microsoft-Antispam-PRVS": "\n <MN2PR12MB4567946C400F6D765E7C1519AA009@MN2PR12MB4567.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:8273;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n apv8LG/l+AMViGyOyMPEkULo8C6mUQP20AQzbjOwbG6JLr49O39OxZ3taM4SsFYjMF+A9dQWlh+Iqii2eojK1n08v050JF9G9gs4t6wlSsCTbNFGfcZ88il2u4ADt+Rp9Jt3Aud1S/h/n9iBJ1i5Mqlt+M5ROTwiln1nxQRlSlbUEeKXAhBvAWsrCqP3KSU5RqyQGrta2hI3b7ZZhUkmb0ExQvrdwZdiL3ANcvddX3djN98WOVYMSfG0CYlBuj42gzXzH9B49trYs+wCmDaoT8tu99LG3sxCAo9E9WnlGm3Tv5WCrdqpR9qwYtfM11MPOJcnqEqTttdcfCxDfeH3/g3HMAdTDwok9M/rNSObMimOZyB2FsArbLbJZtDvdzF96zpBx6j99RQM5qUgz+CZbML2iN6bmW/Owtf+dQNDzk6AIFnt3csxmWWa6OB4mhIhCTrKM3WTyTx08/cYwzEY9SBRIi7HVZzHCyzU6WvPv+4PWYpmCVbTs1B27K6fc72WBts4TL6tyjsj8UHdV/HkmNo+lwW6g3V1vwD6j478NzWZ6mWLuvp2pKAA/jeISt/VVxnqACi3myiJsL+uz9eFt2MHVQYEuovDj5/CN5PEGJTote7iJ3tUfmjFFsLG+EK1XsyRrqDxfdJBPsLQVHL0+pbO/O2kfJvgeHrB4TIsKsCsw7OrD11BY6/3DEwCC5RgyNlsKvjv/HNqVTF+GymBpA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(396003)(376002)(136003)(346002)(39860400002)(46966006)(36840700001)(54906003)(6916009)(36906005)(316002)(26005)(16526019)(70586007)(5660300002)(4326008)(186003)(2906002)(7696005)(336012)(426003)(2616005)(107886003)(478600001)(1076003)(6286002)(36756003)(86362001)(8676002)(83380400001)(7636003)(356005)(82310400003)(70206006)(36860700001)(82740400003)(47076005)(8936002)(55016002);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Jul 2021 13:27:09.8358 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a37b9ebf-74dc-46df-32b5-08d93c93edfb", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT042.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "MN2PR12MB4567", "Subject": "[dpdk-dev] [PATCH v5 03/15] crypto/mlx5: add session operations", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "Sessions are used in symmetric transformations in order to prepare\nobjects and data for packet processing stage.\n\nA mlx5 session includes iv_offset, pointer to mlx5_crypto_dek struct,\nbsf_size, bsf_p_type, block size index, encryption_order and encryption\nstandard.\n\nImplement the next session operations:\n mlx5_crypto_sym_session_get_size- returns the size of the mlx5\n\tsession struct.\n\tmlx5_crypto_sym_session_configure- prepares the DEK hash-list\n\tand saves all the session data.\n\tmlx5_crypto_sym_session_clear - destroys the DEK hash-list.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n doc/guides/cryptodevs/features/mlx5.ini | 5 +\n doc/guides/cryptodevs/mlx5.rst | 10 ++\n drivers/crypto/mlx5/mlx5_crypto.c | 172 +++++++++++++++++++++++-\n 3 files changed, 182 insertions(+), 5 deletions(-)", "diff": "diff --git a/doc/guides/cryptodevs/features/mlx5.ini b/doc/guides/cryptodevs/features/mlx5.ini\nindex ceadd967b6..bd757b5211 100644\n--- a/doc/guides/cryptodevs/features/mlx5.ini\n+++ b/doc/guides/cryptodevs/features/mlx5.ini\n@@ -4,12 +4,17 @@\n ; Refer to default.ini for the full list of available PMD features.\n ;\n [Features]\n+Symmetric crypto = Y\n HW Accelerated = Y\n+Cipher multiple data units = Y\n+Cipher wrapped key = Y\n \n ;\n ; Supported crypto algorithms of a mlx5 crypto driver.\n ;\n [Cipher]\n+AES XTS (128) = Y\n+AES XTS (256) = Y\n \n ;\n ; Supported authentication algorithms of a mlx5 crypto driver.\ndiff --git a/doc/guides/cryptodevs/mlx5.rst b/doc/guides/cryptodevs/mlx5.rst\nindex 05a0a449e2..dd1d1a615d 100644\n--- a/doc/guides/cryptodevs/mlx5.rst\n+++ b/doc/guides/cryptodevs/mlx5.rst\n@@ -53,6 +53,16 @@ Supported NICs\n \n * Mellanox\\ |reg| ConnectX\\ |reg|-6 200G MCX654106A-HCAT (2x200G)\n \n+\n+Limitations\n+-----------\n+\n+- AES-XTS keys provided in xform must include keytag and should be wrappend.\n+- The supported data-unit lengths are 512B and 1KB. In case the `dataunit_len`\n+ is not provided in the cipher xform, the OP length is limited to the above\n+ values and 1MB.\n+\n+\n Prerequisites\n -------------\n \ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex dfc3da3d3f..dd9685dcad 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -3,6 +3,7 @@\n */\n \n #include <rte_malloc.h>\n+#include <rte_mempool.h>\n #include <rte_errno.h>\n #include <rte_log.h>\n #include <rte_pci.h>\n@@ -20,7 +21,9 @@\n #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5\n \n #define MLX5_CRYPTO_FEATURE_FLAGS \\\n-\tRTE_CRYPTODEV_FF_HW_ACCELERATED\n+\t(RTE_CRYPTODEV_FF_SYMMETRIC_CRYPTO | RTE_CRYPTODEV_FF_HW_ACCELERATED | \\\n+\t RTE_CRYPTODEV_FF_CIPHER_WRAPPED_KEY | \\\n+\t RTE_CRYPTODEV_FF_CIPHER_MULTIPLE_DATA_UNITS)\n \n TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list =\n \t\t\t\tTAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list);\n@@ -30,6 +33,32 @@ int mlx5_crypto_logtype;\n \n uint8_t mlx5_crypto_driver_id;\n \n+const struct rte_cryptodev_capabilities mlx5_crypto_caps[] = {\n+\t{\t\t/* AES XTS */\n+\t\t.op = RTE_CRYPTO_OP_TYPE_SYMMETRIC,\n+\t\t{.sym = {\n+\t\t\t.xform_type = RTE_CRYPTO_SYM_XFORM_CIPHER,\n+\t\t\t{.cipher = {\n+\t\t\t\t.algo = RTE_CRYPTO_CIPHER_AES_XTS,\n+\t\t\t\t.block_size = 16,\n+\t\t\t\t.key_size = {\n+\t\t\t\t\t.min = 32,\n+\t\t\t\t\t.max = 64,\n+\t\t\t\t\t.increment = 32\n+\t\t\t\t},\n+\t\t\t\t.iv_size = {\n+\t\t\t\t\t.min = 16,\n+\t\t\t\t\t.max = 16,\n+\t\t\t\t\t.increment = 0\n+\t\t\t\t},\n+\t\t\t\t.dataunit_set =\n+\t\t\t\tRTE_CRYPTO_CIPHER_DATA_UNIT_LEN_512_BYTES |\n+\t\t\t\tRTE_CRYPTO_CIPHER_DATA_UNIT_LEN_4096_BYTES,\n+\t\t\t}, }\n+\t\t}, }\n+\t},\n+};\n+\n static const char mlx5_crypto_drv_name[] = RTE_STR(MLX5_CRYPTO_DRIVER_NAME);\n \n static const struct rte_driver mlx5_drv = {\n@@ -39,6 +68,49 @@ static const struct rte_driver mlx5_drv = {\n \n static struct cryptodev_driver mlx5_cryptodev_driver;\n \n+struct mlx5_crypto_session {\n+\tuint32_t bs_bpt_eo_es;\n+\t/*\n+\t * bsf_size, bsf_p_type, encryption_order and encryption standard,\n+\t * saved in big endian format.\n+\t */\n+\tuint32_t bsp_res;\n+\t/*\n+\t * crypto_block_size_pointer and reserved 24 bits saved in big endian\n+\t * format.\n+\t */\n+\tuint32_t iv_offset:16;\n+\t/* Starting point for Initialisation Vector. */\n+\tstruct mlx5_crypto_dek *dek; /* Pointer to dek struct. */\n+\tuint32_t dek_id; /* DEK ID */\n+} __rte_packed;\n+\n+static void\n+mlx5_crypto_dev_infos_get(struct rte_cryptodev *dev,\n+\t\t\t struct rte_cryptodev_info *dev_info)\n+{\n+\tRTE_SET_USED(dev);\n+\tif (dev_info != NULL) {\n+\t\tdev_info->driver_id = mlx5_crypto_driver_id;\n+\t\tdev_info->feature_flags = MLX5_CRYPTO_FEATURE_FLAGS;\n+\t\tdev_info->capabilities = mlx5_crypto_caps;\n+\t\tdev_info->max_nb_queue_pairs = 0;\n+\t\tdev_info->min_mbuf_headroom_req = 0;\n+\t\tdev_info->min_mbuf_tailroom_req = 0;\n+\t\tdev_info->sym.max_nb_sessions = 0;\n+\t\t/*\n+\t\t * If 0, the device does not have any limitation in number of\n+\t\t * sessions that can be used.\n+\t\t */\n+\t}\n+}\n+\n+static unsigned int\n+mlx5_crypto_sym_session_get_size(struct rte_cryptodev *dev __rte_unused)\n+{\n+\treturn sizeof(struct mlx5_crypto_session);\n+}\n+\n static int\n mlx5_crypto_dev_configure(struct rte_cryptodev *dev,\n \t\tstruct rte_cryptodev_config *config __rte_unused)\n@@ -61,19 +133,109 @@ mlx5_crypto_dev_close(struct rte_cryptodev *dev)\n \treturn 0;\n }\n \n+static int\n+mlx5_crypto_sym_session_configure(struct rte_cryptodev *dev,\n+\t\t\t\t struct rte_crypto_sym_xform *xform,\n+\t\t\t\t struct rte_cryptodev_sym_session *session,\n+\t\t\t\t struct rte_mempool *mp)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_crypto_session *sess_private_data;\n+\tstruct rte_crypto_cipher_xform *cipher;\n+\tuint8_t encryption_order;\n+\tint ret;\n+\n+\tif (unlikely(xform->next != NULL)) {\n+\t\tDRV_LOG(ERR, \"Xform next is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tif (unlikely((xform->type != RTE_CRYPTO_SYM_XFORM_CIPHER) ||\n+\t\t (xform->cipher.algo != RTE_CRYPTO_CIPHER_AES_XTS))) {\n+\t\tDRV_LOG(ERR, \"Only AES-XTS algorithm is supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tret = rte_mempool_get(mp, (void *)&sess_private_data);\n+\tif (ret != 0) {\n+\t\tDRV_LOG(ERR,\n+\t\t\t\"Failed to get session %p private data from mempool.\",\n+\t\t\tsess_private_data);\n+\t\treturn -ENOMEM;\n+\t}\n+\tcipher = &xform->cipher;\n+\tsess_private_data->dek = mlx5_crypto_dek_prepare(priv, cipher);\n+\tif (sess_private_data->dek == NULL) {\n+\t\trte_mempool_put(mp, sess_private_data);\n+\t\tDRV_LOG(ERR, \"Failed to prepare dek.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\tif (cipher->op == RTE_CRYPTO_CIPHER_OP_ENCRYPT)\n+\t\tencryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_MEMORY;\n+\telse\n+\t\tencryption_order = MLX5_ENCRYPTION_ORDER_ENCRYPTED_RAW_WIRE;\n+\tsess_private_data->bs_bpt_eo_es = rte_cpu_to_be_32\n+\t\t\t(MLX5_BSF_SIZE_64B << MLX5_BSF_SIZE_OFFSET |\n+\t\t\t MLX5_BSF_P_TYPE_CRYPTO << MLX5_BSF_P_TYPE_OFFSET |\n+\t\t\t encryption_order << MLX5_ENCRYPTION_ORDER_OFFSET |\n+\t\t\t MLX5_ENCRYPTION_STANDARD_AES_XTS);\n+\tswitch (xform->cipher.dataunit_len) {\n+\tcase 0:\n+\t\tsess_private_data->bsp_res = 0;\n+\t\tbreak;\n+\tcase 512:\n+\t\tsess_private_data->bsp_res = rte_cpu_to_be_32\n+\t\t\t\t\t ((uint32_t)MLX5_BLOCK_SIZE_512B <<\n+\t\t\t\t\t MLX5_BLOCK_SIZE_OFFSET);\n+\t\tbreak;\n+\tcase 4096:\n+\t\tsess_private_data->bsp_res = rte_cpu_to_be_32\n+\t\t\t\t\t ((uint32_t)MLX5_BLOCK_SIZE_4096B <<\n+\t\t\t\t\t MLX5_BLOCK_SIZE_OFFSET);\n+\t\tbreak;\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Cipher data unit length is not supported.\");\n+\t\treturn -ENOTSUP;\n+\t}\n+\tsess_private_data->iv_offset = cipher->iv.offset;\n+\tsess_private_data->dek_id =\n+\t\t\trte_cpu_to_be_32(sess_private_data->dek->obj->id &\n+\t\t\t\t\t 0xffffff);\n+\tset_sym_session_private_data(session, dev->driver_id,\n+\t\t\t\t sess_private_data);\n+\tDRV_LOG(DEBUG, \"Session %p was configured.\", sess_private_data);\n+\treturn 0;\n+}\n+\n+static void\n+mlx5_crypto_sym_session_clear(struct rte_cryptodev *dev,\n+\t\t\t struct rte_cryptodev_sym_session *sess)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\tstruct mlx5_crypto_session *spriv = get_sym_session_private_data(sess,\n+\t\t\t\t\t\t\t\tdev->driver_id);\n+\n+\tif (unlikely(spriv == NULL)) {\n+\t\tDRV_LOG(ERR, \"Failed to get session %p private data.\", spriv);\n+\t\treturn;\n+\t}\n+\tmlx5_crypto_dek_destroy(priv, spriv->dek);\n+\tset_sym_session_private_data(sess, dev->driver_id, NULL);\n+\trte_mempool_put(rte_mempool_from_obj(spriv), spriv);\n+\tDRV_LOG(DEBUG, \"Session %p was cleared.\", spriv);\n+}\n+\n static struct rte_cryptodev_ops mlx5_crypto_ops = {\n \t.dev_configure\t\t\t= mlx5_crypto_dev_configure,\n \t.dev_start\t\t\t= NULL,\n \t.dev_stop\t\t\t= NULL,\n \t.dev_close\t\t\t= mlx5_crypto_dev_close,\n-\t.dev_infos_get\t\t\t= NULL,\n+\t.dev_infos_get\t\t\t= mlx5_crypto_dev_infos_get,\n \t.stats_get\t\t\t= NULL,\n \t.stats_reset\t\t\t= NULL,\n \t.queue_pair_setup\t\t= NULL,\n \t.queue_pair_release\t\t= NULL,\n-\t.sym_session_get_size\t\t= NULL,\n-\t.sym_session_configure\t\t= NULL,\n-\t.sym_session_clear\t\t= NULL,\n+\t.sym_session_get_size\t\t= mlx5_crypto_sym_session_get_size,\n+\t.sym_session_configure\t\t= mlx5_crypto_sym_session_configure,\n+\t.sym_session_clear\t\t= mlx5_crypto_sym_session_clear,\n \t.sym_get_raw_dp_ctx_size\t= NULL,\n \t.sym_configure_raw_dp_ctx\t= NULL,\n };\n", "prefixes": [ "v5", "03/15" ] }