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GET /api/patches/95133/?format=api
{ "id": 95133, "url": "https://patches.dpdk.org/api/patches/95133/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/patch/20210701132609.53727-3-shirik@nvidia.com/", "project": { "id": 1, "url": "https://patches.dpdk.org/api/projects/1/?format=api", "name": "DPDK", "link_name": "dpdk", "list_id": "dev.dpdk.org", "list_email": "dev@dpdk.org", "web_url": "http://core.dpdk.org", "scm_url": "git://dpdk.org/dpdk", "webscm_url": "http://git.dpdk.org/dpdk", "list_archive_url": "https://inbox.dpdk.org/dev", "list_archive_url_format": "https://inbox.dpdk.org/dev/{}", "commit_url_format": "" }, "msgid": "<20210701132609.53727-3-shirik@nvidia.com>", "list_archive_url": "https://inbox.dpdk.org/dev/20210701132609.53727-3-shirik@nvidia.com", "date": "2021-07-01T13:25:56", "name": "[v5,02/15] crypto/mlx5: add DEK object management", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": true, "hash": "2136a6a51e1e669df13fe8ec8df6a4b289b6b932", "submitter": { "id": 1894, "url": "https://patches.dpdk.org/api/people/1894/?format=api", "name": "Shiri Kuzin", "email": "shirik@nvidia.com" }, "delegate": { "id": 6690, "url": "https://patches.dpdk.org/api/users/6690/?format=api", "username": "akhil", "first_name": "akhil", "last_name": "goyal", "email": "gakhil@marvell.com" }, "mbox": "https://patches.dpdk.org/project/dpdk/patch/20210701132609.53727-3-shirik@nvidia.com/mbox/", "series": [ { "id": 17580, "url": "https://patches.dpdk.org/api/series/17580/?format=api", "web_url": "https://patches.dpdk.org/project/dpdk/list/?series=17580", "date": "2021-07-01T13:25:54", "name": "drivers: introduce mlx5 crypto PMD", "version": 5, "mbox": "https://patches.dpdk.org/series/17580/mbox/" } ], "comments": "https://patches.dpdk.org/api/patches/95133/comments/", "check": "success", "checks": "https://patches.dpdk.org/api/patches/95133/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<dev-bounces@dpdk.org>", "X-Original-To": "patchwork@inbox.dpdk.org", "Delivered-To": "patchwork@inbox.dpdk.org", "Received": [ "from mails.dpdk.org (mails.dpdk.org [217.70.189.124])\n\tby inbox.dpdk.org (Postfix) with ESMTP id 674DEA0A0C;\n\tThu, 1 Jul 2021 15:27:13 +0200 (CEST)", "from [217.70.189.124] (localhost [127.0.0.1])\n\tby mails.dpdk.org (Postfix) with ESMTP id 514F6412DD;\n\tThu, 1 Jul 2021 15:27:13 +0200 (CEST)", "from NAM11-DM6-obe.outbound.protection.outlook.com\n (mail-dm6nam11on2053.outbound.protection.outlook.com [40.107.223.53])\n by mails.dpdk.org (Postfix) with ESMTP id 636F2412DD\n for <dev@dpdk.org>; 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helo=mail.nvidia.com;", "From": "Shiri Kuzin <shirik@nvidia.com>", "To": "<dev@dpdk.org>", "CC": "<matan@nvidia.com>, <gakhil@marvell.com>, <suanmingm@nvidia.com>", "Date": "Thu, 1 Jul 2021 16:25:56 +0300", "Message-ID": "<20210701132609.53727-3-shirik@nvidia.com>", "X-Mailer": "git-send-email 2.27.0", "In-Reply-To": "<20210701132609.53727-1-shirik@nvidia.com>", "References": "<20210509160507.224644-1-matan@nvidia.com>\n <20210701132609.53727-1-shirik@nvidia.com>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "8bit", "Content-Type": "text/plain", "X-Originating-IP": "[172.20.187.6]", "X-ClientProxiedBy": "HQMAIL107.nvidia.com (172.20.187.13) To\n HQMAIL107.nvidia.com (172.20.187.13)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-Office365-Filtering-Correlation-Id": "b5ffb3a2-a45e-46fb-3399-08d93c93e5ef", "X-MS-TrafficTypeDiagnostic": "BN8PR12MB3170:", "X-Microsoft-Antispam-PRVS": "\n <BN8PR12MB3170C681CA7B026906903D6CAA009@BN8PR12MB3170.namprd12.prod.outlook.com>", "X-MS-Oob-TLC-OOBClassifiers": "OLM:949;", "X-MS-Exchange-SenderADCheck": "1", "X-Microsoft-Antispam": "BCL:0;", "X-Microsoft-Antispam-Message-Info": "\n uOrKIdha8CbDIfIxC5v3HoBOdxdBKDN3Hf8bAvqLE5Z+ZXCSmI7MyInFusrcv/oqVmEBH/q9TWBzMttbo8tWS+eJjuvaBOO87AYWKtnB5L0ArLJm6Ii5m1wSirp+RBX5ZTwroHvpNZaj7Ry98cw+LbZTmfVT4VoEgo+R7jtBmwnmBdvLb5raLznhIcyCrsJU12emovKLWR0BwFCwc9OddhJXWQA3hm8Xltt8aZBGpIH3IO3+heYXYjXdv7eylgN69Gzt2t0l/HANPdyba3/ikti9i8aLItNlix+9z84nmEetKCpwxNh0gHVbYC/TIHd2+lBZnCltINipuFG6uV8PgBFR+O8aib0Lvv1epQ/M47roY0RHEsYI+xnuiHKJUdTtqaiMqa2+2OOadvLHQDwD9XB6sdeztPJCFD8qn48Z5dsOGlbtZZW61N22Pck3VzCRprW3ThjxjuK9VBVjK6ddp56Kisv0URR47LD4LKR7r/OWq8vQagHuv5am4Em6IuZveBSb/UmK8ThzrZSEWnxXjjvOlLjQfnPDMhe2258qJN4ScHwI0p2bstqU2bu58BaQ1gaGXmEvs+dUkIBljrH7/6A9KfyZ1esq7VkIXpMbaiR/uo5IMYMyXUqRnhHkYt2p//GeG+QwaUhJcPIuE64NBK7+a5cUCXxR7sCtV5WFC3KWkD64/vU15IP5kFBACJ0cva4oYA4/JTdJw05tbrH/DA==", "X-Forefront-Antispam-Report": "CIP:216.228.112.34; CTRY:US; LANG:en; SCL:1;\n SRV:;\n IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:schybrid03.nvidia.com; CAT:NONE;\n SFS:(4636009)(376002)(39860400002)(136003)(396003)(346002)(46966006)(36840700001)(4326008)(83380400001)(54906003)(336012)(426003)(36860700001)(2616005)(8676002)(2906002)(316002)(8936002)(26005)(6916009)(36756003)(107886003)(82740400003)(70206006)(5660300002)(86362001)(1076003)(55016002)(7636003)(47076005)(82310400003)(356005)(186003)(6286002)(478600001)(7696005)(16526019)(70586007);\n DIR:OUT; SFP:1101;", "X-OriginatorOrg": "Nvidia.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "01 Jul 2021 13:26:56.3364 (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n b5ffb3a2-a45e-46fb-3399-08d93c93e5ef", "X-MS-Exchange-CrossTenant-Id": "43083d15-7273-40c1-b7db-39efd9ccc17a", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.112.34];\n Helo=[mail.nvidia.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n BN8NAM11FT042.eop-nam11.prod.protection.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BN8PR12MB3170", "Subject": "[dpdk-dev] [PATCH v5 02/15] crypto/mlx5: add DEK object management", "X-BeenThere": "dev@dpdk.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "DPDK patches and discussions <dev.dpdk.org>", "List-Unsubscribe": "<https://mails.dpdk.org/options/dev>,\n <mailto:dev-request@dpdk.org?subject=unsubscribe>", "List-Archive": "<http://mails.dpdk.org/archives/dev/>", "List-Post": "<mailto:dev@dpdk.org>", "List-Help": "<mailto:dev-request@dpdk.org?subject=help>", "List-Subscribe": "<https://mails.dpdk.org/listinfo/dev>,\n <mailto:dev-request@dpdk.org?subject=subscribe>", "Errors-To": "dev-bounces@dpdk.org", "Sender": "\"dev\" <dev-bounces@dpdk.org>" }, "content": "A DEK(Data encryption Key) is an mlx5 HW object which represents the\ncipher algorithm key.\nThe DEKs are used during data encryption/decryption operations.\n\nIn symmetric algorithms like AES-STS, we use the same DEK for both\nencryption and decryption.\n\nUse the mlx5 hash-list tool to manage the DEK objects in the PMD.\n\nProvide the compare, create and destroy functions to manage DEKs in\nhash-list and introduce an internal API to setup and unset the DEK\nmanagement and to prepare and destroy specific DEK object.\n\nThe DEK hash-list will be created in dev_configure routine and\ndestroyed in dev_close routine.\n\nSigned-off-by: Shiri Kuzin <shirik@nvidia.com>\nAcked-by: Matan Azrad <matan@nvidia.com>\n---\n drivers/crypto/mlx5/meson.build | 1 +\n drivers/crypto/mlx5/mlx5_crypto.c | 42 +++++---\n drivers/crypto/mlx5/mlx5_crypto.h | 51 ++++++++++\n drivers/crypto/mlx5/mlx5_crypto_dek.c | 136 ++++++++++++++++++++++++++\n 4 files changed, 214 insertions(+), 16 deletions(-)\n create mode 100644 drivers/crypto/mlx5/mlx5_crypto.h\n create mode 100644 drivers/crypto/mlx5/mlx5_crypto_dek.c", "diff": "diff --git a/drivers/crypto/mlx5/meson.build b/drivers/crypto/mlx5/meson.build\nindex 6fd70bc477..d55cdbfe6f 100644\n--- a/drivers/crypto/mlx5/meson.build\n+++ b/drivers/crypto/mlx5/meson.build\n@@ -11,6 +11,7 @@ fmt_name = 'mlx5_crypto'\n deps += ['common_mlx5', 'eal', 'cryptodev']\n sources = files(\n \t'mlx5_crypto.c',\n+\t'mlx5_crypto_dek.c',\n )\n cflags_options = [\n \t'-std=c11',\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.c b/drivers/crypto/mlx5/mlx5_crypto.c\nindex f89d508a7e..dfc3da3d3f 100644\n--- a/drivers/crypto/mlx5/mlx5_crypto.c\n+++ b/drivers/crypto/mlx5/mlx5_crypto.c\n@@ -3,12 +3,9 @@\n */\n \n #include <rte_malloc.h>\n-#include <rte_log.h>\n #include <rte_errno.h>\n+#include <rte_log.h>\n #include <rte_pci.h>\n-#include <rte_crypto.h>\n-#include <rte_cryptodev.h>\n-#include <rte_cryptodev_pmd.h>\n \n #include <mlx5_glue.h>\n #include <mlx5_common.h>\n@@ -17,6 +14,7 @@\n #include <mlx5_common_os.h>\n \n #include \"mlx5_crypto_utils.h\"\n+#include \"mlx5_crypto.h\"\n \n #define MLX5_CRYPTO_DRIVER_NAME mlx5_crypto\n #define MLX5_CRYPTO_LOG_NAME pmd.crypto.mlx5\n@@ -24,16 +22,6 @@\n #define MLX5_CRYPTO_FEATURE_FLAGS \\\n \tRTE_CRYPTODEV_FF_HW_ACCELERATED\n \n-struct mlx5_crypto_priv {\n-\tTAILQ_ENTRY(mlx5_crypto_priv) next;\n-\tstruct ibv_context *ctx; /* Device context. */\n-\tstruct rte_pci_device *pci_dev;\n-\tstruct rte_cryptodev *crypto_dev;\n-\tvoid *uar; /* User Access Region. */\n-\tuint32_t pdn; /* Protection Domain number. */\n-\tstruct ibv_pd *pd;\n-};\n-\n TAILQ_HEAD(mlx5_crypto_privs, mlx5_crypto_priv) mlx5_crypto_priv_list =\n \t\t\t\tTAILQ_HEAD_INITIALIZER(mlx5_crypto_priv_list);\n static pthread_mutex_t priv_list_lock = PTHREAD_MUTEX_INITIALIZER;\n@@ -51,11 +39,33 @@ static const struct rte_driver mlx5_drv = {\n \n static struct cryptodev_driver mlx5_cryptodev_driver;\n \n+static int\n+mlx5_crypto_dev_configure(struct rte_cryptodev *dev,\n+\t\tstruct rte_cryptodev_config *config __rte_unused)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\n+\tif (mlx5_crypto_dek_setup(priv) != 0) {\n+\t\tDRV_LOG(ERR, \"Dek hash list creation has failed.\");\n+\t\treturn -ENOMEM;\n+\t}\n+\treturn 0;\n+}\n+\n+static int\n+mlx5_crypto_dev_close(struct rte_cryptodev *dev)\n+{\n+\tstruct mlx5_crypto_priv *priv = dev->data->dev_private;\n+\n+\tmlx5_crypto_dek_unset(priv);\n+\treturn 0;\n+}\n+\n static struct rte_cryptodev_ops mlx5_crypto_ops = {\n-\t.dev_configure\t\t\t= NULL,\n+\t.dev_configure\t\t\t= mlx5_crypto_dev_configure,\n \t.dev_start\t\t\t= NULL,\n \t.dev_stop\t\t\t= NULL,\n-\t.dev_close\t\t\t= NULL,\n+\t.dev_close\t\t\t= mlx5_crypto_dev_close,\n \t.dev_infos_get\t\t\t= NULL,\n \t.stats_get\t\t\t= NULL,\n \t.stats_reset\t\t\t= NULL,\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto.h b/drivers/crypto/mlx5/mlx5_crypto.h\nnew file mode 100644\nindex 0000000000..5a54cb0dca\n--- /dev/null\n+++ b/drivers/crypto/mlx5/mlx5_crypto.h\n@@ -0,0 +1,51 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2021 NVIDIA Corporation & Affiliates\n+ */\n+\n+#ifndef MLX5_CRYPTO_H_\n+#define MLX5_CRYPTO_H_\n+\n+#include <stdbool.h>\n+\n+#include <rte_cryptodev.h>\n+#include <rte_cryptodev_pmd.h>\n+\n+#include <mlx5_common_utils.h>\n+\n+#define MLX5_CRYPTO_DEK_HTABLE_SZ (1 << 11)\n+#define MLX5_CRYPTO_KEY_LENGTH 80\n+\n+struct mlx5_crypto_priv {\n+\tTAILQ_ENTRY(mlx5_crypto_priv) next;\n+\tstruct ibv_context *ctx; /* Device context. */\n+\tstruct rte_pci_device *pci_dev;\n+\tstruct rte_cryptodev *crypto_dev;\n+\tvoid *uar; /* User Access Region. */\n+\tuint32_t pdn; /* Protection Domain number. */\n+\tstruct ibv_pd *pd;\n+\tstruct mlx5_hlist *dek_hlist; /* Dek hash list. */\n+};\n+\n+struct mlx5_crypto_dek {\n+\tstruct mlx5_hlist_entry entry; /* Pointer to DEK hash list entry. */\n+\tstruct mlx5_devx_obj *obj; /* Pointer to DEK DevX object. */\n+\tuint8_t data[MLX5_CRYPTO_KEY_LENGTH]; /* DEK key data. */\n+\tbool size_is_48; /* Whether the key\\data size is 48 bytes or not. */\n+} __rte_cache_aligned;\n+\n+int\n+mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n+\t\t\tstruct mlx5_crypto_dek *dek);\n+\n+struct mlx5_crypto_dek *\n+mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,\n+\t\t\tstruct rte_crypto_cipher_xform *cipher);\n+\n+int\n+mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv);\n+\n+void\n+mlx5_crypto_dek_unset(struct mlx5_crypto_priv *priv);\n+\n+#endif /* MLX5_CRYPTO_H_ */\n+\ndiff --git a/drivers/crypto/mlx5/mlx5_crypto_dek.c b/drivers/crypto/mlx5/mlx5_crypto_dek.c\nnew file mode 100644\nindex 0000000000..e09c20c844\n--- /dev/null\n+++ b/drivers/crypto/mlx5/mlx5_crypto_dek.c\n@@ -0,0 +1,136 @@\n+/* SPDX-License-Identifier: BSD-3-Clause\n+ * Copyright (c) 2021 NVIDIA Corporation & Affiliates\n+ */\n+\n+#include <rte_ip.h>\n+#include <rte_common.h>\n+#include <rte_errno.h>\n+#include <rte_log.h>\n+\n+#include <mlx5_prm.h>\n+#include <mlx5_devx_cmds.h>\n+\n+#include \"mlx5_crypto_utils.h\"\n+#include \"mlx5_crypto.h\"\n+\n+struct mlx5_crypto_dek_ctx {\n+\tstruct rte_crypto_cipher_xform *cipher;\n+\tstruct mlx5_crypto_priv *priv;\n+};\n+\n+int\n+mlx5_crypto_dek_destroy(struct mlx5_crypto_priv *priv,\n+\t\t\tstruct mlx5_crypto_dek *dek)\n+{\n+\treturn mlx5_hlist_unregister(priv->dek_hlist, &dek->entry);\n+}\n+\n+struct mlx5_crypto_dek *\n+mlx5_crypto_dek_prepare(struct mlx5_crypto_priv *priv,\n+\t\t\tstruct rte_crypto_cipher_xform *cipher)\n+{\n+\tstruct mlx5_hlist *dek_hlist = priv->dek_hlist;\n+\tstruct mlx5_crypto_dek_ctx dek_ctx = {\n+\t\t.cipher = cipher,\n+\t\t.priv = priv,\n+\t};\n+\tstruct rte_crypto_cipher_xform *cipher_ctx = cipher;\n+\tuint64_t key64 = __rte_raw_cksum(cipher_ctx->key.data,\n+\t\t\t\t\t cipher_ctx->key.length, 0);\n+\tstruct mlx5_hlist_entry *entry = mlx5_hlist_register(dek_hlist,\n+\t\t\t\t\t\t\t key64, &dek_ctx);\n+\n+\treturn entry == NULL ? NULL :\n+\t\t\t container_of(entry, struct mlx5_crypto_dek, entry);\n+}\n+\n+static int\n+mlx5_crypto_dek_match_cb(struct mlx5_hlist *list __rte_unused,\n+\t\t\t struct mlx5_hlist_entry *entry,\n+\t\t\t uint64_t key __rte_unused, void *cb_ctx)\n+{\n+\tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n+\tstruct rte_crypto_cipher_xform *cipher_ctx = ctx->cipher;\n+\tstruct mlx5_crypto_dek *dek =\n+\t\t\tcontainer_of(entry, typeof(*dek), entry);\n+\tuint32_t key_len = dek->size_is_48 ? 48 : 80;\n+\n+\tif (key_len != cipher_ctx->key.length)\n+\t\treturn -1;\n+\treturn memcmp(cipher_ctx->key.data, dek->data, key_len);\n+}\n+\n+static struct mlx5_hlist_entry *\n+mlx5_crypto_dek_create_cb(struct mlx5_hlist *list __rte_unused,\n+\t\t\t uint64_t key __rte_unused, void *cb_ctx)\n+{\n+\tstruct mlx5_crypto_dek_ctx *ctx = cb_ctx;\n+\tstruct rte_crypto_cipher_xform *cipher_ctx = ctx->cipher;\n+\tstruct mlx5_crypto_dek *dek = rte_zmalloc(__func__, sizeof(*dek),\n+\t\t\t\t\t\t RTE_CACHE_LINE_SIZE);\n+\tstruct mlx5_devx_dek_attr dek_attr = {\n+\t\t.pd = ctx->priv->pdn,\n+\t\t.key_purpose = MLX5_CRYPTO_KEY_PURPOSE_AES_XTS,\n+\t\t.has_keytag = 1,\n+\t};\n+\n+\tif (dek == NULL) {\n+\t\tDRV_LOG(ERR, \"Failed to allocate dek memory.\");\n+\t\treturn NULL;\n+\t}\n+\tswitch (cipher_ctx->key.length) {\n+\tcase 48:\n+\t\tdek->size_is_48 = true;\n+\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_128b;\n+\t\tbreak;\n+\tcase 80:\n+\t\tdek->size_is_48 = false;\n+\t\tdek_attr.key_size = MLX5_CRYPTO_KEY_SIZE_256b;\n+\t\tbreak;\n+\tdefault:\n+\t\tDRV_LOG(ERR, \"Key size not supported.\");\n+\t\treturn NULL;\n+\t}\n+\tmemcpy(&dek_attr.key, cipher_ctx->key.data, cipher_ctx->key.length);\n+\tdek->obj = mlx5_devx_cmd_create_dek_obj(ctx->priv->ctx, &dek_attr);\n+\tif (dek->obj == NULL) {\n+\t\trte_free(dek);\n+\t\treturn NULL;\n+\t}\n+\tmemcpy(&dek->data, cipher_ctx->key.data, cipher_ctx->key.length);\n+\treturn &dek->entry;\n+}\n+\n+static void\n+mlx5_crypto_dek_remove_cb(struct mlx5_hlist *list __rte_unused,\n+\t\t\t struct mlx5_hlist_entry *entry)\n+{\n+\tstruct mlx5_crypto_dek *dek =\n+\t\tcontainer_of(entry, typeof(*dek), entry);\n+\n+\tclaim_zero(mlx5_devx_cmd_destroy(dek->obj));\n+\trte_free(dek);\n+}\n+\n+\n+int\n+mlx5_crypto_dek_setup(struct mlx5_crypto_priv *priv)\n+{\n+\tpriv->dek_hlist = mlx5_hlist_create(\"dek_hlist\",\n+\t\t\t\t MLX5_CRYPTO_DEK_HTABLE_SZ,\n+\t\t\t\t 0, MLX5_HLIST_WRITE_MOST |\n+\t\t\t\t MLX5_HLIST_DIRECT_KEY,\n+\t\t\t\t mlx5_crypto_dek_create_cb,\n+\t\t\t\t mlx5_crypto_dek_match_cb,\n+\t\t\t\t mlx5_crypto_dek_remove_cb);\n+\tif (priv->dek_hlist == NULL)\n+\t\treturn -1;\n+\treturn 0;\n+}\n+\n+void\n+mlx5_crypto_dek_unset(struct mlx5_crypto_priv *priv)\n+{\n+\tmlx5_hlist_destroy(priv->dek_hlist);\n+\tpriv->dek_hlist = NULL;\n+}\n", "prefixes": [ "v5", "02/15" ] }